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px4-firmware/nuttx-patches/wip_inflight_to_upstream.patch

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diff --git NuttX/nuttx/drivers/usbdev/cdcacm.c NuttX/nuttx/drivers/usbdev/cdcacm.c
index 64e2e68..15f92dd 100644
--- NuttX/nuttx/drivers/usbdev/cdcacm.c
+++ NuttX/nuttx/drivers/usbdev/cdcacm.c
@@ -243,6 +243,12 @@ static const struct uart_ops_s g_uartops =
#ifdef CONFIG_SERIAL_IFLOWCONTROL
cdcuart_rxflowcontrol, /* rxflowcontrol */
#endif
+#ifdef CONFIG_SERIAL_DMA
+ NULL, /* dmasend */
+ NULL, /* dmareceive */
+ NULL, /* dmarxfree */
+ NULL, /* dmatxavail */
+#endif
NULL, /* send */
cdcuart_txint, /* txinit */
NULL, /* txready */
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_serial.c NuttX/nuttx/arch/arm/src/stm32/stm32_serial.c
index 644c810..10919e8 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_serial.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_serial.c
@@ -1945,11 +1945,11 @@ static int up_interrupt_common(struct up_dev_s *priv)
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
- || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
+ || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT)
struct inode *inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
#endif
-#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT)
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT)
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
#endif
int ret = OK;
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 5e2ba73..adda863 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -95,10 +95,10 @@ static inline void rcc_reset(void)
putreg32(0x00000000, STM32_RCC_CFGR);
- /* Reset HSION, HSEON, CSSON and PLLON bits */
+ /* Reset HSEON, CSSON and PLLON bits */
regval = getreg32(STM32_RCC_CR);
- regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
+ regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
/* Reset PLLCFGR register to reset default */
@@ -619,11 +619,6 @@ static void stm32_stdclockconfig(void)
volatile int32_t timeout;
#ifdef STM32_BOARD_USEHSI
- /* Enable Internal High-Speed Clock (HSI) */
-
- regval = getreg32(STM32_RCC_CR);
- regval |= RCC_CR_HSION; /* Enable HSI */
- putreg32(regval, STM32_RCC_CR);
/* Wait until the HSI is ready (or until a timeout elapsed) */
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
index 73f1419..9ac38a1 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
@@ -231,12 +231,14 @@ ssize_t up_progmem_erasepage(size_t page)
return -EFAULT;
}
- /* Get flash ready and begin erasing single page */
-
+#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
return -EPERM;
}
+#endif
+
+ /* Get flash ready and begin erasing single page */
stm32_flash_unlock();
@@ -318,12 +320,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
return -EFAULT;
}
- /* Get flash ready and begin flashing */
-
+#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
return -EPERM;
}
+#endif
+
+ /* Get flash ready and begin flashing */
stm32_flash_unlock();
diff --git NuttX/nuttx/drivers/mtd/ramtron.c NuttX/nuttx/drivers/mtd/ramtron.c
index ad448c8..236084f 100644
--- NuttX/nuttx/drivers/mtd/ramtron.c
+++ NuttX/nuttx/drivers/mtd/ramtron.c
@@ -539,7 +539,7 @@ static inline int ramtron_pagewrite(struct ramtron_dev_s *priv, FAR const uint8_
finfo("page: %08lx offset: %08lx\n", (long)page, (long)offset);
-#ifndef RAMTRON_WRITEWAIT
+#ifndef CONFIG_RAMTRON_WRITEWAIT
/* Wait for any preceding write to complete. We could simplify things by
* perform this wait at the end of each write operation (rather than at
* the beginning of ALL operations), but have the wait first will slightly
@@ -574,7 +574,7 @@ static inline int ramtron_pagewrite(struct ramtron_dev_s *priv, FAR const uint8_
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
finfo("Written\n");
-#ifdef RAMTRON_WRITEWAIT
+#ifdef CONFIG_RAMTRON_WRITEWAIT
/* Wait for write completion now so we can report any errors to the caller. Thus
* the caller will know whether or not if the data is on stable storage
*/
@@ -657,13 +657,13 @@ static ssize_t ramtron_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyt
FAR uint8_t *buffer)
{
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
-#ifdef RAMTRON_WRITEWAIT
+#ifdef CONFIG_RAMTRON_WRITEWAIT
uint8_t status;
#endif
finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
-#ifndef RAMTRON_WRITEWAIT
+#ifndef CONFIG_RAMTRON_WRITEWAIT
/* Wait for any preceding write to complete. We could simplify things by
* perform this wait at the end of each write operation (rather than at
* the beginning of ALL operations), but have the wait first will slightly
@@ -690,7 +690,7 @@ static ssize_t ramtron_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyt
SPI_RECVBLOCK(priv->dev, buffer, nbytes);
-#ifdef RAMTRON_WRITEWAIT
+#ifdef CONFIG_RAMTRON_WRITEWAIT
/* Read the status register. This isn't strictly needed, but it gives us a
* chance to detect if SPI transactions are operating correctly, which
* allows us to catch complete device failures in the read path. We expect
diff --git NuttX/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h NuttX/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
index 51cca40..a7cbc46 100644
--- NuttX/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
+++ NuttX/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
@@ -93,6 +93,7 @@
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
+#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x4000288c BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff I2S2ext */
diff --git NuttX/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h NuttX/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
index 4c703be..49bfa2e 100644
--- NuttX/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
+++ NuttX/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
@@ -94,6 +94,7 @@
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff TIM13 */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
+#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x400028cc BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.c NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.c
index 13fbdb3..b2aee60 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.c
@@ -2,9 +2,10 @@
* arch/arm/src/stm32/stm32_pwr.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
- * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2015-2017 Gregory Nutt. All rights reserved.
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <gnutt@nuttx.org>
+ * David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -54,6 +55,12 @@
#if defined(CONFIG_STM32_PWR)
/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+static uint16_t g_bkp_writable_counter = 0;
+
+/************************************************************************************
* Private Functions
************************************************************************************/
@@ -115,6 +122,39 @@ void stm32_pwr_enablesdadc(uint8_t sdadc)
}
#endif
+/************************************************************************************
+ * Name: stm32_pwr_initbkp
+ *
+ * Description:
+ * Insures the referenced count access to the backup domain (RTC registers,
+ * RTC backup data registers and backup SRAM is consistent with the HW state
+ * without relying on a variable.
+ *
+ * NOTE: This function should only be called by SoC Start up code.
+ *
+ * Input Parameters:
+ * writable - True: enable ability to write to backup domain registers
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+void stm32_pwr_initbkp(bool writable)
+{
+ uint16_t regval;
+
+ /* Make the HW not writable */
+
+ regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
+ regval &= ~PWR_CR_DBP;
+ stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
+
+ /* Make the reference count agree */
+
+ g_bkp_writable_counter = 0;
+ stm32_pwr_enablebkp(writable);
+}
/************************************************************************************
* Name: stm32_pwr_enablebkp
@@ -137,7 +177,6 @@ void stm32_pwr_enablesdadc(uint8_t sdadc)
void stm32_pwr_enablebkp(bool writable)
{
- static uint16_t writable_counter = 0;
irqstate_t flags;
uint16_t regval;
bool waswritable;
@@ -152,24 +191,24 @@ void stm32_pwr_enablebkp(bool writable)
if (writable)
{
- DEBUGASSERT(writable_counter < UINT16_MAX);
- writable_counter++;
+ DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX);
+ g_bkp_writable_counter++;
}
- else if (writable_counter > 0)
+ else if (g_bkp_writable_counter > 0)
{
- writable_counter--;
+ g_bkp_writable_counter--;
}
/* Enable or disable the ability to write */
- if (waswritable && writable_counter == 0)
+ if (waswritable && g_bkp_writable_counter == 0)
{
/* Disable backup domain access */
regval &= ~PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
}
- else if (!waswritable && writable_counter > 0)
+ else if (!waswritable && g_bkp_writable_counter > 0)
{
/* Enable backup domain access */
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.h NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.h
index 700dd60..ab33eb9 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.h
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.h
@@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_pwr.h
*
- * Copyright (C) 2009, 2013, 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
+ * Copyright (C) 2009, 2013, 2015, 2017 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt <gnutt@nuttx.org>
+ * David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -85,6 +86,27 @@ void stm32_pwr_enablesdadc(uint8_t sdadc);
#endif
/************************************************************************************
+ * Name: stm32_pwr_initbkp
+ *
+ * Description:
+ * Insures the referenced count access to the backup domain (RTC registers,
+ * RTC backup data registers and backup SRAM is consistent with the HW state
+ * without relying on a variable.
+ *
+ * NOTE: This function should only be called by SoC Start up code.
+ *
+ * Input Parameters:
+ * writable - set the initial state of the enable and the
+ * bkp_writable_counter
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+void stm32_pwr_initbkp(bool writable);
+
+/************************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_rcc.c NuttX/nuttx/arch/arm/src/stm32/stm32_rcc.c
index cf3c115..71fd4f7 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_rcc.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_rcc.c
@@ -1,8 +1,9 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_rcc.c
*
- * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
+ * Copyright (C) 2009, 2011-2012, 2017 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt <gnutt@nuttx.org>
+ * David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -125,9 +126,12 @@ static inline void rcc_resetbkp(void)
/* Check if the RTC is already configured */
+ stm32_pwr_initbkp(false);
+
regval = getreg32(RTC_MAGIC_REG);
if (regval != RTC_MAGIC)
{
+
stm32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c
index bd653cf..71adbcf 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_bbsram.c
*
- * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@@ -257,7 +257,7 @@ static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
static inline void stm32_bbsram_unlock(void)
{
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
}
/****************************************************************************
@@ -277,7 +277,7 @@ static inline void stm32_bbsram_unlock(void)
static inline void stm32_bbsram_lock(void)
{
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
}
/****************************************************************************
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c
index 961eaf4..c9d2d5d 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c
@@ -2,7 +2,7 @@
* arch/arm/src/stm32f7/stm32_pwr.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
- * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved.
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
@@ -53,6 +53,12 @@
#if defined(CONFIG_STM32F7_PWR)
/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+static uint16_t g_bkp_writable_counter = 0;
+
+/************************************************************************************
* Private Functions
************************************************************************************/
@@ -76,52 +82,108 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1
************************************************************************************/
/************************************************************************************
+ * Name: stm32_pwr_initbkp
+ *
+ * Description:
+ * Insures the referenced count access to the backup domain (RTC registers,
+ * RTC backup data registers and backup SRAM is consistent with the HW state
+ * without relying on a variable.
+ *
+ * NOTE: This function should only be called by SoC Start up code.
+ *
+ * Input Parameters:
+ * writable - True: enable ability to write to backup domain registers
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+void stm32_pwr_initbkp(bool writable)
+{
+ uint16_t regval;
+
+ /* Make the HW not writable */
+
+ regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
+ regval &= ~PWR_CR1_DBP;
+ stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
+
+ /* Make the reference count agree */
+
+ g_bkp_writable_counter = 0;
+ stm32_pwr_enablebkp(writable);
+}
+
+/************************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
* Enables access to the backup domain (RTC registers, RTC backup data registers
* and backup SRAM).
*
+ * NOTE: Reference counting is used in order to supported nested calls to this
+ * function. As a consequence, every call to stm32_pwr_enablebkp(true) must
+ * be followed by a matching call to stm32_pwr_enablebkp(false).
+ *
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
- * True: The backup domain was previously writable.
+ * None
*
************************************************************************************/
-bool stm32_pwr_enablebkp(bool writable)
+void stm32_pwr_enablebkp(bool writable)
{
+ irqstate_t flags;
uint16_t regval;
bool waswritable;
+ bool wait = false;
+
+ flags = enter_critical_section();
/* Get the current state of the STM32 PWR control register */
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
waswritable = ((regval & PWR_CR1_DBP) != 0);
+ if (writable)
+ {
+ DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX);
+ g_bkp_writable_counter++;
+ }
+ else if (g_bkp_writable_counter > 0)
+ {
+ g_bkp_writable_counter--;
+ }
/* Enable or disable the ability to write */
- if (waswritable && !writable)
+ if (waswritable && g_bkp_writable_counter == 0)
{
/* Disable backup domain access */
regval &= ~PWR_CR1_DBP;
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
}
- else if (!waswritable && writable)
+ else if (!waswritable && g_bkp_writable_counter > 0)
{
/* Enable backup domain access */
regval |= PWR_CR1_DBP;
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
+ wait = true;
+ }
+
+ leave_critical_section(flags);
+
+ if (wait)
+ {
/* Enable does not happen right away */
up_udelay(4);
}
-
- return waswritable;
}
/************************************************************************************
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h
index 772851d..c80de12 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_pwr.h
*
- * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@@ -68,6 +68,27 @@ extern "C"
************************************************************************************/
/************************************************************************************
+ * Name: stm32_pwr_initbkp
+ *
+ * Description:
+ * Insures the referenced count access to the backup domain (RTC registers,
+ * RTC backup data registers and backup SRAM is consistent with the HW state
+ * without relying on a variable.
+ *
+ * NOTE: This function should only be called by SoC Start up code.
+ *
+ * Input Parameters:
+ * writable - set the initial state of the enable and the
+ * bkp_writable_counter
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+void stm32_pwr_initbkp(bool writable);
+
+/************************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
@@ -78,11 +99,11 @@ extern "C"
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
- * True: The backup domain was previously writeable.
+ * none
*
************************************************************************************/
-bool stm32_pwr_enablebkp(bool writable);
+void stm32_pwr_enablebkp(bool writable);
/************************************************************************************
* Name: stm32_pwr_enablebreg
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c
index 21cac17..a64ce09 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_rcc.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@@ -52,6 +52,7 @@
#include "chip/stm32_flash.h"
#include "stm32_rcc.h"
+#include "stm32_pwr.h"
/****************************************************************************
* Pre-processor Definitions
@@ -113,6 +114,13 @@ void stm32_clockconfig(void)
rcc_reset();
+#if defined(CONFIG_STM32F7_PWR)
+
+ /* Insure the bkp is initialized */
+
+ stm32_pwr_initbkp(false);
+#endif
+
#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c
index bd42b83..5445c01 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_rtc.c
*
- * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2015-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@@ -261,7 +261,7 @@ static void rtc_wprunlock(void)
* registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* The following steps are required to unlock the write protection on all the
* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
@@ -300,7 +300,7 @@ static inline void rtc_wprlock(void)
* data registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
}
/****************************************************************************
@@ -850,7 +850,7 @@ int up_rtc_initialize(void)
regval = getreg32(RTC_MAGIC_REG);
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
if (regval != RTC_MAGIC)
{
@@ -943,7 +943,7 @@ int up_rtc_initialize(void)
}
}
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
/* Loop, attempting to initialize/resume the RTC. This loop is necessary
* because it seems that occasionally it takes longer to initialize the
@@ -994,7 +994,7 @@ int up_rtc_initialize(void)
* backup data registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* Remember that the RTC is initialized */
@@ -1014,7 +1014,7 @@ int up_rtc_initialize(void)
* data registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
if (ret != OK && nretry > 0)
{
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