forked from Archive/PX4-Autopilot
432 lines
16 KiB
C
432 lines
16 KiB
C
/************************************************************************************
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* nuttx-configs/av-x-v1/include/board.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#pragma once
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include "stm32_rcc.h"
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#include "stm32_sdmmc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The av-x-v1 board provides the following clock sources:
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*
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* X2: 16 MHz oscillator for STM32F777NI microcontroller and Ethernet PHY.
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* X1: 32.768 KHz crystal for STM32F777NI embedded RTC
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 16 MHz RC factory-trimmed
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* LSI: 32 KHz RC
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* HSE: 16 MHz crystal for HSE
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*/
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#define STM32_BOARD_XTAL 16000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 0
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/* Main PLL Configuration.
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*
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* PLL source is HSE = 25,000,000
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*
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 2 <= PLLM <= 63
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* 192 <= PLLN <= 432
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* 192 MHz <= PLL_VCO <= 432MHz
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*
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* SYSCLK = PLL_VCO / PLLP
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* Subject to
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*
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* PLLP = {2, 4, 6, 8}
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* SYSCLK <= 216 MHz
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*
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* SDMMC and RNG Clock = PLL_VCO / PLLQ
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* Subject to
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* The SDMMC and the random number generator need a frequency lower than or equal
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* to 48 MHz to work correctly.
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*
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* 2 <= PLLQ <= 15
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*/
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/* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz
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*
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* PLL_VCO = (16,000,000 / 8) * 216 = 432 MHz
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* SYSCLK = 432 MHz / 2 = 216 MHz
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* SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 216)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
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/* Configure factors for PLLSAI clock */
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#define CONFIG_STM32F7_PLLSAI 1
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
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/* Configure Dedicated Clock Configuration Register */
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#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
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#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
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#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
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#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
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#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
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#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
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/* Configure factors for PLLI2S clock */
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#define CONFIG_STM32F7_PLLI2S 1
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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/* Configure Dedicated Clock Configuration Register 2 */
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#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
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#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
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#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
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#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
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#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
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#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
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#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
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#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
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#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
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#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
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#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
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#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
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#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
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#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
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/* Several prescalers allow the configuration of the two AHB buses, the
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* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
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* frequency of the two AHB buses is 216 MHz while the maximum frequency of
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* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
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* the low-speed APB domain is 54 MHz.
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*/
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/* AHB clock (HCLK) is SYSCLK (216 MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* SDMMC dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(118+2)=400 KHz
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*/
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/* Use the Falling edge of the SDIO_CLK clock to change the edge the
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* data and commands are change on
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*/
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#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
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#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
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* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_STM32F7_SDMMC_DMA
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# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
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* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
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*/
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//TODO #warning "Check Freq for 24mHz"
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#ifdef CONFIG_STM32F7_SDMMC_DMA
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# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA Channl/Stream Selections *****************************************************/
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/* Stream selections are arbitrary for now but might become important in the future
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* if we set aside more DMA channels/streams.
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*
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* SDMMC DMA is on DMA2
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*
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* SDMMC1 DMA
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* DMAMAP_SDMMC1_1 = Channel 4, Stream 3 <- may later be used by SPI DMA
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* DMAMAP_SDMMC1_2 = Channel 4, Stream 6
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*/
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#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1
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/* FLASH wait states
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*
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* --------- ---------- -----------
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* VDD MAX SYSCLK WAIT STATES
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* --------- ---------- -----------
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* 1.7-2.1 V 180 MHz 8
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* 2.1-2.4 V 216 MHz 9
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* 2.4-2.7 V 216 MHz 8
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* 2.7-3.6 V 216 MHz 7
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* --------- ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 7
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/* Alternate function pin selections ************************************************/
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#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
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#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
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#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
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#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
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#define GPIO_UART4_RX GPIO_UART4_RX_4 /* PD0 */
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#define GPIO_UART4_TX GPIO_UART4_TX_3 /* PA12 */
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#define GPIO_UART4_RS485_DIR GPIO_UART4_RTS_2 /* PB14 */
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#define GPIO_UART5_RX GPIO_UART5_RX_4 /* PB8 */
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#define GPIO_UART5_TX GPIO_UART5_TX_4 /* PB9 */
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#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */
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#define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */
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#define GPIO_UART7_RX GPIO_UART7_RX_1 /* PE8 */
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#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE7 */
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/* USART8: has no remap
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*
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* GPIO_UART8_RX PE0
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* GPIO_UART8_TX PE1
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*/
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/* UART RX DMA configurations */
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#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
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/* CAN
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*
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* CAN1 is routed to transceiver.
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*/
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#define GPIO_CAN1_RX GPIO_CAN1_RX_5 /* PI9 */
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */
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/* SPI
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* SPI1-SPI4 sensors
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PB5 */
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_3 /* PI2 */
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_3 /* PI3 */
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_4 /* PD3 */
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#define GPIO_SPI4_MISO GPIO_SPI4_MISO_1 /* PE5 */
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#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE6 */
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#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 /* PE2 */
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#define GPIO_SPI5_MISO GPIO_SPI5_MISO_1 /* PF8 */
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#define GPIO_SPI5_MOSI GPIO_SPI5_MOSI_2 /* PF11 */
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#define GPIO_SPI5_SCK GPIO_SPI5_SCK_2 /* PH6 */
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/* The STM32 F7 connects to a SMSC LAN8720A PHY using these pins:
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*
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* STM32 F7 BOARD LAN8720A
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* GPIO SIGNAL PIN NAME
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* -------- ------------ -------------
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* PB11 RMII_TX_EN TXEN
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* PB12 RMII_TXD0 TXD0
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* PB13 RMII_TXD1 TXD1
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* PC4 RMII_RXD0 RXD0/MODE0
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* PC5 RMII_RXD1 RXD1/MODE1
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* PD5 RMII_RXER RXER/PHYAD0
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* PA7 RMII_CRS_DV CRS_DV/MODE2
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* PC1 RMII_MDC MDC
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* PA2 RMII_MDIO MDIO
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* N/A NRST nRST
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* PA1 RMII_REF_CLK nINT/REFCLK0
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* N/A OSC_25M XTAL1/CLKIN
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*
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* The PHY address is 0, since RMII_RXER/PHYAD0 features a pull down.
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* After reset, RMII_RXER/PHYAD0 switches to the RXER function,
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* receive errors can be detected using GPIO pin PD5
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*/
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#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1
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#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_1
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#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1
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/* I2C Mapping
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*
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*/
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 /* PF1 */
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 /* PF0 */
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#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET |GPIO_PORTF | GPIO_PIN1)
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#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET |GPIO_PORTF | GPIO_PIN0)
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#define GPIO_I2C3_SCL GPIO_I2C3_SCL_2 /* PH7 */
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#define GPIO_I2C3_SDA GPIO_I2C3_SDA_2 /* PH8 */
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#define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT |GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN7)
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#define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT |GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN8)
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#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2 /* PF14 */
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#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2 /* PF15 */
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#define GPIO_I2C4_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN14)
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#define GPIO_I2C4_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN15)
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/* SDMMC1
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*
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* VDD 3.3
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* GND
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* SDMMC1_CK PC12
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* SDMMC1_CMD PD2
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* SDMMC1_D0 PC8
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* SDMMC1_D1 PC9
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* SDMMC1_D2 PC10
|
|
* SDMMC1_D3 PC11
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|
*/
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|
|
|
/************************************************************************************
|
|
* Public Data
|
|
************************************************************************************/
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
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|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
/************************************************************************************
|
|
* Public Function Prototypes
|
|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Name: stm32_boardinitialize
|
|
*
|
|
* Description:
|
|
* All STM32 architectures must provide the following entry point. This entry point
|
|
* is called early in the initialization -- after all memory has been configured
|
|
* and mapped but before any devices have been initialized.
|
|
*
|
|
************************************************************************************/
|
|
|
|
void stm32_boardinitialize(void);
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|