bae275898b
Instead of directly passing the next packet to the parser after successful parsing, switch the state to SBUS2_DECODE_STATE_SBUS_START and search for the start byte again. The timeout is increased as the IO main loop also takes a bit of time (max ~0.7ms). Tested on v5x with Futaba R7008SB (60Hz update rate) and FrSky X8R (111Hz update rate). Background: When using the Futaba R7008SB, I noticed there's additional bytes added in between packets. Often it's a null byte, but sometimes more. There's some consistency but I did not find any documentation for it. Sample data: a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 34 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 04 00 c0 8b 00 0f 04 ec 1f a8 fb 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 14 00 0f 04 ec 1f a8 fb 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 24 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 34 00 0f 05 ec 1f 30 60 bf 1c bd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 34 00 0f 07 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 04 00 03 c0 31 00 0f 05 fc 1f a8 fb 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 14 00 0f 05 fc 1f a8 fb 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 24 00 0f 04 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 34 00 0f 04 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 04 00 03 c4 00 00 0f 04 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 14 00 0f 04 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 24 00 0f 04 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 34 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 04 00 03 c0 31 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 14 00 0f 05 fc 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 24 00 0f 05 fc 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 34 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 04 00 03 c0 31 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 14 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 24 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 34 00 0f 05 f4 1f a8 fb 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 04 00 03 c4 00 00 b0 60 7f 1c bd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 14 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 24 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 34 00 0f 05 ec 1f a8 fb 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 04 00 03 c0 31 00 b0 60 bf 1c bd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 14 00 0f 04 f4 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 24 00 30 70 7f 1c bd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 34 00 0f 05 f4 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 04 00 03 c4 00 00 0f 05 fc 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 14 00 0f 05 ec 1f b0 60 bf 1c bd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 14 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 01 08 40 00 02 10 80 00 24 00 0f 05 ec 1f a8 fd 07 16 5b 81 05 d4 a0 06 20 00 This was causing the parser to skip entire packets resulting in an update rate of ~31Hz on the FMU side. With this patch the update rate increases to 42-48Hz. The investigation was triggered by an RC glitch with a packet containing random channel data. It's likely, although not completely verified that the frequent desync randomly happend to pass the CRC check with garbage data. |
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.ci | ||
.clusterfuzzlite | ||
.devcontainer | ||
.github | ||
.vscode | ||
Documentation | ||
ROMFS | ||
Tools | ||
boards | ||
cmake | ||
integrationtests/python_src/px4_it | ||
launch | ||
msg | ||
platforms | ||
posix-configs | ||
src | ||
test | ||
test_data | ||
validation | ||
.ackrc | ||
.clang-tidy | ||
.gitattributes | ||
.github_changelog_generator | ||
.gitignore | ||
.gitmodules | ||
.travis.yml | ||
.ycm_extra_conf.py | ||
CMakeLists.txt | ||
CODE_OF_CONDUCT.md | ||
CONTRIBUTING.md | ||
CTestConfig.cmake | ||
Firmware.sublime-project | ||
Jenkinsfile | ||
Kconfig | ||
LICENSE | ||
Makefile | ||
README.md | ||
appveyor.yml | ||
eclipse.cproject | ||
eclipse.project | ||
package.xml |
README.md
PX4 Drone Autopilot
This repository holds the PX4 flight control solution for drones, with the main applications located in the src/modules directory. It also contains the PX4 Drone Middleware Platform, which provides drivers and middleware to run drones.
PX4 is highly portable, OS-independent and supports Linux, NuttX and MacOS out of the box.
- Official Website: http://px4.io (License: BSD 3-clause, LICENSE)
- Supported airframes (portfolio):
- Multicopters
- Fixed wing
- VTOL
- Autogyro
- Rover
- many more experimental types (Blimps, Boats, Submarines, High altitude balloons, etc)
- Releases: Downloads
Building a PX4 based drone, rover, boat or robot
The PX4 User Guide explains how to assemble supported vehicles and fly drones with PX4. See the forum and chat if you need help!
Changing code and contributing
This Developer Guide is for software developers who want to modify the flight stack and middleware (e.g. to add new flight modes), hardware integrators who want to support new flight controller boards and peripherals, and anyone who wants to get PX4 working on a new (unsupported) airframe/vehicle.
Developers should read the Guide for Contributions. See the forum and chat if you need help!
Weekly Dev Call
The PX4 Dev Team syncs up on a weekly dev call.
Note The dev call is open to all interested developers (not just the core dev team). This is a great opportunity to meet the team and contribute to the ongoing development of the platform. It includes a QA session for newcomers. All regular calls are listed in the Dronecode calendar.
Maintenance Team
- Project: Founder
- Architecture
- Dev Call
- Communication Architecture
- UI in QGroundControl
- Multicopter Flight Control
- Multicopter Software Architecture
- VTOL Flight Control
- Fixed Wing Flight Control
- OS / NuttX
- Driver Architecture
- Commander Architecture
- UAVCAN
- State Estimation
- Vision based navigation and Obstacle Avoidance
- RTPS/ROS2 Interface
See also maintainers list (px4.io) and the contributors list (Github).
Supported Hardware
This repository contains code supporting Pixhawk standard boards (best supported, best tested, recommended choice) and proprietary boards.
Pixhawk Standard Boards
- FMUv6X and FMUv6U (STM32H7, 2021)
- Various vendors will provide FMUv6X and FMUv6U based designs Q3/2021
- FMUv5 and FMUv5X (STM32F7, 2019/20)
- FMUv4 (STM32F4, 2015)
- FMUv3 (STM32F4, 2014)
- FMUv2 (STM32F4, 2013)
Manufacturer and Community supported
- Holybro Durandal
- Hex Cube Orange
- Hex Cube Yellow
- Airmind MindPX V2.8
- Airmind MindRacer V1.2
- Bitcraze Crazyflie 2.0
- Omnibus F4 SD
- Holybro Kakute F7
- Raspberry PI with Navio 2
Additional information about supported hardware can be found in PX4 user Guide > Autopilot Hardware.
Project Roadmap
A high level project roadmap is available here.
Project Governance
The PX4 Autopilot project including all of its trademarks is hosted under Dronecode, part of the Linux Foundation.