forked from Archive/PX4-Autopilot
505 lines
34 KiB
C
505 lines
34 KiB
C
/************************************************************************************
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* arch/arm/include/stm32/chip.h
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*
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* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip and provide alternate function pin-mapping
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*
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* NOTE: Each GPIO pin may serve either for general purpose I/O or for a special
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* alternate function (such as USART, CAN, USB, SDIO, etc.). That particular
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* pin-mapping will depend on the package and STM32 family. If you are incorporating
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* a new STM32 chip into NuttX, you will need to add the pin-mapping to a header file
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* and to include that header file below. The chip-specific pin-mapping is defined in
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* the chip datasheet.
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*/
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#if defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S (?) */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 112 /* GPIOA-G */
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# define STM32_NADC 1 /* ADC1 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
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# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
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# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 0 /* No I2S (?) */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 51 /* GPIOA-D */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F103VCT6)
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
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# define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */
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# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 0 /* No I2S (?) */
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# define STM32_NUSART 5 /* USART1-5 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 80 /* GPIOA-E */
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# define STM32_NADC 3 /* ADC1-3 */
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F105VBT7)
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
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# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 80 /* GPIOA-E */
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# define STM32_NADC 2 /* ADC1-2*/
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
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# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
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# define STM32_NI2C 1 /* I2C1 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 80 /* GPIOA-E */
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# define STM32_NADC 2 /* ADC1-2*/
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F207IG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 140 /* GPIOA-I */
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# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 139 /* GPIOA-I */
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 139 /* GPIOA-I */
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
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# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NCAN 2 /* CAN1-2 */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
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# define STM32_NGPIO 139 /* GPIOA-I */
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# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */
|
|
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
|
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
|
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
|
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
|
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
|
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
|
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
|
|
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
|
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
|
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
|
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
|
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
|
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
|
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */
|
|
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
|
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
|
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
|
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
|
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
|
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
|
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
|
|
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
|
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
|
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
|
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
|
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
|
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
|
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */
|
|
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
|
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
|
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
|
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
|
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
|
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
|
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */
|
|
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
|
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
|
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
|
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
|
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
|
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
|
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
|
|
# define STM32_NFSMC 1 /* FSMC */
|
|
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
|
|
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
|
|
* 32-bit general timers TIM2 and 5 with DMA */
|
|
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
|
|
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
|
# define STM32_NDMA 2 /* DMA1-2 */
|
|
# define STM32_NSPI 3 /* SPI1-3 */
|
|
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
|
|
# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
|
|
# define STM32_NI2C 3 /* I2C1-3 */
|
|
# define STM32_NCAN 2 /* CAN1-2 */
|
|
# define STM32_NSDIO 1 /* SDIO */
|
|
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
|
|
# define STM32_NGPIO 139 /* GPIOA-I */
|
|
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
|
|
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
|
# define STM32_NCRC 1 /* CRC */
|
|
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
|
|
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
|
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
|
|
|
#else
|
|
# error "Unsupported STM32 chip"
|
|
#endif
|
|
|
|
#endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */
|
|
|