forked from Archive/PX4-Autopilot
528 lines
18 KiB
C
528 lines
18 KiB
C
/****************************************************************************
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* drivers/lcd/sd1329.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __DRIVERS_LCD_SD1329_H
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#define __DRIVERS_LCD_SD1329_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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/* SD1329 Commands **********************************************************/
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/* Set column Address.
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*
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* This triple byte command specifies column start address and end address of
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* the display data RAM. This command also sets the column address pointer to
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* column start address. This pointer is used to define the current read/write
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* column address in graphic display data RAM. If horizontal address increment
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* mode is enabled by command 0xa0, after finishing read/write one column data,
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* it is incremented automatically to the next column address. Whenever the
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* column address pointer finishes accessing the end column address, it is
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* reset back to start column address and the row address is incremented to the
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* next row.
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*
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* Byte 1: 0x15
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* Byte 2: A[5:0]: Start Address, range: 0x00-0x3f
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* Byte 3: B[5:0]: End Address, range: 0x00-0x3f
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*/
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#define SSD1329_SET_COLADDR 0x15
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/* Set Row Address.
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*
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* This triple byte command specifies row start address and end address of the
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* display data RAM. This command also sets the row address pointer to row
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* start address. This pointer is used to define the current read/write row
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* address in graphic display data RAM. If vertical address increment mode is
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* enabled by command 0xa0, after finishing read/write one row data, it is
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* incremented automatically to the next row address. Whenever the row address
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* pointer finishes accessing the end row address, it is reset back to start
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* row address.
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*
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* Byte 1: 0x75
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* Byte 2: A[6:0]: Start Address, range: 0x00-0x7f
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* Byte 3: B[6:0]: End Address, range: 0x00-0x7f
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*/
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#define SSD1329_SET_ROWADDR 0x75
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/* Set Contract Current
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*
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* This double byte command is to set Contrast Setting of the display. The
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* chip has 256 contrast steps from 0x00 to 0xff. The segment output current
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* increases linearly with the increase of contrast step.
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*
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* Byte 1: 0x81
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* Byte 2: A[7:0]: Contrast Value, range: 0-255
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*/
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#define SSD1329_SET_CONTRAST 0x81
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/* Set Second Pre-Charge Speed
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*
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* This command is used to set the speed of second pre-charge in phase 3.
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* This speed can be doubled to achieve faster pre-charging through setting
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* 0x82 A[0].
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*
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* Byte 1: 0x82
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* Byte 2: A[7:1]: Second Pre-charge Speed
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* A[0] = 1, Enable doubling the Second Pre-charge speed
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*/
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#define SSD1329_PRECHRG2_SPEED 0x82
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# define SSD1329_PRECHRG2_DBL 0x01
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/* Set Master Icon Control
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*
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* This double command is used to set the ON / OFF conditions of internal
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* charge pump, icon circuits and overall icon status.
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*
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* Byte 1: 0x90
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* Byte 2: Icon control (OR of bits 0-1,4-5)
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*/
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#define SSD1329_ICON_CONTROL 0x90
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# define SSD1329_ICON_NORMAL 0x00 /* A[1:0]1=00: Icon RESET to normal display */
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# define SSD1329_ICON_ALLON 0x01 /* A[1:0]1=01: Icon All ON */
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# define SSD1329_ICON_ALLOFF 0x02 /* A[1:0]=10: Icon All OFF */
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# define SSD1329_ICON_DISABLE 0x00 /* A[4]=0: Disable Icon display */
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# define SSD1329_ICON_ENABLE 0x10 /* A[4]=1: Enable Icon display */
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# define SSD1329_VICON_DISABLE 0x00 /* A[5]=0: Disable VICON charge pump circuit */
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# define SSD1329_VICON_ENABLE 0x20 /* A[5]=1: Enable VICON charge pump circuit */
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/* Set Icon Current Range
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*
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* This double byte command is used to set one fix current range for all icons
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* between the range of 0uA and 127.5uA. The uniformity improves as the icon
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* current range increases.
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*
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* Byte 1: 0x91
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* Byte 2: A[7:0]: Max icon current:
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* 00 = 0.0 uA
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* 01 = 0.5 uA
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* ...
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* ff = 127.5 uA
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*/
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#define SSD1329_ICON_CURRRNG 0x91
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/* Set Individual Icon Current
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*
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* This multiple byte command is used to fine tune the current for each of the
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* 64 icons. Command 0x92 followed by 64 single byte data. These 64 byte data
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* have to be entered in order to make this command function. Below is the
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* formula for calculating the icon current.
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*
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* Icon Current = Single byte value / 127 x Maximum icon current set with command 0x91
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*
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* Byte 1: 0x92
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* Byte 2-65: An[6:0]: icon current for ICSn, range: 0x00-0x7f
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* Icon Current of ICSn = An[6:0]/127) x max icon current
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*/
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#define SSD1329_ICON_CURRENT 0x92
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/* Set Individual Icon ON / OFF Register
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*
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* This double byte command is used to select one of the 64 icons and choose the
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* ON, OFF or blinking condition of the selected icon.
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*
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* Byte 1: 0x93
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* Byte 2: A[5:0]: Select one of the 64 icons from ICS0 ~ ICS63
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* A[7:6]: OFF/ON/BLINK
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*/
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#define SSD1329_ICON_SELECT 0x93
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# define SSD1329_ICON_OFF 0x00
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# define SSD1329_ICON_ON 0x40
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# define SSD1329_ICON_BLINK 0xc0
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/* Set Icon ON / OFF Registers
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*
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* This double byte command is used to set the ON / OFF status of all 64 icons.
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*
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* Byte 1: 0x94
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* Byte 2: A[7:6]: OFF/ON/BLINK (Same as 0x93)
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*/
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#define SSD1329_ICON_ALL 0x94
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/* Set Icon Blinking Cycle
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*
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* This double byte command is used to set icon oscillator frequency and
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* blinking cycle selected with above command 0x93.
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*
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* Byte 1: 0x95
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* Byte 2:
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* - A[2:0]:Icon Blinking cycle
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* - A[5:4]:Icon oscillation frequency
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*/
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#define SSD1329_ICON_BLINKING 0x95
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# define SSD1329_ICON_BLINK_0p25S 0x00 /* 0.25 sec */
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# define SSD1329_ICON_BLINK_0p50S 0x01 /* 0.50 sec */
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# define SSD1329_ICON_BLINK_0p75S 0x02 /* 0.75 sec */
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# define SSD1329_ICON_BLINK_0p100S 0x03 /* 1.00 sec */
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# define SSD1329_ICON_BLINK_0p125S 0x04 /* 1.25 sec */
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# define SSD1329_ICON_BLINK_0p150S 0x05 /* 1.50 sec */
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# define SSD1329_ICON_BLINK_0p175S 0x06 /* 1.75 sec */
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# define SSD1329_ICON_BLINK_0p200S 0x07 /* 2.00 sec */
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# define SSD1329_ICON_BLINK_61KHZ 0x00 /* 61 KHz */
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# define SSD1329_ICON_BLINK_64KHZ 0x10 /* 64 KHz */
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# define SSD1329_ICON_BLINK_68KHZ 0x20 /* 68 KHz */
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# define SSD1329_ICON_BLINK_73KHZ 0x30 /* 73 KHz */
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/* Set Icon Duty
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*
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* This double byte command is used to set the icon frame frequency and icon AC
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* drive duty ratio.
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*
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* Byte 1: 0x96
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* Byte 2:
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* - A[2:0]: AC Drive
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* - A[7:4]: con frame frequency
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*/
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#define SSD1329_ICON_ACDRIVE 0x96
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# define SSD1329_ICON_DUTY_DC 0x00
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# define SSD1329_ICON_DUTY_63_64 0x01
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# define SSD1329_ICON_DUTY_62_64 0x02
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# define SSD1329_ICON_DUTY_61_64 0x03
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# define SSD1329_ICON_DUTY_60_64 0x04
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# define SSD1329_ICON_DUTY_59_64 0x05
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# define SSD1329_ICON_DUTY_58_64 0x06
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# define SSD1329_ICON_DUTY_57_64 0x07
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/* Set Re-map
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*
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* This double command has multiple configurations and each bit setting is
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* described as follows:
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*
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* Column Address Remapping (A[0])
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* This bit is made for increase the flexibility layout of segment signals in
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* OLED module with segment arranged from left to right (when A[0] is set to 0)
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* or from right to left (when A[0] is set to 1).
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*
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* Nibble Remapping (A[1])
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* When A[1] is set to 1, the two nibbles of the data bus for RAM access are
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* re-mapped, such that (D7, D6, D5, D4, D3, D2, D1, D0) acts like (D3, D2, D1,
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* D0, D7, D6, D5, D4) If this feature works together with Column Address
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* Re-map, it would produce an effect of flipping the outputs from SEG0-127 to
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* SEG127-SEG0.
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*
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* Address increment mode (A[2])
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* When A[2] is set to 0, the driver is set as horizontal address incremen
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* mode. After the display RAM is read/written, the column address pointer is
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* increased automatically by 1. If the column address pointer reaches column
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* end address, the column address pointer is reset to column start address and
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* row address pointer is increased by 1.
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*
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* When A[2] is set to 1, the driver is set to vertical address increment mode.
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* After the display RAM is read/written, the row address pointer is increased
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* automatically by 1. If the row address pointer reaches the row end address,
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* the row address pointer is reset to row start address and column address
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* pointer is increased by 1.
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*
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* COM Remapping (A[4])
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* This bit defines the scanning direction of the common for flexible layout
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* of common signals in OLED module either from up to down (when A[4] is set to
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* 0) or from bottom to up (when A[4] is set to 1).
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*
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* Splitting of Odd / Even COM Signals (A[6])
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* This bit is made to match the COM layout connection on the panel. When A[6]
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* is set to 0, no splitting odd / even of the COM signal is performed. When
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* A[6] is set to 1, splitting odd / even of the COM signal is performed,
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* output pin assignment sequence is shown as below (for 128MUX ratio):
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*
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* Byte 1: 0xa0
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* Byte 2: A[7:0]
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*/
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#define SSD1329_GDDRAM_REMAP 0xa0
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# define SSD1329_COLADDR_REMAP 0x01 /* A[0]: Enable column re-map */
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# define SSD1329_NIBBLE_REMAP 0x02 /* A[1]: Enable nibble re-map */
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# define SSD1329_VADDR_INCR 0x04 /* A[1]: Enable vertical address increment */
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# define SSD1329_COM_REMAP 0x10 /* A[4]: Enable COM re-map */
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# define SSD1329_COM_SPLIT 0x40 /* A[6]: Enable COM slip even/odd */
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/* Set Display Start Line
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*
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* This double byte command is to set Display Start Line register for
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* determining the starting address of display RAM to be displayed by selecting
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* a value from 0 to 127.
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*
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* Byte 1: 0xa1
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* Byte 2: A[6:0]: Vertical scroll by setting the starting address of
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* display RAM from 0-127
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*/
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#define SSD1329_VERT_START 0xa1
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/* Set Display Offset
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*
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* This double byte command specifies the mapping of display start line (it is
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* assumed that COM0 is the display start line, display start line register
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* equals to 0) to one of COM0-COM127.
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*
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* Byte 1: 0xa2
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* Byte 2: A[6:0]: Set vertical offset by COM from 0-127
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*/
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#define SSD1329_VERT_OFFSET 0xa2
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/* Set Display Mode - Normal, all on, all off, inverse
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*
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* These are single byte commands and are used to set display status to Normal
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* Display, Entire Display ON, Entire Display OFF or Inverse Display.
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*
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* Normal Display (0xa4)
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* Reset the <20>Entire Display ON, Entire Display OFF or Inverse Display<61> effects
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* and turn the data to ON at the corresponding gray level.
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*
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* Set Entire Display ON (0xa5)
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* Force the entire display to be at gray scale level GS15, regardless of the
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* contents of the display data RAM.
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*
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* Set Entire Display OFF (0xa6)
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* Force the entire display to be at gray scale level GS0, regardless of the
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* contents of the display data RAM.
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*
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* Inverse Display (0xa7)
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* The gray scale level of display data are swapped such that <20>GS0<53> <-> <20>GS15<31>,
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* <20>GS1<53> <-> <20>GS14<31>, etc.
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*
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* Byte 1: Display mode command
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*/
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#define SSD1329_DISP_NORMAL 0xa4
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#define SSD1329_DISP_OFF 0xa5
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#define SSD1329_DISP_ON 0xa6
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#define SSD1329_DISP_INVERT 0xa7
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/* Set MUX Ratio
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*
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* This double byte command sets multiplex ratio (MUX ratio) from 16MUX to
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* 128MUX. In POR, multiplex ratio is 128MUX.
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*
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* Byte 1: 0xa8
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* Byte 2: A[6:0] 15-127 representing 16-128 MUX
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*/
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#define SSD1329_MUX_RATIO 0xa8
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/* Set Sleep mode ON / OFF
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*
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* These single byte commands are used to turn the matrix display on the OLED
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* panel display either ON or OFF. When the sleep mode is set to ON (0xae), the
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* display is OFF, the segment and common output are in high impedance state
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* and circuits will be turned OFF. When the sleep mode is set to OFF (0xaf),
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* the display is ON.
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*
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* Byte 1: sleep mode command
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*/
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#define SSD1329_SLEEP_ON 0xae
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#define SSD1329_SLEEP_OFF 0xaf
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/* Set Phase Length
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*
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* In the second byte of this double command, lower nibble and higher nibble is
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* defined separately. The lower nibble adjusts the phase length of Reset (phase
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* 1). The higher nibble is used to select the phase length of first pre-charge
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* phase (phase 2). The phase length is ranged from 1 to 16 DCLK's. RESET for
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* A[3:0] is set to 3 which means 4 DCLK<4C>s selected for Reset phase. POR for
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* A[7:4] is set to 5 which means 6 DCLK<4C>s is selected for first pre-charge
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* phase. Please refer to Table 9-1 for detail breakdown levels of each step.
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*
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* Byte 1: 0xb1
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* Byte 2: A[3:0]: Phase 1 period of 1~16 DCLK<4C>s
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* A[7:4]: Phase 2 period of 1~16 DCLK<4C>s
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*/
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#define SSD1329_PHASE_LENGTH 0xb1
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/* Set Frame Frequency
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*
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* This double byte command is used to set the number of DCLK<4C>s per row between
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* the range of 0x14 and 0x7f. Then the Frame frequency of the matrix display
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* is equal to DCLK frequency / A[6:0].
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*
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* Byte 1: 0xb2
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* Byte 2: A[6:0]:Total number of DCLK<4C>s per row. Ranging from
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* 0x14 to 0x4e DCLK<4C>s. frame Frequency = DCLK freq /A[6:0].
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*/
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#define SSD1329_FRAME_FREQ 0xb2
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/* Set Front Clock Divider / Oscillator Frequency
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*
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* This double command is used to set the frequency of the internal display
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* clocks, DCLK's. It is defined by dividing the oscillator frequency by the
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* divide ratio (Value from 1 to 16). Frame frequency is determined by divide
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* ratio, number of display clocks per row, MUX ratio and oscillator frequency.
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* The lower nibble of the second byte is used to select the oscillator
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* frequency. Please refer to Table 9-1 for detail breakdown levels of each
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* step.
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*
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* Byte 1: 0xb3
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* Byte 2: A[3:0]: Define divide ratio (D) of display clock (DCLK)
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* Divide ratio=A[3:0]+1
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* A[7:4] : Set the Oscillator Frequency, FOSC. Range:0-15
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*/
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#define SSD1329_DCLK_DIV 0xb3
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/* Set Default Gray Scale Table
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*
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* This single byte command is used to set the gray scale table to initial
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* default setting.
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*
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* Byte 1: 0xb7
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*/
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#define SSD1329_GSCALE_TABLE 0xb7
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/* Look Up Table for Gray Scale Pulse width
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*
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* This command is used to set each individual gray scale level for the display.
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* Except gray scale level GS0 that has no pre-charge and current drive, each
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* gray scale level is programmed in the length of current drive stage pulse
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* width with unit of DCLK. The longer the length of the pulse width, the
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* brighter the OLED pixel when it<69>s turned ON.
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*
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* The setting of gray scale table entry can perform gamma correction on OLED
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* panel display. Normally, it is desired that the brightness response of the
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* panel is linearly proportional to the image data value in display data RAM.
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* However, the OLED panel is somehow responded in non-linear way. Appropriate
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* gray scale table setting like example below can compensate this effect.
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*
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* Byte 1: 0xb8
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* Bytes 2-16: An[5:0], value for GSn level Pulse width
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*/
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#define SSD1329_GSCALE_LOOKUP 0xb8
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/* Set Second Pre-charge Period
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*
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* This double byte command is used to set the phase 3 second pre-charge period.
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* The period of phase 3 can be programmed by command 0xbb and it is ranged from
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* 0 to 15 DCLK's.
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*
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* Byte 1: 0xbb
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* Byte 2: 0-15 DCLKs
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*/
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#define SSD1329_PRECHRG2_PERIOD 0xbb
|
||
|
||
/* Set First Precharge voltage, VP
|
||
*
|
||
* This double byte command is used to set phase 2 first pre-charge voltage
|
||
* level. It can be programmed to set the first pre-charge voltage reference to
|
||
* VCC or VCOMH.
|
||
*
|
||
* Byte 1: 0xbc
|
||
* Byte 2: A[5] == 0, Pre-charge voltage is (0.30 + A[4:0]) * Vcc
|
||
* A{5] == 1, 1.00 x VCC or connect to VCOMH if VCC > VCOMH
|
||
*/
|
||
|
||
#define SSD1329_PRECHRG1_VOLT 0xbc
|
||
|
||
/* Set VCOMH
|
||
*
|
||
* This double byte command sets the high voltage level of common pins, VCOMH.
|
||
* The level of VCOMH is programmed with reference to VCC.
|
||
*
|
||
* Byte 1: 0xbe
|
||
* Byte 2: (0.51 + A[5:0]) * Vcc
|
||
*/
|
||
|
||
#define SSD1329_COM_HIGH 0xbe
|
||
|
||
/* NOOP
|
||
*
|
||
* This is a no operation command.
|
||
*
|
||
* Byte 1: 0xe3
|
||
*/
|
||
|
||
#define SSD1329_NOOP 0xe3
|
||
|
||
/* Set Command Lock
|
||
*
|
||
* This command is used to lock the MCU from accepting any command.
|
||
*
|
||
* Byte 1: 0xfd
|
||
* Byte 2: 0x12 | A[2]
|
||
* A[2] == 1, Enable locking the MCU from entering command
|
||
*/
|
||
|
||
#define SSD1329_CMD_LOCK 0xfd
|
||
# define SSD1329_LOCK_ON 0x13
|
||
# define SSD1329_LOCK_OFF 0x12
|
||
|
||
/* SD1329 Status ************************************************************/
|
||
|
||
#define SDD1329_STATUS_ON 0x00 /* D[6]=0: indicates the display is ON */
|
||
#define SDD1329_STATUS_OFF 0x40 /* D[6]=1: indicates the display is OFF */
|
||
|
||
/****************************************************************************
|
||
* Public Types
|
||
****************************************************************************/
|
||
|
||
/****************************************************************************
|
||
* Public Functions
|
||
****************************************************************************/
|
||
|
||
#undef EXTERN
|
||
#if defined(__cplusplus)
|
||
#define EXTERN extern "C"
|
||
extern "C" {
|
||
#else
|
||
#define EXTERN extern
|
||
#endif
|
||
|
||
#undef EXTERN
|
||
#if defined(__cplusplus)
|
||
}
|
||
#endif
|
||
#endif /* __DRIVERS_LCD_SD1329_H */
|