forked from Archive/PX4-Autopilot
507 lines
19 KiB
C
507 lines
19 KiB
C
/************************************************************************************
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* nuttx-configs/spracing/h7extreme/include/board.h
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*
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* Copyright (C) 2016-2020 Gregory Nutt. All rights reserved.
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* Authors: Igor Misic <igy1000mb@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __NUTTX_CONFIG_SPRACING_H7EXTREME_INCLUDE_BOARD_H
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#define __NUTTX_CONFIG_SPRACING_H7EXTREME_INCLUDE_BOARD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include "board_dma_map.h"
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include "stm32_rcc.h"
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#include "stm32_sdmmc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The sp racing h7 extreme board provides the following clock sources:
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*
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* X1: 8 MHz crystal for HSE
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 64 MHz RC factory-trimmed
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* HSE: 8 MHz crystal for HSE
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE = 8,000,000
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*
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* PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 1 <= PLLM <= 63
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* 4 <= PLLN <= 512
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* 150 MHz <= PLL_VCOL <= 420MHz
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* 192 MHz <= PLL_VCOH <= 836MHz
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*
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* SYSCLK = PLL_VCO / PLLP
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* CPUCLK = SYSCLK / D1CPRE
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* Subject to
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*
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* PLLP1 = {2, 4, 6, 8, ..., 128}
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* PLLP2,3 = {2, 3, 4, ..., 128}
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* CPUCLK <= 480 MHz
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*/
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#define STM32_BOARD_USEHSE
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#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE
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/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
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*
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* PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz
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*
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* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
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* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz
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* PLL1R = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz - locked for H750
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*/
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#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVP1EN | \
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RCC_PLLCFGR_DIVQ1EN | \
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RCC_PLLCFGR_DIVR1EN)
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#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2)
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#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(200)
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#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2)
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#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4)
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#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(2)
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#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200)
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#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
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#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
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#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
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/* PLL2 */
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#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVP2EN | \
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RCC_PLLCFGR_DIVQ2EN | \
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RCC_PLLCFGR_DIVR2EN)
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#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(4)
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#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(260)
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#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(2)
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#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(10)
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#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(2)
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#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 260)
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#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2)
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#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 10)
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#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 2)
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/* PLL3 */
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#define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL3RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVP3EN | \
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RCC_PLLCFGR_DIVQ3EN | \
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RCC_PLLCFGR_DIVR3EN)
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#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(2)
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#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(50)
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#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2)
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#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(2)
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#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(2)
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#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 50)
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#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 2)
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#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 2)
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#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 2)
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/* SYSCLK = PLL1P = 400MHz
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* CPUCLK = SYSCLK / 1 = 400 MHz
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*/
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#define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK)
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#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY)
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#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1)
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/* Configure Clock Assignments */
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/* AHB clock (HCLK) is SYSCLK/2 (200 MHz max)
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* HCLK1 = HCLK2 = HCLK3 = HCLK4 = 200
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*/
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#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */
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#define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */
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#define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/2 (100 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB2 clock (PCLK2) is HCLK/2 (50 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB3 clock (PCLK3) is HCLK/2 (50 MHz) */
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#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd2 /* PCLK3 = HCLK / 2 */
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#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB4 clock (PCLK4) is HCLK/4 (50 MHz) */
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#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd2 /* PCLK4 = HCLK / 2 */
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#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timer clock frequencies */
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Kernel Clock Configuration
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*
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* Note: look at Table 54 in ST Manual
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*/
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/* I2C123 clock source */
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#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI
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/* SPI123 clock source */
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#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1
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/* SPI45 clock source */
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#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_APB
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/* USB 1 and 2 clock source */
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#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48
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/* ADC 1 2 3 clock source */
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#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
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/* QSPI clock source */
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#define STM32_RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_PLL2
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/* FLASH wait states
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*
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* ------------ ---------- -----------
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* Vcore MAX ACLK WAIT STATES
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* ------------ ---------- -----------
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* 1.15-1.26 V 70 MHz 0
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* (VOS1 level) 140 MHz 1
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* 210 MHz 2
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* 1.05-1.15 V 55 MHz 0
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* (VOS2 level) 110 MHz 1
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* 165 MHz 2
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* 220 MHz 3
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* 0.95-1.05 V 45 MHz 0
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* (VOS3 level) 90 MHz 1
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* 135 MHz 2
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* 180 MHz 3
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* 225 MHz 4
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* ------------ ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 2
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/* SDMMC definitions ********************************************************/
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/* Init 400kHz, freq = PLL1Q/(2*div) div = PLL1Q/(2*freq) */
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#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div = PLL1Q/(2*freq)
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* div = 4.8 = 240 / 50, So round up to 5 for default speed 24 MB/s
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*/
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#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA)
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# define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_MMCXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA)
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# define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_SDXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
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/* LED definitions ******************************************************************/
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/* The sp racing h7 extreme board has three, LED_GREEN a Green LED, LED_BLUE
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* Red LED can be controlled by software.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
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* The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_NLEDS 1
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#define BOARD_LED_RED BOARD_LED1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
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* events as follows:
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*
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*
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* SYMBOL Meaning LED state
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* Red Green Blue
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* ---------------------- -------------------------- ------ ------ ----*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
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#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */
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/* Alternate function pin selections ************************************************/
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#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PB15 */
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#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PB14 */
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#define GPIO_USART2_RX 0 /* Not in use */
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#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
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#define GPIO_UART4_RX GPIO_UART4_RX_5 /* PD0 */
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#define GPIO_UART4_TX GPIO_UART4_TX_5 /* PD1 */
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#define GPIO_UART5_RX GPIO_UART5_RX_2 /* PB5 */
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#define GPIO_UART5_TX GPIO_UART5_TX_1 /* PB13 */
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#define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */
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#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */
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#define GPIO_UART8_RX GPIO_UART8_RX_1 /* PE0 */
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#define GPIO_UART8_TX GPIO_UART8_TX_1 /* PE1 */
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/* SPI
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* SPI2 is gyro 1
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* SPI3 is gyro 2
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* SPI4 is BARO
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*/
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//#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
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//#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_3 /* PD7 */
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//#define GPIO_SPI1_SCK GPIO_SPI1_SCK_3 /* PG11 */
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_2 /* PC2 */
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_3 /* PC3 */
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_5 /* PD3 */
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#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 /* PB4 */
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#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_1 /* PD6 */
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#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 /* PB3 */
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#define GPIO_SPI4_MISO GPIO_SPI4_MISO_1 /* PE13 */
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#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE14 */
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#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 /* PE12 */
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/* I2C
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*
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* Each I2C is associated with a U[S]ART
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* hence the naming I2C2_SDA_UART4 in FMU USAGE spreadsheet
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*
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* The optional _GPIO configurations allow the I2C driver to manually
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* reset the bus to clear stuck slaves. They match the pin configuration,
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* but are normally-high GPIOs.
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*
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*/
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */
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#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN8)
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#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
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/* SDMMC1
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*
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* VDD 3.3
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* GND
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* SDMMC1_CK PC12
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* SDMMC1_CMD PD2
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* SDMMC1_D0 PC8
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* SDMMC1_D1 PC9
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* SDMMC1_D2 PC10
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* SDMMC1_D3 PC11
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* GPIO_SDMMC1_NCD PG0
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*/
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|
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/* USB
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*
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* OTG_FS_DM PA11
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* OTG_FS_DP PA12
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* VBUS PA9
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*/
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|
|
|
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/* Board provides GPIO or other Hardware for signaling to timing analyzer */
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|
|
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#if defined(CONFIG_BOARD_USE_PROBES)
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# include "stm32_gpio.h"
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# define PROBE_N(n) (1<<((n)-1))
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# define PROBE_1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN14) /* PE14 AUX1 */
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# define PROBE_2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN10) /* PA10 AUX2 */
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# define PROBE_3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11) /* PE11 AUX3 */
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# define PROBE_4 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9) /* PE9 AUX4 */
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# define PROBE_5 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN13) /* PD13 AUX5 */
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# define PROBE_6 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN14) /* PD14 FMU_CAP6 */
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# define PROBE_7 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN6) /* PH6 FMU_CAP5 */
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# define PROBE_8 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN9) /* PH9 FMU_CAP4 */
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# define PROBE_9 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN5) /* PA5 FMU_CAP3 */
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# define PROBE_10 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN3) /* PB3 FMU_CAP2 */
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|
# define PROBE_11 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN11) /* PB11 FMU_CAP1 */
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|
|
|
# define PROBE_INIT(mask) \
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|
do { \
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if ((mask)& PROBE_N(1)) { stm32_configgpio(PROBE_1); } \
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if ((mask)& PROBE_N(2)) { stm32_configgpio(PROBE_2); } \
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if ((mask)& PROBE_N(3)) { stm32_configgpio(PROBE_3); } \
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if ((mask)& PROBE_N(4)) { stm32_configgpio(PROBE_4); } \
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if ((mask)& PROBE_N(5)) { stm32_configgpio(PROBE_5); } \
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if ((mask)& PROBE_N(6)) { stm32_configgpio(PROBE_6); } \
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if ((mask)& PROBE_N(7)) { stm32_configgpio(PROBE_7); } \
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if ((mask)& PROBE_N(8)) { stm32_configgpio(PROBE_8); } \
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if ((mask)& PROBE_N(9)) { stm32_configgpio(PROBE_9); } \
|
|
if ((mask)& PROBE_N(10)) { stm32_configgpio(PROBE_10); } \
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|
if ((mask)& PROBE_N(11)) { stm32_configgpio(PROBE_11); } \
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|
} while(0)
|
|
|
|
# define PROBE(n,s) do {stm32_gpiowrite(PROBE_##n,(s));}while(0)
|
|
# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true)
|
|
#else
|
|
# define PROBE_INIT(mask)
|
|
# define PROBE(n,s)
|
|
# define PROBE_MARK(n)
|
|
#endif
|
|
|
|
/* QSPI configuration */
|
|
|
|
#define CONFIG_STM32H7_QUADSPI
|
|
#define CONFIG_STM32H7_QSPI_FLASH_SIZE 16777216 /* bytes */
|
|
#define CONFIG_STM32H7_QSPI_FIFO_THESHOLD 1
|
|
#define CONFIG_STM32H7_QSPI_CSHT 1 /* HIGH TIME 1 CYCLE */
|
|
|
|
#define GPIO_QSPI_CS GPIO_QUADSPI_BK1_NCS_3 /* PB10 */
|
|
#define GPIO_QSPI_IO0 GPIO_QUADSPI_BK1_IO0_3 /* PD11 */
|
|
#define GPIO_QSPI_IO1 GPIO_QUADSPI_BK1_IO1_3 /* PD12 */
|
|
#define GPIO_QSPI_IO2 GPIO_QUADSPI_BK1_IO2_1 /* PE2 */
|
|
#define GPIO_QSPI_IO3 GPIO_QUADSPI_BK1_IO3_2 /* PD13 */
|
|
#define GPIO_QSPI_SCK GPIO_QUADSPI_CLK_1 /* PB2 */
|
|
|
|
/************************************************************************************
|
|
* Public Data
|
|
************************************************************************************/
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
/************************************************************************************
|
|
* Public Function Prototypes
|
|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Name: stm32_boardinitialize
|
|
*
|
|
* Description:
|
|
* All STM32 architectures must provide the following entry point. This entry point
|
|
* is called early in the initialization -- after all memory has been configured
|
|
* and mapped but before any devices have been initialized.
|
|
*
|
|
************************************************************************************/
|
|
|
|
void stm32_boardinitialize(void);
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /*__NUTTX_CONFIG_SPRACING_H7EXTREME_INCLUDE_BOARD_H */
|