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pr-qmc5883
Author | SHA1 | Date |
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Daniel Agar | b147f8d811 |
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@ -52,6 +52,7 @@ QMC5883L::~QMC5883L()
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perf_free(_reset_perf);
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perf_free(_bad_register_perf);
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perf_free(_bad_transfer_perf);
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perf_free(_overflow_perf);
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}
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int QMC5883L::init()
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@ -81,6 +82,7 @@ void QMC5883L::print_status()
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perf_print_counter(_reset_perf);
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perf_print_counter(_bad_register_perf);
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perf_print_counter(_bad_transfer_perf);
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perf_print_counter(_overflow_perf);
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}
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int QMC5883L::probe()
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@ -137,8 +139,8 @@ void QMC5883L::RunImpl()
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ScheduleDelayed(100_ms);
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} else {
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PX4_DEBUG("Reset not complete, check again in 10 ms");
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ScheduleDelayed(10_ms);
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PX4_DEBUG("Reset not complete, check again in 100 ms");
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ScheduleDelayed(100_ms);
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}
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}
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@ -180,32 +182,35 @@ void QMC5883L::RunImpl()
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uint8_t cmd = static_cast<uint8_t>(Register::X_LSB);
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if (transfer(&cmd, 1, (uint8_t *)&buffer, sizeof(buffer)) == PX4_OK) {
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// process data if successful transfer, no overflow
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if ((buffer.STATUS & STATUS_BIT::OVL) == 0) {
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int16_t x = combine(buffer.X_MSB, buffer.X_LSB);
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int16_t y = combine(buffer.Y_MSB, buffer.Y_LSB);
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int16_t z = combine(buffer.Z_MSB, buffer.Z_LSB);
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if (x != _prev_data[0] || y != _prev_data[1] || z != _prev_data[2]) {
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_prev_data[0] = x;
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_prev_data[1] = y;
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_prev_data[2] = z;
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const int16_t x = combine(buffer.X_MSB, buffer.X_LSB);
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const int16_t y = combine(buffer.Y_MSB, buffer.Y_LSB);
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const int16_t z = combine(buffer.Z_MSB, buffer.Z_LSB);
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// Sensor orientation
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// Forward X := +X
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// Right Y := -Y
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// Down Z := -Z
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y = (y == INT16_MIN) ? INT16_MAX : -y; // -y
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z = (z == INT16_MIN) ? INT16_MAX : -z; // -z
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const bool data_ready = (buffer.STATUS & STATUS_BIT::DRDY);
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const bool overflow = (buffer.STATUS & STATUS_BIT::OVL);
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_px4_mag.update(now, x, y, z);
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const bool data_changed = ((x != _prev_data[0] || y != _prev_data[1] || z != _prev_data[2]));
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_prev_data[0] = x;
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_prev_data[1] = y;
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_prev_data[2] = z;
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success = true;
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// publish data if successful transfer of new data, no overflow
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if (data_ready && !overflow && data_changed) {
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// Sensor orientation
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// Forward X := +X
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// Right Y := -Y
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// Down Z := -Z
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_px4_mag.update(now, x, math::negate(y), math::negate(z));
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if (_failure_count > 0) {
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_failure_count--;
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}
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success = true;
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if (_failure_count > 0) {
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_failure_count--;
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}
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} else if (overflow) {
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perf_count(_overflow_perf);
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}
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} else {
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@ -88,6 +88,7 @@ private:
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perf_counter_t _bad_register_perf{perf_alloc(PC_COUNT, MODULE_NAME": bad register")};
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perf_counter_t _bad_transfer_perf{perf_alloc(PC_COUNT, MODULE_NAME": bad transfer")};
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perf_counter_t _reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": reset")};
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perf_counter_t _overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": data overflow")};
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hrt_abstime _reset_timestamp{0};
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hrt_abstime _last_config_check_timestamp{0};
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@ -106,7 +107,7 @@ private:
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static constexpr uint8_t size_register_cfg{3};
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register_config_t _register_cfg[size_register_cfg] {
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// Register | Set bits, Clear bits
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{ Register::CNTL1, CNTL1_BIT::ODR_50HZ | CNTL1_BIT::Mode_Continuous, CNTL1_BIT::OSR_512 | CNTL1_BIT::RNG_2G},
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{ Register::CNTL1, CNTL1_BIT::ODR_50HZ_SET | CNTL1_BIT::Mode_Continuous_SET, CNTL1_BIT::OSR_512_CLEAR | CNTL1_BIT::RNG_2G_CLEAR | CNTL1_BIT::ODR_50HZ_CLEAR | CNTL1_BIT::Mode_Continuous_CLEAR},
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{ Register::CNTL2, CNTL2_BIT::ROL_PNT, CNTL2_BIT::SOFT_RST},
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{ Register::SET_RESET_PERIOD, SET_RESET_PERIOD_BIT::FBR, 0 },
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};
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@ -87,16 +87,18 @@ enum STATUS_BIT : uint8_t {
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// CNTL1
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enum CNTL1_BIT : uint8_t {
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// OSR[7:6]
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OSR_512 = Bit7 | Bit6, // 00
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OSR_512_CLEAR = Bit7 | Bit6, // 00: 512
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// RNG[5:4]
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RNG_2G = Bit5 | Bit4, // 00
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RNG_2G_CLEAR = Bit5 | Bit4, // 00: 2G
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// ODR[3:2]
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ODR_50HZ = Bit2, // 01
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ODR_50HZ_SET = Bit2, // 01: 50Hz
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ODR_50HZ_CLEAR = Bit3,
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// MODE[1:0]
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Mode_Continuous = Bit0, // 01
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Mode_Continuous_SET = Bit0, // 01: Continuous
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Mode_Continuous_CLEAR = Bit1,
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};
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// CNTL2
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