Commit Graph

22928 Commits

Author SHA1 Message Date
David Sidrane a254b0dca5 px4fmu-v5:Define the FMU_CAP[1:3] per FMUv5 Spec 2017-07-17 21:02:50 -10:00
David Sidrane 14ce28b1f3 px4fmu-v5:GPIO Clean up per FMUv5 Spec.
Added comments to ADC defines with Pin numbers.
  Added the GPIO_HW_{REV:VER}_DRIVE signals
  Define the GPIO_nPOWER_IN_{A:C] and assign them to
  BRICK1, BRICK2 and USB Valid.
  Regroupped power signals and defined true logic Power Control macros
  in the arch agnostic form.
  Defined the same IOCTL defines for FMU GPIO IOCTL
  Use the power Control macros on board_app_initialize
2017-07-17 21:02:50 -10:00
David Sidrane d33b945db6 px4fmu-v5:SPI chip selects per FMUv5 Spec 2017-07-17 21:02:50 -10:00
David Sidrane 8607b72805 px4fmu-v5:Removed unused LED alias defines. 2017-07-17 21:02:50 -10:00
David Sidrane 892ae1436c px4fmu-v4pro::Insure the discharge of the PWM pins on rest.
As done on fmuV4 on resets invoked from system (not boot) insure
  we establish a low output state (discharge the pins) on PWM pins
  before they become inputs as a result of the pending reset.

  We also delay the reset by 400 MS to insure the 3.1 Ms pulse is
  not too close to the last PWM pulse.
2017-07-17 21:02:50 -10:00
David Sidrane b23e6fc87c px4fmu-v4pro:Define GPIO xxx_VALIDs and initalize them.
The LTC4417 provides a valid signals for brick1, brick 2 and USB
  This change  configures the GIOP and provides 1) a MACRO to read
  the pin and 2) the IOCTL defines to read it from the FMU.

  The macro's result is true logic: It is true when the signal is active.
  (Active low on the the LTC4417). The IOCTL read would be the actual
  pin state.
2017-07-17 21:02:50 -10:00
David Sidrane 258faeee03 px4fmu-v4:Define GPIO GPIO_VDD_USB_VALID and initalize it.
The V4 HW replaced the LTC4417 provided valid signal for USB.
  with an active high, version. This commit configures the GIOP
  and provides 1) a MACRO to read the pin and the IOCTL defines
  to read it from the FMU. The macro result true logic: true
  when the signal is high. The IOCTL read would be the actual
  pin state.
2017-07-17 21:02:50 -10:00
David Sidrane f7cc78bffe px4fmu-v2:Define GPIO GPIO_VDD_USB_VALID and initalize it.
The LTC4417 provides a valid signal for USB. This change
   configures the GIOP and provides 1) True logic macro to
   read the pin and the IOCTL defines to read it from the FMU.
   The macro will return true when the signal is active (low
   on the LTC4417). The IOCTL will read be the actual pin state.
2017-07-17 21:02:50 -10:00
David Sidrane 30aca6677f px4fmu-v2:nuttx config fix typo GPIO_USART6_CTT->GPIO_USART6_CTS
Since Hardware flow control has not been enabled this typo
   survived.
2017-07-17 21:02:50 -10:00
David Sidrane 4188c4d0d5 px4fmu-v5:Turn On SD card 2017-07-17 21:02:50 -10:00
David Sidrane a09bc63747 px4fmu-v5:Use PX4_ERR in board init, spi init and sdio init 2017-07-17 21:02:50 -10:00
David Sidrane 2a61518c9f px4fmu-v5:Enable SPI5 in NuttX 2017-07-17 21:02:50 -10:00
David Sidrane 229c5d482f px4fmu-v5:More GPIO_VDD_3V3V_SD_CARD_EN -> GPIO_VDD_3V3_SD_CARD_EN 2017-07-17 21:02:50 -10:00
David Sidrane 46daebfb6c px4fmu-v5:Removed a SPI 5 reeady signal from board_spi_reset
board_spi_reset is used to reset the internal SPI bus.
   therefore GPIO_SPI5_DRDY7_EXTERNAL1 should not have been
   minipulated, as it is on SPI5
2017-07-17 21:02:50 -10:00
David Sidrane 59d020fba3 px4fmu-v5:Added comment block to board_spi_reset 2017-07-17 21:02:50 -10:00
David Sidrane 85b6986079 px4fmu-v5:Fix board_peripheral_reset to use correct polarity
GPIO_nVDD_5V_PERIPH_EN is Active low. board_peripheral_reset
   need to tune it OFF then ON
2017-07-17 21:02:50 -10:00
David Sidrane ebc8b47fad px4fmu-v5:Added board_on_reset api to reset PWM 2017-07-17 21:02:50 -10:00
David Sidrane 54bd0a9f2a px4fmu-v5:Using arch agnostic gpio init
Define the GPIO pin list use the board_gpio_init
2017-07-17 21:02:50 -10:00
David Sidrane 044b845c40 px4fmu-v5:Match GPIO_VDD_3V3_SD_CARD_EN and polarity to FMUv5 Pin Spec RC01
Removed extra V GPIO_VDD_3V3[V]_SD_CARD_EN and it is active High
2017-07-17 21:02:50 -10:00
David Sidrane 82dc6de19f px4fmu-v5:Define the BOARD_NUMBER_BRICKS for future enumeration
When BOARD_NUMBER_BRICKS exists it will enable multiple
   power source testing and reporting.
2017-07-17 21:02:50 -10:00
David Sidrane b9f43068af px4fmu-v5:Define the existance of the UI PWM LED and it's polarity
Per https://docs.google.com/spreadsheets/d/1-n0__BYDedQrc_2NHqBenG1DNepAgnHpSGglke-QQwY/edit#gid=730959725
  Usage of the PWM UI led is optional and if used it's polaity may
  be set ot Active low or high.
2017-07-17 21:02:50 -10:00
David Sidrane 33cd8c7093 px4fmu-v5:Fixed comment 8 PWM 2017-07-17 21:02:50 -10:00
David Sidrane e20d685f40 px4fmu-v5:Add Timer and Channel to comment for HEATER 2017-07-17 21:02:50 -10:00
David Sidrane c1eac11823 px4fmu-v5:Match signals names to FMUv5 Pin Spec RC01 2017-07-17 21:02:50 -10:00
David Sidrane 5669434585 px4fmu-v5:Define ADC GPIO and Channels clearly
Moving forward we want all the board configs to drive the
   configuration. This is just cleanup to give a clear
   example of how ADC should be defined by a simple list,
   based on ADC pin number as related to the GPIO and
   channel number. Then the xxx_CHANNEL bit are
   used to form the ADC_CHANNELS (mask). The GPIO
   will are used to for a list for initalization.
2017-07-17 21:02:50 -10:00
David Sidrane 5ba02d740c px4fmu-v5:Group SPI signals by bus 2017-07-17 21:02:50 -10:00
David Sidrane 88c1521b5e px4fmu-v5:Status LED's are driven open drain
Allows Anaode of LEDs to be tied to V5 or V3.3
2017-07-17 21:02:50 -10:00
David Sidrane 68e5764dbc board common:Add arch agnostic gpio init 2017-07-17 21:02:50 -10:00
Simone Guscetti ada48571d7 fmu-v5: fix timer config 2017-07-17 21:02:50 -10:00
Simone Guscetti a00441ecf4 fmu-v5 timer_config: timer io channels for FMU_CH7/8 2017-07-17 21:02:50 -10:00
Simone Guscetti a4d8bf56cc fmu-v5 timer_config: set up the timers for v5 board
FMU_CH7/8 use timer 12 ch1/2
FMU_CAP use timer 2
Buzzer use timer 9
2017-07-17 21:02:50 -10:00
Simone Guscetti bc793d15cf fmu-v5 board_config: add FMU_CH7 and FMU_CH8 2017-07-17 21:02:50 -10:00
Simone Guscetti db9bef352a fmu-v5 board_config: config SPI5 sync and reset pins 2017-07-17 21:02:50 -10:00
Simone Guscetti 1e86f24cf9 fmu-v5 board_config: set up external spi 2017-07-17 21:02:50 -10:00
Simone Guscetti 74dfa8805f fmu-v5 board_config: power A is the brick voltage sensing 2017-07-17 21:02:50 -10:00
Simone Guscetti 518383ada8 fmu-v5: update board config to the newest pin assigment 2017-07-17 21:02:50 -10:00
Simone Guscetti 308295f648 fmu-v5: fix compiling errors 2017-07-17 21:02:50 -10:00
Simone Guscetti 30f9c61e67 fmu-v5: started updating board config to newest specs 2017-07-17 21:02:50 -10:00
Julien Lecoeur 71136dcedf Log_writer_file: Increase stack size
Test flights reported the warning `[load_mon] log_writer_file low on stack! (292 bytes left)`

Increase stack size from 1060  to 1072 (=8 + 1060 rounded to next multiple of 8).
2017-07-18 08:24:37 +02:00
Julien Lecoeur bc006b81fc can_boot_descriptor: python3 compatibility 2017-07-18 08:24:37 +02:00
Julien Lecoeur 87e9ad0caa Patch NuttX/nuttx and NuttX/apps for new arm-none-eabi-gcc 7.1.0 warnings
Rename nuttx patch

Add nuttx patch for unused variable error

Pending nuttx patch

Backport nuttx fix for unused variables in nsh_proccmds.c

Fix Patch format

Modify pending patch to match new nuttx PR

Move accepted nuttx changes from pending patch to backport patch
2017-07-18 08:24:37 +02:00
Julien Lecoeur 940f2c3cca Update libuavcan submodule, fix arm-none-eabi-gcc 7.1.0 warnings 2017-07-18 08:24:37 +02:00
Julien Lecoeur 61d6903b40 Fix -Werror=stringop-overflow on gcc 7
The error was:
Firmware/src/systemcmds/hardfault_log/hardfault_log.c:312:7: error: specified bound 30 equals the size of the destination [-Werror=stringop-overflow=]
       strncat(marker, sp_name, sizeof(marker));
       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2017-07-18 08:24:37 +02:00
Julien Lecoeur abcb920df4 Fix -Werror=implicit-fallthrough on arm-none-eabi-gcc 7.1.0
BMP280: fix -Werror=implicit-fallthrough on arm-none-eabi-gcc 7

gnss: fix -Werror=implicit-fallthrough on arm-none-eabi-gcc 7

fmu: fix -Werror=implicit-fallthrough on arm-none-eabi-gcc 7

timer.c: fix -Werror=implicit-fallthrough on arm-none-eabi-gcc 7

px4cannode_led: fix -Werror=implicit-fallthrough on arm-none-eabi-gcc 7

Fix -Werror=implicit-fallthrough on gcc7
2017-07-18 08:24:37 +02:00
Julien Lecoeur d477b1f0f4 Fix -Werror=stringop-overflow on gcc 7
This prevents the compiler from optimising pdump. The error was:
Firmware/src/drivers/boards/common/board_crashdump.c:41:2: error: 'memset' writing 3240 bytes into a region of size 4 overflows the destination [-Werror=stringop-overflow=]
  memset(pdump, 0, sizeof(fullcontext_s));
2017-07-18 08:24:37 +02:00
David Sidrane 4349f49610 PX4 System:Expunge the nuttx adc structure from the system
This PR is preliminary ground work for FMUv5.

   PX4 does not use the NuttX adc driver. But used the same format
   for the data returned by the nuttx ADC driver.

   There was a fixme:in src/platforms/px4_adc.h "this needs to be
   a px4_adc_msg_s type" With this PR the need for
   src/platforms/px4_adc.h goes away as the driver drv_adc.h now
   describes the px4_adc_msg_t.
2017-07-17 22:28:29 +02:00
Carl Olsson d92377a6e6 ekf2: remove unused function (#7529)
* ekf2: remove unused function

Signed-off-by: CarlOlsson <carlolsson.co@gmail.com>

* ekf2: removed unused variable _mag_decl_saved

Signed-off-by: CarlOlsson <carlolsson.co@gmail.com>
2017-07-17 17:24:23 +10:00
Beat Küng c59d7baad8 replay: add backward compatibility for updated sensor_combined topic 2017-07-16 14:08:37 +02:00
Beat Küng cef3a29ac9 refactor replay: split timestamp offset into separate method 2017-07-16 14:08:37 +02:00
Nicolae Rosia 950273dbcf msg: ekf: switch to uin32_t for deltas, should be more than enough
Signed-off-by: Nicolae Rosia <nicolae.rosia@gmail.com>
2017-07-16 14:08:37 +02:00