forked from Archive/PX4-Autopilot
STM32 CAN driver now compiles
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4210 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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@ -122,19 +122,19 @@
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/* CAN */
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/* CAN */
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#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN11)
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#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
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#define GPIO_CAN1_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN8)
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#define GPIO_CAN1_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
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#define GPIO_CAN1_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN0)
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#define GPIO_CAN1_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
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#define GPIO_CAN1_RX_4 (GPIO_ALT|GPIO_AF9|GPIO_PORTI|GPIO_PIN9)
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#define GPIO_CAN1_RX_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
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#define GPIO_CAN1_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN12)
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#define GPIO_CAN1_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
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#define GPIO_CAN1_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN9)
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#define GPIO_CAN1_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
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#define GPIO_CAN1_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN1)
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#define GPIO_CAN1_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1)
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#define GPIO_CAN1_TX_4 (GPIO_ALT|GPIO_AF9|GPIO_PORTH|GPIO_PIN13)
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#define GPIO_CAN1_TX_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
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#define GPIO_CAN2_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN12)
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#define GPIO_CAN2_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
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#define GPIO_CAN2_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN5)
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#define GPIO_CAN2_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
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#define GPIO_CAN2_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN13)
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#define GPIO_CAN2_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
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#define GPIO_CAN2_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN6)
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#define GPIO_CAN2_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
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/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
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/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
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* (PA4 or PA5) is automatically connected to the analog converter output
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* (PA4 or PA5) is automatically connected to the analog converter output
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File diff suppressed because it is too large
Load Diff
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@ -815,10 +815,10 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_
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static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
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static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
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{
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{
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FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
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FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
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uint32_t resetbit;
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uint32_t resetbit;
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uint32_t regaddr;
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uint32_t regaddr;
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uint32_t regval;
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uint32_t regval;
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irqstate_t flags;
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pwmvdbg("TIM%d\n", priv->timid);
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pwmvdbg("TIM%d\n", priv->timid);
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@ -898,6 +898,12 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
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#endif
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#endif
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}
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}
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/* Disable interrupts momentary to stop any ongoing timer processing and
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* to prevent any concurrent access to the reset register.
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*/
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flags = irqsave();
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/* Reset the timer - stopping the output and putting the timer back
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/* Reset the timer - stopping the output and putting the timer back
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* into a state where pwm_start() can be called.
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* into a state where pwm_start() can be called.
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*/
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*/
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@ -908,6 +914,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
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regval &= ~resetbit;
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regval &= ~resetbit;
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putreg32(regval, regaddr);
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putreg32(regval, regaddr);
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irqrestore(flags);
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pwmvdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
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pwmvdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
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pwm_dumpregs(priv, "After stop");
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pwm_dumpregs(priv, "After stop");
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@ -15,6 +15,7 @@ Contents
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- LEDs
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- LEDs
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- Ethernet
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- Ethernet
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- PWM
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- PWM
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- CAN
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- Configurations
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- Configurations
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Development Environment
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Development Environment
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@ -220,6 +221,40 @@ FSMC must be disabled in this case! PD13 is available at:
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TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD.
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TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD.
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Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14.
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Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14.
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CAN
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===
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Connector 10 (CN10) is DB-9 male connector that can be used with CAN1 or CAN2.
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JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver
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JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver
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CAN signals are then available on CN10 pins:
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CN10 Pin 7 = CANH
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CN10 Pin 2 = CANL
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Mapping to STM32 GPIO pins:
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PD0 = FSMC_D2 & CAN1_RX
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PD1 = FSMC_D3 & CAN1_TX
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PB13 = ULPI_D6 & CAN2_TX
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PB5 = ULPI_D7 & CAN2_RX
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Configuration Options:
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CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
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CONFIG_STM32_CAN2 must also be defined)
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CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
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Default: 8
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CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
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Default: 4
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CONFIG_STM32_CAN1 - Enable support for CAN1
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CONFIG_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined.
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CONFIG_STM32_CAN2 - Enable support for CAN1
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CONFIG_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2 is defined.
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STM3240G-EVAL-specific Configuration Options
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STM3240G-EVAL-specific Configuration Options
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============================================
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============================================
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@ -301,6 +301,32 @@
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#define GPIO_TIM4_CH2 GPIO_TIM4_CH2_2
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#define GPIO_TIM4_CH2 GPIO_TIM4_CH2_2
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/* CAN
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*
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* Connector 10 (CN10) is DB-9 male connector that can be used with CAN1 or CAN2.
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*
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* JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver
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* JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver
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*
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* CAN signals are then available on CN10 pins:
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*
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* CN10 Pin 7 = CANH
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* CN10 Pin 2 = CANL
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*
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* Mapping to STM32 GPIO pins:
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*
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* PD0 = FSMC_D2 & CAN1_RX
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* PD1 = FSMC_D3 & CAN1_TX
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* PB13 = ULPI_D6 & CAN2_TX
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* PB5 = ULPI_D7 & CAN2_RX
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*/
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3
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#define GPIO_CAN2_RX GPIO_CAN2_RX_2
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#define GPIO_CAN2_TX GPIO_CAN2_TX_1
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/************************************************************************************
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/************************************************************************************
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* Public Data
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* Public Data
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************************************************************************************/
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************************************************************************************/
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@ -89,11 +89,14 @@
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/* CAN message support */
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/* CAN message support */
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#define CAN_MAXDATALEN 8
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#define CAN_MAXDATALEN 8
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#define CAN_ID(hdr) ((uint16_t)(hdr) >> 5)
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#define CAN_ID(hdr) ((uint16_t)(hdr) >> 5)
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#define CAN_RTR(hdr) (((hdr) & 0x0010) != 0)
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#define CAN_RTR(hdr) (((hdr) & 0x0010) != 0)
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#define CAN_DLC(hdr) ((hdr) & 0x0f)
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#define CAN_DLC(hdr) ((hdr) & 0x0f)
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#define CAN_MSGLEN(hdr) (sizeof(struct can_msg_s) - (CAN_MAXDATALEN - CAN_DLC(hdr)))
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#define CAN_MSGLEN(hdr) (sizeof(struct can_msg_s) - (CAN_MAXDATALEN - CAN_DLC(hdr)))
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#define CAN_MSG(id, rtr, dlc) ((uint16_t)id << 5 | (uint16_t)rtr << 4 | (uint16_t)dlc)
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/* Built-in ioctl commands
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/* Built-in ioctl commands
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*
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*
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* CANIOCTL_RTR: Send the remote transmission request and wait for the response.
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* CANIOCTL_RTR: Send the remote transmission request and wait for the response.
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