forked from Archive/PX4-Autopilot
Add scripts for debugging with openocd
Note: We now use the version of stm32f4x that comes with openocd 0.7.0 or later
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# program a bootable device load on a mavstation
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# To run type openocd -f mavprogram.cfg
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source [find interface/olimex-arm-usb-ocd-h.cfg]
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source [find px4fmu-v1-board.cfg]
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init
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halt
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# Find the flash inside this CPU
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flash probe 0
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# erase it (128 pages) then program and exit
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#flash erase_sector 0 0 127
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# stm32f1x mass_erase 0
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# It seems that Pat's image has a start address offset of 0x1000 but the vectors need to be at zero, so fixbin.sh moves things around
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#flash write_bank 0 fixed.bin 0
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#flash write_image firmware.elf
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#shutdown
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target remote :3333
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mon reset halt
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mon poll
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mon cortex_m maskisr auto
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set mem inaccessible-by-default off
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set print pretty
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source Debug/PX4
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# The latest defaults in OpenOCD 0.7.0 are actually prettymuch correct for the px4fmu
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# increase working area to 32KB for faster flash programming
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set WORKAREASIZE 0x8000
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source [find target/stm32f4x.cfg]
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openocd -f interface/olimex-arm-usb-ocd-h.cfg -f Debug/stm32f4x.cfg
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# script for stm32f2xxx
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32f4xxx
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
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#
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# Since we may be running of an RC oscilator, we crank down the speed a
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# bit more to be on the safe side. Perhaps superstition, but if are
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# running off a crystal, we can run closer to the limit. Note
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# that there can be a pretty wide band where things are more or less stable.
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jtag_khz 1000
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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#jtag scan chain
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# See STM Document RM0033
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# Section 32.6.3 - corresponds to Cortex-M3 r2p0
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set _CPUTAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID ] } {
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set _BSTAPID $BSTAPID
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} else {
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# See STM Document RM0033
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# Section 32.6.2
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#
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set _BSTAPID 0x06413041
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}
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jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -rtos auto
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m3 reset_config sysresetreq
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