forked from Archive/PX4-Autopilot
PIC32 Ethernet driver now at least talks to the PHY
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4467 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
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9422880309
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e01934d011
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@ -75,7 +75,6 @@
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* CONFIG_PIC32MX_NINTERFACES determines the number of physical interfaces
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* that will be supported -- unless it is more than actually supported by the
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@ -120,6 +119,14 @@
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# define CONFIG_NET_NRXDESC 4
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#endif
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/* Make sure that the size of each buffer is a multiple of 4 bytes. This
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* will force alignment of all buffers to 4-byte boundaries (this is needed
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* by the queuing logic which will cast each buffer address to a pointer
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* type).
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*/
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#define PIC32MX_ALIGNED_BUFSIZE ((CONFIG_NET_BUFSIZE + 3) & ~3)
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/* The number of buffers will, then, be one for each descriptor plus one extra */
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#define PIC32MX_NBUFFERS (CONFIG_NET_NRXDESC + CONFIG_NET_NTXDESC + 1)
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@ -342,7 +349,7 @@ struct pic32mx_driver_s
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struct pic32mx_rxdesc_s pd_rxdesc[CONFIG_NET_NRXDESC];
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struct pic32mx_txdesc_s pd_txdesc[CONFIG_NET_NTXDESC];
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uint8_t pd_buffers[PIC32MX_NBUFFERS * CONFIG_NET_BUFSIZE];
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uint8_t pd_buffers[PIC32MX_NBUFFERS * PIC32MX_ALIGNED_BUFSIZE];
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};
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/****************************************************************************
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@ -416,6 +423,7 @@ static void pic32mx_showmii(uint8_t phyaddr, const char *msg);
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# define pic32mx_showmii(phyaddr,msg)
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# endif
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static void pic32mx_phybusywait(void);
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static void pic32mx_phywrite(uint8_t phyaddr, uint8_t regaddr,
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uint16_t phydata);
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static uint16_t pic32mx_phyread(uint8_t phyaddr, uint8_t regaddr);
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@ -582,7 +590,7 @@ static inline void pic32mx_bufferinit(struct pic32mx_driver_s *priv)
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for (i = 0, buffer = priv->pd_buffers; i < PIC32MX_NBUFFERS; i++)
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{
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sq_addlast((sq_entry_t*)buffer, &priv->pd_freebuffers);
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buffer += CONFIG_NET_BUFSIZE;
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buffer += PIC32MX_ALIGNED_BUFSIZE;
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}
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}
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@ -2102,6 +2110,27 @@ static void pic32mx_showmii(uint8_t phyaddr, const char *msg)
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}
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#endif
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/****************************************************************************
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* Function: pic32mx_phybusywait
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*
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* Description:
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* Wait until the PHY is no longer busy
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*
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* Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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*
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****************************************************************************/
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static void pic32mx_phybusywait(void)
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{
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while ((pic32mx_getreg(PIC32MX_EMAC1_MIND) & EMAC1_MIND_MIIMBUSY) != 0);
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}
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/****************************************************************************
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* Function: pic32mx_phywrite
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*
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@ -2125,23 +2154,23 @@ static void pic32mx_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata)
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{
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uint32_t regval;
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/* Make sure that the PHY is not still busy from the last command */
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pic32mx_phybusywait();
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/* Set PHY address and PHY register address */
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regval = ((uint32_t)phyaddr << EMAC1_MADR_PHYADDR_SHIFT) |
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((uint32_t)regaddr << EMAC1_MADR_REGADDR_SHIFT);
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pic32mx_putreg(regval, PIC32MX_EMAC1_MADR);
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/* Set up to write */
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pic32mx_putreg(EMAC1_MCMD_WRITE, PIC32MX_EMAC1_MCMD);
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/* Write the register data to the PHY */
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pic32mx_putreg((uint32_t)phydata, PIC32MX_EMAC1_MWTD);
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/* Wait for the PHY command to complete */
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/* Two clock cycles until busy is set from the write operation */
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while ((pic32mx_getreg(PIC32MX_EMAC1_MIND) & EMAC1_MIND_MIIMBUSY) != 0);
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__asm__ __volatile__ ("nop; nop;");
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}
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#endif
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@ -2167,7 +2196,9 @@ static uint16_t pic32mx_phyread(uint8_t phyaddr, uint8_t regaddr)
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{
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uint32_t regval;
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pic32mx_putreg(0, PIC32MX_EMAC1_MCMD);
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/* Make sure that the PHY is not still busy from the last command */
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pic32mx_phybusywait();
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/* Set PHY address and PHY register address */
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@ -2179,9 +2210,13 @@ static uint16_t pic32mx_phyread(uint8_t phyaddr, uint8_t regaddr)
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pic32mx_putreg(EMAC1_MCMD_READ, PIC32MX_EMAC1_MCMD);
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/* Four clock cycles until busy is set from the write operation */
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__asm__ __volatile__ ("nop; nop; nop; nop;");
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/* Wait for the PHY command to complete */
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while ((pic32mx_getreg(PIC32MX_EMAC1_MIND) & (EMAC1_MIND_MIIMBUSY|EMAC1_MIND_NOTVALID)) != 0);
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pic32mx_phybusywait();
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pic32mx_putreg(0, PIC32MX_EMAC1_MCMD);
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/* Return the PHY register data */
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@ -2761,6 +2796,17 @@ static void pic32mx_ethreset(struct pic32mx_driver_s *priv)
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while ((pic32mx_getreg(PIC32MX_ETH_STAT) & ETH_STAT_ETHBUSY) != 0);
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/* Turn the Ethernet controller on. */
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pic32mx_putreg(ETH_CON1_ON, PIC32MX_ETH_CON1SET);
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/* Clear the Ethernet STAT BUFCNT */
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while ((pic32mx_getreg(PIC32MX_ETH_STAT) & ETH_STAT_BUFCNT_MASK) != 0)
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{
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pic32mx_putreg(ETH_CON1_BUFCDEC, PIC32MX_ETH_CON1SET);
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}
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/* Clear the Ethernet Interrupt Flag (ETHIF) bit in the Interrupts module */
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#if CONFIG_PIC32MX_NINTERFACES > 1
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