forked from Archive/PX4-Autopilot
WIP: ctrl zero h7 pixracer pro sync
This commit is contained in:
Daniel Agar
parent
c9b5e488f5
commit
da5c61bf46
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@ -221,32 +221,32 @@
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/* UART/USART */
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#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
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#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2 /* PD4 */
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#define GPIO_USART2_CTS GPIO_USART2_CTS_NSS_2 /* PD3 */
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#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
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#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
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#define GPIO_USART2_CTS GPIO_USART2_CTS_NSS_2 /* PD3 */
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2 /* PD4 */
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
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#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */
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#define GPIO_USART3_CTS GPIO_USART3_CTS_NSS_2 /* PD11 */
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
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#define GPIO_USART3_CTS GPIO_USART3_CTS_NSS_2 /* PD11 */
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#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */
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#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */
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#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */
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#define GPIO_UART4_TX GPIO_UART4_TX_2 /* PA0 */
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#define GPIO_UART4_RX GPIO_UART4_RX_2 /* PA1 */
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#define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */
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#define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */
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#define GPIO_USART6_TX 0 /* USART6 is RX-only */
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#define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */
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#define GPIO_UART7_RX GPIO_UART7_RX_1 /* PE7 */
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#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE8 */
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#define GPIO_UART7_TX GPIO_UART7_TX_3 /* PE8 */
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#define GPIO_UART7_RX GPIO_UART7_RX_3 /* PE7 */
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#define GPIO_UART8_RX GPIO_UART8_RX_1 /* PE0 */
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#define GPIO_UART8_TX GPIO_UART8_TX_1 /* PE1 */
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#define GPIO_UART8_TX GPIO_UART8_TX_1 /* PE1 */
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#define GPIO_UART8_RX GPIO_UART8_RX_1 /* PE0 */
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/* CAN */
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3 /* PD0 */
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3 /* PD0 */
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */
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/* SPI */
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@ -262,7 +262,7 @@
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#define GPIO_SPI5_SCK ADJ_SLEW_RATE(GPIO_SPI5_SCK_1) /* PF7 */
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#define GPIO_SPI5_MISO GPIO_SPI5_MISO_1 /* PF8 */
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#define GPIO_SPI5_MOSI GPIO_SPI5_MOSI_1 /* PF9 */
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#define GPIO_SPI5_MOSI GPIO_SPI5_MOSI_2 /* PF9 */
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/* I2C */
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@ -37,8 +37,9 @@
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#define DMAMAP_SPI1_RX DMAMAP_DMA12_SPI1RX_0 /* DMA1:37 */
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#define DMAMAP_SPI1_TX DMAMAP_DMA12_SPI1TX_0 /* DMA1:38 */
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#define DMAMAP_USART6_RX DMAMAP_DMA12_USART6RX_1 /* DMA1:71 */
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#define DMAMAP_USART6_TX DMAMAP_DMA12_USART6TX_1 /* DMA1:72 */
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#define DMAMAP_SPI2_RX DMAMAP_DMA12_SPI2RX_0 /* DMA1:39 */
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#define DMAMAP_SPI2_TX DMAMAP_DMA12_SPI2TX_0 /* DMA1:40 */
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#define DMAMAP_SPI5_RX DMAMAP_DMA12_SPI5RX_0 /* DMA1:85 */
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#define DMAMAP_SPI5_TX DMAMAP_DMA12_SPI5TX_0 /* DMA1:86 */
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#define DMAMAP_SPI5_RX DMAMAP_DMA12_SPI5RX_0 /* DMA1:83 */
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#define DMAMAP_SPI5_TX DMAMAP_DMA12_SPI5TX_0 /* DMA1:84 */
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@ -53,13 +53,11 @@ CONFIG_CDCACM_VENDORSTR="mRo"
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CONFIG_CLOCK_MONOTONIC=y
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_HARDFAULT_ALERT=y
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CONFIG_DEBUG_MEMFAULT=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DEFAULT_SMALL=y
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CONFIG_DEV_FIFO_SIZE=0
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CONFIG_DEV_PIPE_MAXSIZE=1024
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CONFIG_DEV_PIPE_SIZE=70
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CONFIG_DISABLE_MQUEUE=y
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CONFIG_EXPERIMENTAL=y
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CONFIG_FAT_DMAMEMORY=y
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CONFIG_FAT_LCNAMES=y
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@ -188,10 +186,8 @@ CONFIG_STM32H7_SPI5_DMA_BUFFER=1024
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CONFIG_STM32H7_SPI_DMA=y
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CONFIG_STM32H7_SPI_DMATHRESHOLD=8
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CONFIG_STM32H7_TIM1=y
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CONFIG_STM32H7_TIM2=y
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CONFIG_STM32H7_TIM3=y
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CONFIG_STM32H7_TIM4=y
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CONFIG_STM32H7_TIM8=y
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CONFIG_STM32H7_UART4=y
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CONFIG_STM32H7_UART7=y
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CONFIG_STM32H7_UART8=y
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@ -206,7 +206,6 @@ SECTIONS
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_sram4_heap_start = ABSOLUTE(.);
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} > SRAM4
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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@ -220,13 +219,4 @@ SECTIONS
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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.ramfunc : {
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_sramfuncs = .;
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*(.ramfunc .ramfunc.*)
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. = ALIGN(4);
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_eramfuncs = .;
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} > ITCM_RAM AT > FLASH
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_framfuncs = LOADADDR(.ramfunc);
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}
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@ -198,7 +198,6 @@ SECTIONS
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} > AXI_SRAM
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/* Emit the the D3 power domain section for locating BDMA data */
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.sram4_reserve (NOLOAD) :
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{
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*(.sram4)
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