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nuttx configs: disable nuttx timers which are used for PWM output 

These are not required, and to be consistent we enforce disabling them now.
This commit is contained in:
Beat Küng 2020-01-29 14:56:46 +01:00 committed by David Sidrane
parent b380278f02
commit d74d094940
23 changed files with 93 additions and 53 deletions
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2
boards/airmind/mindpx-v2/nuttx-config/nsh/defconfig
View File

@ -191,9 +191,7 @@ CONFIG_STM32_SPI2=y
CONFIG_STM32_SPI4=y
CONFIG_STM32_TIM10=y
CONFIG_STM32_TIM11=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_TIM9=y
CONFIG_STM32_UART4=y
CONFIG_STM32_UART7=y

4
boards/av/x-v1/nuttx-config/nsh/defconfig
View File

@ -213,12 +213,8 @@ CONFIG_STM32F7_SPI1=y
CONFIG_STM32F7_SPI2=y
CONFIG_STM32F7_SPI4=y
CONFIG_STM32F7_SPI5=y
CONFIG_STM32F7_TIM10=y
CONFIG_STM32F7_TIM11=y
CONFIG_STM32F7_TIM14=y
CONFIG_STM32F7_TIM1=y
CONFIG_STM32F7_TIM3=y
CONFIG_STM32F7_TIM4=y
CONFIG_STM32F7_UART4=y
CONFIG_STM32F7_UART5=y
CONFIG_STM32F7_UART7=y

2
boards/bitcraze/crazyflie/nuttx-config/nsh/defconfig
View File

@ -175,8 +175,6 @@ CONFIG_STM32_SAVE_CRASHDUMP=y
CONFIG_STM32_SERIALBRK_BSDCOMPAT=y
CONFIG_STM32_SERIAL_DISABLE_REORDERING=y
CONFIG_STM32_SPI1=y
CONFIG_STM32_TIM2=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_USART2=y
CONFIG_STM32_USART3=y
CONFIG_STM32_USART6=y

4
boards/holybro/kakutef7/nuttx-config/nsh/defconfig
View File

@ -182,10 +182,6 @@ CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y
CONFIG_STM32F7_SPI1=y
CONFIG_STM32F7_SPI2=y
CONFIG_STM32F7_SPI4=y
CONFIG_STM32F7_TIM1=y
CONFIG_STM32F7_TIM3=y
CONFIG_STM32F7_TIM5=y
CONFIG_STM32F7_TIM8=y
CONFIG_STM32F7_UART4=y
CONFIG_STM32F7_UART7=y
CONFIG_STM32F7_USART1=y

2
boards/mro/ctrl-zero-f7/nuttx-config/nsh/defconfig
View File

@ -191,9 +191,7 @@ CONFIG_STM32F7_SPI2=y
CONFIG_STM32F7_SPI5=y
CONFIG_STM32F7_TIM10=y
CONFIG_STM32F7_TIM11=y
CONFIG_STM32F7_TIM1=y
CONFIG_STM32F7_TIM3=y
CONFIG_STM32F7_TIM4=y
CONFIG_STM32F7_TIM9=y
CONFIG_STM32F7_UART4=y
CONFIG_STM32F7_UART7=y

2
boards/mro/x21-777/nuttx-config/nsh/defconfig
View File

@ -189,9 +189,7 @@ CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y
CONFIG_STM32F7_SPI1=y
CONFIG_STM32F7_SPI2=y
CONFIG_STM32F7_TIM10=y
CONFIG_STM32F7_TIM1=y
CONFIG_STM32F7_TIM3=y
CONFIG_STM32F7_TIM4=y
CONFIG_STM32F7_TIM9=y
CONFIG_STM32F7_UART4=y
CONFIG_STM32F7_UART7=y

2
boards/mro/x21/nuttx-config/nsh/defconfig
View File

@ -189,9 +189,7 @@ CONFIG_STM32_SPI1=y
CONFIG_STM32_SPI2=y
CONFIG_STM32_TIM10=y
CONFIG_STM32_TIM11=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_TIM9=y
CONFIG_STM32_UART4=y
CONFIG_STM32_UART7=y

3
boards/nxp/fmuk66-v3/nuttx-config/nsh/defconfig
View File

@ -68,9 +68,6 @@ CONFIG_KINETIS_EMAC_RMIICLK1588CLKIN=y
CONFIG_KINETIS_ENET=y
CONFIG_KINETIS_FLEXCAN0=y
CONFIG_KINETIS_FLEXCAN1=y
CONFIG_KINETIS_FTM0=y
CONFIG_KINETIS_FTM2=y
CONFIG_KINETIS_FTM3=y
CONFIG_KINETIS_GPIOIRQ=y
CONFIG_KINETIS_I2C0=y
CONFIG_KINETIS_I2C1=y

1
boards/omnibus/f4sd/nuttx-config/nsh/defconfig
View File

@ -168,7 +168,6 @@ CONFIG_STM32_SPI1=y
CONFIG_STM32_SPI2=y
CONFIG_STM32_SPI3=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM5=y
CONFIG_STM32_UART4=y
CONFIG_STM32_USART1=y

2
boards/px4/fmu-v2/nuttx-config/nsh/defconfig
View File

@ -192,9 +192,7 @@ CONFIG_STM32_SPI2=y
CONFIG_STM32_SPI4=y
CONFIG_STM32_TIM10=y
CONFIG_STM32_TIM11=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_TIM9=y
CONFIG_STM32_UART4=y
CONFIG_STM32_UART7=y

2
boards/px4/fmu-v3/nuttx-config/nsh/defconfig
View File

@ -191,9 +191,7 @@ CONFIG_STM32_SPI2=y
CONFIG_STM32_SPI4=y
CONFIG_STM32_TIM10=y
CONFIG_STM32_TIM11=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_TIM9=y
CONFIG_STM32_UART4=y
CONFIG_STM32_UART7=y

2
boards/px4/fmu-v3/nuttx-config/stackcheck/defconfig
View File

@ -192,9 +192,7 @@ CONFIG_STM32_SPI2=y
CONFIG_STM32_SPI4=y
CONFIG_STM32_TIM10=y
CONFIG_STM32_TIM11=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_TIM9=y
CONFIG_STM32_UART4=y
CONFIG_STM32_UART7=y

2
boards/px4/fmu-v4/nuttx-config/nsh/defconfig
View File

@ -192,8 +192,6 @@ CONFIG_STM32_SPI4=y
CONFIG_STM32_SPI_DMA=y
CONFIG_STM32_TIM10=y
CONFIG_STM32_TIM11=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_TIM8=y
CONFIG_STM32_TIM9=y
CONFIG_STM32_UART4=y

2
boards/px4/fmu-v4/nuttx-config/stackcheck/defconfig
View File

@ -193,8 +193,6 @@ CONFIG_STM32_SPI4=y
CONFIG_STM32_SPI_DMA=y
CONFIG_STM32_TIM10=y
CONFIG_STM32_TIM11=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_TIM8=y
CONFIG_STM32_TIM9=y
CONFIG_STM32_UART4=y

2
boards/px4/fmu-v4pro/nuttx-config/nsh/defconfig
View File

@ -197,8 +197,6 @@ CONFIG_STM32_SPI6=y
CONFIG_STM32_SPI_DMA=y
CONFIG_STM32_TIM10=y
CONFIG_STM32_TIM11=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_TIM8=y
CONFIG_STM32_TIM9=y
CONFIG_STM32_UART4=y

4
boards/px4/fmu-v5/nuttx-config/critmonitor/defconfig
View File

@ -196,10 +196,6 @@ CONFIG_STM32F7_SPI5=y
CONFIG_STM32F7_SPI6=y
CONFIG_STM32F7_TIM10=y
CONFIG_STM32F7_TIM11=y
CONFIG_STM32F7_TIM1=y
CONFIG_STM32F7_TIM3=y
CONFIG_STM32F7_TIM4=y
CONFIG_STM32F7_TIM9=y
CONFIG_STM32F7_UART4=y
CONFIG_STM32F7_UART7=y
CONFIG_STM32F7_UART8=y

4
boards/px4/fmu-v5/nuttx-config/irqmonitor/defconfig
View File

@ -196,10 +196,6 @@ CONFIG_STM32F7_SPI5=y
CONFIG_STM32F7_SPI6=y
CONFIG_STM32F7_TIM10=y
CONFIG_STM32F7_TIM11=y
CONFIG_STM32F7_TIM1=y
CONFIG_STM32F7_TIM3=y
CONFIG_STM32F7_TIM4=y
CONFIG_STM32F7_TIM9=y
CONFIG_STM32F7_UART4=y
CONFIG_STM32F7_UART7=y
CONFIG_STM32F7_UART8=y

4
boards/px4/fmu-v5/nuttx-config/nsh/defconfig
View File

@ -196,10 +196,6 @@ CONFIG_STM32F7_SPI5=y
CONFIG_STM32F7_SPI6=y
CONFIG_STM32F7_TIM10=y
CONFIG_STM32F7_TIM11=y
CONFIG_STM32F7_TIM1=y
CONFIG_STM32F7_TIM3=y
CONFIG_STM32F7_TIM4=y
CONFIG_STM32F7_TIM9=y
CONFIG_STM32F7_UART4=y
CONFIG_STM32F7_UART7=y
CONFIG_STM32F7_UART8=y

4
boards/px4/fmu-v5/nuttx-config/stackcheck/defconfig
View File

@ -196,10 +196,6 @@ CONFIG_STM32F7_SPI5=y
CONFIG_STM32F7_SPI6=y
CONFIG_STM32F7_TIM10=y
CONFIG_STM32F7_TIM11=y
CONFIG_STM32F7_TIM1=y
CONFIG_STM32F7_TIM3=y
CONFIG_STM32F7_TIM4=y
CONFIG_STM32F7_TIM9=y
CONFIG_STM32F7_UART4=y
CONFIG_STM32F7_UART7=y
CONFIG_STM32F7_UART8=y

2
boards/uvify/core/nuttx-config/nsh/defconfig
View File

@ -190,8 +190,6 @@ CONFIG_STM32_SPI2=y
CONFIG_STM32_SPI4=y
CONFIG_STM32_TIM10=y
CONFIG_STM32_TIM11=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM4=y
CONFIG_STM32_TIM8=y
CONFIG_STM32_TIM9=y
CONFIG_STM32_UART4=y

16
platforms/nuttx/src/px4/nxp/kinetis/include/px4_arch/io_timer_hw_description.h
View File

@ -111,6 +111,7 @@ static inline constexpr timer_io_channels_t initIOTimerChannel(const io_timers_t
static inline constexpr io_timers_t initIOTimer(Timer::Timer timer)
{
bool nuttx_config_timer_enabled = false;
io_timers_t ret{};
switch (timer) {
@ -119,6 +120,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer)
ret.clock_register = KINETIS_SIM_SCGC6;
ret.clock_bit = SIM_SCGC6_FTM0;
ret.vectorno = KINETIS_IRQ_FTM0;
#ifdef CONFIG_KINETIS_FTM0
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::FTM1:
@ -126,6 +130,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer)
ret.clock_register = KINETIS_SIM_SCGC6;
ret.clock_bit = SIM_SCGC6_FTM1;
ret.vectorno = KINETIS_IRQ_FTM1;
#ifdef CONFIG_KINETIS_FTM1
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::FTM2:
@ -133,6 +140,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer)
ret.clock_register = KINETIS_SIM_SCGC3;
ret.clock_bit = SIM_SCGC3_FTM2;
ret.vectorno = KINETIS_IRQ_FTM2;
#ifdef CONFIG_KINETIS_FTM2
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::FTM3:
@ -140,9 +150,15 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer)
ret.clock_register = KINETIS_SIM_SCGC3;
ret.clock_bit = SIM_SCGC3_FTM3;
ret.vectorno = KINETIS_IRQ_FTM3;
#ifdef CONFIG_KINETIS_FTM3
nuttx_config_timer_enabled = true;
#endif
break;
}
// This is not strictly required, but for consistency let's make sure NuttX timers are disabled
constexpr_assert(!nuttx_config_timer_enabled, "IO Timer requires NuttX timer config to be disabled (KINETIS_FTMx)");
return ret;
}

41
platforms/nuttx/src/px4/stm/stm32_common/include/px4_arch/io_timer_hw_description.h
View File

@ -104,6 +104,7 @@ static inline constexpr timer_io_channels_t initIOTimerChannelOutputClear(const
static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dma = {})
{
bool nuttx_config_timer_enabled = false;
io_timers_t ret{};
switch (timer) {
@ -113,6 +114,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB2ENR_TIM1EN;
ret.clock_freq = STM32_APB2_TIM1_CLKIN;
ret.vectorno = STM32_IRQ_TIM1CC;
#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32F7_TIM1)
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer2:
@ -121,6 +125,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1ENR_TIM2EN;
ret.clock_freq = STM32_APB1_TIM2_CLKIN;
ret.vectorno = STM32_IRQ_TIM2;
#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32F7_TIM2)
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer3:
@ -129,6 +136,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1ENR_TIM3EN;
ret.clock_freq = STM32_APB1_TIM3_CLKIN;
ret.vectorno = STM32_IRQ_TIM3;
#if defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32F7_TIM3)
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer4:
@ -137,6 +147,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1ENR_TIM4EN;
ret.clock_freq = STM32_APB1_TIM4_CLKIN;
ret.vectorno = STM32_IRQ_TIM4;
#if defined(CONFIG_STM32_TIM4) || defined(CONFIG_STM32F7_TIM4)
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer5:
@ -145,6 +158,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1ENR_TIM5EN;
ret.clock_freq = STM32_APB1_TIM5_CLKIN;
ret.vectorno = STM32_IRQ_TIM5;
#if defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32F7_TIM5)
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer6:
@ -153,6 +169,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1ENR_TIM6EN;
ret.clock_freq = STM32_APB1_TIM6_CLKIN;
ret.vectorno = STM32_IRQ_TIM6;
#if defined(CONFIG_STM32_TIM6) || defined(CONFIG_STM32F7_TIM6)
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer7:
@ -161,6 +180,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1ENR_TIM7EN;
ret.clock_freq = STM32_APB1_TIM7_CLKIN;
ret.vectorno = STM32_IRQ_TIM7;
#if defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32F7_TIM7)
nuttx_config_timer_enabled = true;
#endif
break;
#ifdef RCC_APB2ENR_TIM8EN
@ -171,6 +193,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB2ENR_TIM8EN;
ret.clock_freq = STM32_APB2_TIM8_CLKIN;
ret.vectorno = STM32_IRQ_TIM8CC;
#if defined(CONFIG_STM32_TIM8) || defined(CONFIG_STM32F7_TIM8)
nuttx_config_timer_enabled = true;
#endif
break;
#endif
@ -182,6 +207,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB2ENR_TIM9EN;
ret.clock_freq = STM32_APB2_TIM9_CLKIN;
ret.vectorno = STM32_IRQ_TIM9;
#if defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32F7_TIM9)
nuttx_config_timer_enabled = true;
#endif
break;
#endif
@ -193,6 +221,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB2ENR_TIM10EN;
ret.clock_freq = STM32_APB2_TIM10_CLKIN;
ret.vectorno = STM32_IRQ_TIM10;
#if defined(CONFIG_STM32_TIM10) || defined(CONFIG_STM32F7_TIM10)
nuttx_config_timer_enabled = true;
#endif
break;
#endif
@ -204,6 +235,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB2ENR_TIM11EN;
ret.clock_freq = STM32_APB2_TIM11_CLKIN;
ret.vectorno = STM32_IRQ_TIM11;
#if defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32F7_TIM11)
nuttx_config_timer_enabled = true;
#endif
break;
#endif
@ -215,6 +249,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1ENR_TIM12EN;
ret.clock_freq = STM32_APB1_TIM12_CLKIN;
ret.vectorno = STM32_IRQ_TIM12;
#if defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32F7_TIM12)
nuttx_config_timer_enabled = true;
#endif
break;
#endif
@ -226,6 +263,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
default: break;
}
// This is not strictly required, but for consistency let's make sure NuttX timers are disabled
constexpr_assert(!nuttx_config_timer_enabled, "IO Timer requires NuttX timer config to be disabled (STM32_TIMx)");
// DShot
if (dshot_dma.index != DMA::Invalid) {
ret.dshot.dma_base = getDMABaseRegister(dshot_dma);
@ -235,4 +275,3 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
return ret;
}

37
platforms/nuttx/src/px4/stm/stm32h7/include/px4_arch/io_timer_hw_description.h
View File

@ -129,6 +129,7 @@ static inline constexpr timer_io_channels_t initIOTimerChannel(const io_timers_t
static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dma = {})
{
bool nuttx_config_timer_enabled = false;
io_timers_t ret{};
switch (timer) {
@ -138,6 +139,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB2ENR_TIM1EN;
ret.clock_freq = STM32_APB2_TIM1_CLKIN;
ret.vectorno = STM32_IRQ_TIMCC;
#ifdef CONFIG_STM32_TIM1
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer2:
@ -146,6 +150,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1LENR_TIM2EN;
ret.clock_freq = STM32_APB1_TIM2_CLKIN;
ret.vectorno = STM32_IRQ_TIM2;
#ifdef CONFIG_STM32_TIM2
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer3:
@ -154,6 +161,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1LENR_TIM3EN;
ret.clock_freq = STM32_APB1_TIM3_CLKIN;
ret.vectorno = STM32_IRQ_TIM3;
#ifdef CONFIG_STM32_TIM3
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer4:
@ -162,6 +172,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1LENR_TIM4EN;
ret.clock_freq = STM32_APB1_TIM4_CLKIN;
ret.vectorno = STM32_IRQ_TIM4;
#ifdef CONFIG_STM32_TIM4
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer5:
@ -170,6 +183,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1LENR_TIM5EN;
ret.clock_freq = STM32_APB1_TIM5_CLKIN;
ret.vectorno = STM32_IRQ_TIM5;
#ifdef CONFIG_STM32_TIM5
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer6:
@ -178,6 +194,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1LENR_TIM6EN;
ret.clock_freq = STM32_APB1_TIM6_CLKIN;
ret.vectorno = STM32_IRQ_TIM6;
#ifdef CONFIG_STM32_TIM6
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer7:
@ -186,6 +205,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1LENR_TIM7EN;
ret.clock_freq = STM32_APB1_TIM7_CLKIN;
ret.vectorno = STM32_IRQ_TIM7;
#ifdef CONFIG_STM32_TIM7
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer8:
@ -194,6 +216,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB2ENR_TIM8EN;
ret.clock_freq = STM32_APB2_TIM8_CLKIN;
ret.vectorno = STM32_IRQ_TIM8CC;
#ifdef CONFIG_STM32_TIM8
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer9:
@ -208,6 +233,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1LENR_TIM12EN;
ret.clock_freq = STM32_APB1_TIM12_CLKIN;
ret.vectorno = STM32_IRQ_TIM12;
#ifdef CONFIG_STM32_TIM12
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer13:
@ -216,6 +244,9 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1LENR_TIM13EN;
ret.clock_freq = STM32_APB1_TIM13_CLKIN;
ret.vectorno = STM32_IRQ_TIM13;
#ifdef CONFIG_STM32_TIM13
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::Timer14:
@ -224,9 +255,15 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
ret.clock_bit = RCC_APB1LENR_TIM14EN;
ret.clock_freq = STM32_APB1_TIM14_CLKIN;
ret.vectorno = STM32_IRQ_TIM14;
#ifdef CONFIG_STM32_TIM14
nuttx_config_timer_enabled = true;
#endif
break;
}
// This is not strictly required, but for consistency let's make sure NuttX timers are disabled
constexpr_assert(!nuttx_config_timer_enabled, "IO Timer requires NuttX timer config to be disabled (STM32_TIMx)");
// DShot
if (dshot_dma.index != DMA::Invalid) {
ret.dshot.dma_base = getDMABaseRegister(dshot_dma);