forked from Archive/PX4-Autopilot
boards: enable CONFIG_ARMV7M_LAZYFPU everywhere
This commit is contained in:
parent
abec2bd8df
commit
cb74cb8692
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F427V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -52,6 +52,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -31,6 +31,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F405RG=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -28,6 +28,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F412CE=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -20,6 +20,7 @@ CONFIG_ARCH_CHIP_STM32H7=y
|
|||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARMV7M_BASEPRI_WAR=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -20,6 +20,7 @@ CONFIG_ARCH_CHIP_STM32H7=y
|
|||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARMV7M_BASEPRI_WAR=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -20,6 +20,7 @@ CONFIG_ARCH_CHIP_STM32H7=y
|
|||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARMV7M_BASEPRI_WAR=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -37,6 +37,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -20,6 +20,7 @@ CONFIG_ARCH_CHIP_STM32H7=y
|
|||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARMV7M_BASEPRI_WAR=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_STACKCHECK=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -29,6 +29,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F429V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -20,6 +20,7 @@ CONFIG_ARCH_CHIP_STM32H7=y
|
|||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARMV7M_BASEPRI_WAR=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F427V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -19,6 +19,7 @@ CONFIG_ARCH_CHIP_KINETIS=y
|
|||
CONFIG_ARCH_CHIP_MK66FN2M0VMD18=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -19,6 +19,7 @@ CONFIG_ARCH_CHIP_KINETIS=y
|
|||
CONFIG_ARCH_CHIP_MK66FN2M0VMD18=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -18,6 +18,7 @@ CONFIG_ARCH_CHIP_KINETIS=y
|
|||
CONFIG_ARCH_CHIP_MK66FN2M0VMD18=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -18,6 +18,7 @@ CONFIG_ARCH_CHIP_KINETIS=y
|
|||
CONFIG_ARCH_CHIP_MK66FN2M0VMD18=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -24,6 +24,7 @@ CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
|
|||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_ITCM=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_ARM_MPU=y
|
||||
|
|
|
@ -19,6 +19,7 @@ CONFIG_ARCH_CHIP_S32K146=y
|
|||
CONFIG_ARCH_CHIP_S32K14X=y
|
||||
CONFIG_ARCH_CHIP_S32K1XX=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -20,6 +20,7 @@ CONFIG_ARCH_CHIP="stm32"
|
|||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32F405RG=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F427V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F427V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F427V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_STACKCHECK=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F427V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F427V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F427V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_STACKCHECK=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F469I=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_STACKCHECK=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_STACKCHECK=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -20,6 +20,7 @@ CONFIG_ARCH_CHIP_STM32H7=y
|
|||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARMV7M_BASEPRI_WAR=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_ARMV7M_BASEPRI_WAR=y
|
|||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_STACKCHECK=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
|
|
|
@ -32,6 +32,7 @@ CONFIG_ARCH_CHIP_STM32=y
|
|||
CONFIG_ARCH_CHIP_STM32F427V=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=512
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_LAZYFPU=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
|
|
|
@ -64,7 +64,7 @@ void ISM330DLC::exit_and_cleanup()
|
|||
{
|
||||
if (_drdy_gpio != 0) {
|
||||
// Disable data ready callback
|
||||
px4_arch_gpiosetevent(_drdy_gpio, false, false, false, nullptr, nullptr);
|
||||
//px4_arch_gpiosetevent(_drdy_gpio, false, false, false, nullptr, nullptr);
|
||||
|
||||
RegisterWrite(Register::INT1_CTRL, 0);
|
||||
}
|
||||
|
@ -190,10 +190,10 @@ int ISM330DLC::DataReadyInterruptCallback(int irq, void *context, void *arg)
|
|||
|
||||
void ISM330DLC::DataReady()
|
||||
{
|
||||
_time_data_ready = hrt_absolute_time();
|
||||
// _time_data_ready = hrt_absolute_time();
|
||||
|
||||
perf_count(_drdy_count_perf);
|
||||
perf_count(_drdy_interval_perf);
|
||||
// perf_count(_drdy_count_perf);
|
||||
// perf_count(_drdy_interval_perf);
|
||||
|
||||
// make another measurement
|
||||
ScheduleNow();
|
||||
|
@ -205,7 +205,7 @@ void ISM330DLC::Start()
|
|||
|
||||
if (_drdy_gpio != 0 && false) { // TODO: enable
|
||||
// Setup data ready on rising edge
|
||||
px4_arch_gpiosetevent(_drdy_gpio, true, true, false, &ISM330DLC::DataReadyInterruptCallback, this);
|
||||
//px4_arch_gpiosetevent(_drdy_gpio, true, true, false, &ISM330DLC::DataReadyInterruptCallback, this);
|
||||
|
||||
// FIFO threshold level setting
|
||||
// FIFO_CTRL1: FTH_[7:0]
|
||||
|
|
Loading…
Reference in New Issue