forked from Archive/PX4-Autopilot
IO: Implement serial driver for STM32F7 MCUs.
This commit is contained in:
Simon Laube
Lorenz Meier
parent
a26c3a0530
commit
c6c9f4dc64
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@ -63,6 +63,8 @@
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#define PX4IO_SERIAL_VECTOR STM32_IRQ_UART7
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#define PX4IO_SERIAL_TX_DMAMAP DMAMAP_UART7_TX
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#define PX4IO_SERIAL_RX_DMAMAP DMAMAP_UART7_RX
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#define PX4IO_SERIAL_RCC_REG STM32_RCC_APB1ENR
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#define PX4IO_SERIAL_RCC_EN RCC_APB1ENR_UART7EN
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#define PX4IO_SERIAL_CLOCK STM32_PCLK1_FREQUENCY
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#define PX4IO_SERIAL_BITRATE 1500000 /* 1.5Mbps -> max rate for IO */
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@ -40,6 +40,7 @@ px4_add_module(
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px4io_uploader.cpp
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px4io_serial.cpp
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px4io_serial_f4.cpp
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px4io_serial_f7.cpp
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DEPENDS
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platforms__common
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)
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@ -54,24 +54,12 @@
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#include <stdio.h>
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#include <arch/board/board.h>
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/* XXX might be able to prune these */
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#include <nuttx/arch.h>
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#include <chip.h>
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#include <up_internal.h>
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#include <up_arch.h>
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#include <debug.h>
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#include <systemlib/perf_counter.h>
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#include <board_config.h>
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#include <modules/px4iofirmware/protocol.h>
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#include <drivers/device/device.h>
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#include <drivers/drv_hrt.h>
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#include <board_config.h>
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#include <systemlib/perf_counter.h>
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#include <modules/px4iofirmware/protocol.h>
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class PX4IO_serial : public device::Device
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{
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@ -190,8 +178,66 @@ private:
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#define PX4IO_INTERFACE_CLASS PX4IO_serial_f7
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#define PX4IO_INTERFACE_F7
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#include <stm32_dma.h>
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class PX4IO_serial_f7 : public PX4IO_serial
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{
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public:
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PX4IO_serial_f7();
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~PX4IO_serial_f7();
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virtual int init();
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virtual int ioctl(unsigned operation, unsigned &arg);
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protected:
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/**
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* Start the transaction with IO and wait for it to complete.
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*/
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int _bus_exchange(IOPacket *_packet);
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private:
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DMA_HANDLE _tx_dma;
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DMA_HANDLE _rx_dma;
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IOPacket *_current_packet;
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/** saved DMA status */
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static const unsigned _dma_status_inactive = 0x80000000; // low bits overlap DMA_STATUS_* values
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static const unsigned _dma_status_waiting = 0x00000000;
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volatile unsigned _rx_dma_status;
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/** client-waiting lock/signal */
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px4_sem_t _completion_semaphore;
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/**
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* DMA completion handler.
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*/
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static void _dma_callback(DMA_HANDLE handle, uint8_t status, void *arg);
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void _do_rx_dma_callback(unsigned status);
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/**
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* Serial interrupt handler.
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*/
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static int _interrupt(int vector, void *context, void *arg);
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void _do_interrupt();
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/**
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* Cancel any DMA in progress with an error.
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*/
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void _abort_dma();
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/**
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* Performance counters.
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*/
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perf_counter_t _pc_dmasetup;
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perf_counter_t _pc_dmaerrs;
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/* do not allow top copying this class */
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PX4IO_serial_f7(PX4IO_serial_f7 &);
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PX4IO_serial_f7 &operator = (const PX4IO_serial_f7 &);
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};
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#else
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#error "Interface not implemented for this chip"
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#endif
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@ -0,0 +1,495 @@
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/****************************************************************************
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*
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* Copyright (c) 2013-2015 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/**
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* @file px4io_serial_f7.cpp
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*
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* Serial interface for PX4IO on STM32F7
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*/
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#include "px4io_serial.h"
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#ifdef PX4IO_INTERFACE_F7
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#include "stm32_uart.h"
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#include "cache.h"
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/* serial register accessors */
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#define REG(_x) (*(volatile uint32_t *)(PX4IO_SERIAL_BASE + (_x)))
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#define rISR REG(STM32_USART_ISR_OFFSET)
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#define rISR_ERR_FLAGS_MASK (0x1f)
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#define rICR REG(STM32_USART_ICR_OFFSET)
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#define rRDR REG(STM32_USART_RDR_OFFSET)
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#define rTDR REG(STM32_USART_TDR_OFFSET)
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#define rBRR REG(STM32_USART_BRR_OFFSET)
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#define rCR1 REG(STM32_USART_CR1_OFFSET)
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#define rCR2 REG(STM32_USART_CR2_OFFSET)
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#define rCR3 REG(STM32_USART_CR3_OFFSET)
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#define rGTPR REG(STM32_USART_GTPR_OFFSET)
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PX4IO_serial_f7::PX4IO_serial_f7() :
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_tx_dma(nullptr),
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_rx_dma(nullptr),
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_current_packet(nullptr),
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_rx_dma_status(_dma_status_inactive),
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_completion_semaphore(SEM_INITIALIZER(0)),
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#if 0
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_pc_dmasetup(perf_alloc(PC_ELAPSED, "io_dmasetup ")),
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_pc_dmaerrs(perf_alloc(PC_COUNT, "io_dmaerrs "))
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#else
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_pc_dmasetup(nullptr),
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_pc_dmaerrs(nullptr)
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#endif
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{
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}
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PX4IO_serial_f7::~PX4IO_serial_f7()
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{
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if (_tx_dma != nullptr) {
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stm32_dmastop(_tx_dma);
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stm32_dmafree(_tx_dma);
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}
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if (_rx_dma != nullptr) {
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stm32_dmastop(_rx_dma);
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stm32_dmafree(_rx_dma);
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}
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/* reset the UART */
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rCR1 = 0;
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rCR2 = 0;
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rCR3 = 0;
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/* detach our interrupt handler */
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up_disable_irq(PX4IO_SERIAL_VECTOR);
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irq_detach(PX4IO_SERIAL_VECTOR);
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/* restore the GPIOs */
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px4_arch_unconfiggpio(PX4IO_SERIAL_TX_GPIO);
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px4_arch_unconfiggpio(PX4IO_SERIAL_RX_GPIO);
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/* Disable APB clock for the USART peripheral */
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modifyreg32(PX4IO_SERIAL_RCC_REG, PX4IO_SERIAL_RCC_EN, 0);
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/* and kill our semaphores */
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px4_sem_destroy(&_completion_semaphore);
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perf_free(_pc_dmasetup);
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perf_free(_pc_dmaerrs);
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}
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int
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PX4IO_serial_f7::init()
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{
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/* initialize base implementation */
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int r;
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if ((r = PX4IO_serial::init()) != 0) {
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return r;
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}
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/* allocate DMA */
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_tx_dma = stm32_dmachannel(PX4IO_SERIAL_TX_DMAMAP);
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_rx_dma = stm32_dmachannel(PX4IO_SERIAL_RX_DMAMAP);
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if ((_tx_dma == nullptr) || (_rx_dma == nullptr)) {
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return -1;
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}
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/* Enable the APB clock for the USART peripheral */
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modifyreg32(PX4IO_SERIAL_RCC_REG, 0, PX4IO_SERIAL_RCC_EN);
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/* configure pins for serial use */
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px4_arch_configgpio(PX4IO_SERIAL_TX_GPIO);
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px4_arch_configgpio(PX4IO_SERIAL_RX_GPIO);
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/* reset & configure the UART */
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rCR1 = 0;
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rCR2 = 0;
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rCR3 = 0;
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/* clear data that may be in the RDR and clear overrun error: */
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if (rISR & USART_ISR_RXNE) {
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(void)rRDR;
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}
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rICR = rISR & rISR_ERR_FLAGS_MASK; /* clear the flags */
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/* configure line speed */
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uint32_t usartdiv32 = (PX4IO_SERIAL_CLOCK + (PX4IO_SERIAL_BITRATE) / 2) / (PX4IO_SERIAL_BITRATE);
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rBRR = usartdiv32;
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/* attach serial interrupt handler */
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irq_attach(PX4IO_SERIAL_VECTOR, _interrupt, this);
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up_enable_irq(PX4IO_SERIAL_VECTOR);
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/* enable UART in DMA mode, enable error and line idle interrupts */
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rCR3 = USART_CR3_EIE;
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/* TODO: maybe use DDRE */
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rCR1 = USART_CR1_RE | USART_CR1_TE | USART_CR1_UE | USART_CR1_IDLEIE;
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/* TODO: maybe we need to adhere to the procedure as described in the reference manual page 1251 (34.5.2) */
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/* create semaphores */
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px4_sem_init(&_completion_semaphore, 0, 0);
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/* _completion_semaphore use case is a signal */
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px4_sem_setprotocol(&_completion_semaphore, SEM_PRIO_NONE);
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/* XXX this could try talking to IO */
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return 0;
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}
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int
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PX4IO_serial_f7::ioctl(unsigned operation, unsigned &arg)
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{
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switch (operation) {
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case 1: /* XXX magic number - test operation */
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switch (arg) {
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case 0:
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syslog(LOG_INFO, "test 0\n");
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/* kill DMA, this is a PIO test */
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stm32_dmastop(_tx_dma);
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stm32_dmastop(_rx_dma);
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rCR3 &= ~(USART_CR3_DMAR | USART_CR3_DMAT);
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for (;;) {
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while (!(rISR & USART_ISR_TXE))
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;
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rTDR = 0x55;
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}
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return 0;
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case 1: {
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unsigned fails = 0;
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for (unsigned count = 0;; count++) {
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uint16_t value = count & 0xffff;
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if (write((PX4IO_PAGE_TEST << 8) | PX4IO_P_TEST_LED, &value, 1) != 0) {
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fails++;
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}
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if (count >= 5000) {
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syslog(LOG_INFO, "==== test 1 : %u failures ====\n", fails);
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perf_print_counter(_pc_txns);
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perf_print_counter(_pc_dmasetup);
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perf_print_counter(_pc_retries);
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perf_print_counter(_pc_timeouts);
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perf_print_counter(_pc_crcerrs);
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perf_print_counter(_pc_dmaerrs);
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perf_print_counter(_pc_protoerrs);
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perf_print_counter(_pc_uerrs);
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perf_print_counter(_pc_idle);
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perf_print_counter(_pc_badidle);
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count = 0;
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}
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}
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return 0;
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}
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case 2:
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syslog(LOG_INFO, "test 2\n");
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return 0;
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}
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default:
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break;
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}
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return -1;
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}
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int
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PX4IO_serial_f7::_bus_exchange(IOPacket *_packet)
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{
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_current_packet = _packet;
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/* clear data that may be in the RDR and clear overrun error: */
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if (rISR & USART_ISR_RXNE) {
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(void)rRDR;
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}
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rICR = rISR & rISR_ERR_FLAGS_MASK; /* clear the flags */
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/* start RX DMA */
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perf_begin(_pc_txns);
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perf_begin(_pc_dmasetup);
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/* DMA setup time ~3µs */
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_rx_dma_status = _dma_status_waiting;
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/*
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* Note that we enable circular buffer mode as a workaround for
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* there being no API to disable the DMA FIFO. We need direct mode
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* because otherwise when the line idle interrupt fires there
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* will be packet bytes still in the DMA FIFO, and we will assume
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* that the idle was spurious.
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*
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* XXX this should be fixed with a NuttX change.
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*/
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stm32_dmasetup(
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_rx_dma,
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PX4IO_SERIAL_BASE + STM32_USART_RDR_OFFSET,
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reinterpret_cast<uint32_t>(_current_packet),
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sizeof(*_current_packet),
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DMA_SCR_CIRC | /* XXX see note above */
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DMA_SCR_DIR_P2M |
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DMA_SCR_MINC |
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DMA_SCR_PSIZE_8BITS |
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DMA_SCR_MSIZE_8BITS |
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DMA_SCR_PBURST_SINGLE |
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DMA_SCR_MBURST_SINGLE);
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rCR3 |= USART_CR3_DMAR;
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stm32_dmastart(_rx_dma, _dma_callback, this, false);
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/* Clean _current_packet, so DMA can see the data */
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arch_clean_dcache((uintptr_t)_current_packet,
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(uintptr_t)_current_packet + sizeof(*_current_packet));
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/* start TX DMA - no callback if we also expect a reply */
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/* DMA setup time ~3µs */
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stm32_dmasetup(
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_tx_dma,
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PX4IO_SERIAL_BASE + STM32_USART_TDR_OFFSET,
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reinterpret_cast<uint32_t>(_current_packet),
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PKT_SIZE(*_current_packet),
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DMA_SCR_DIR_M2P |
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DMA_SCR_MINC |
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DMA_SCR_PSIZE_8BITS |
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DMA_SCR_MSIZE_8BITS |
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DMA_SCR_PBURST_SINGLE |
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DMA_SCR_MBURST_SINGLE);
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rCR3 |= USART_CR3_DMAT;
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stm32_dmastart(_tx_dma, nullptr, nullptr, false);
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//rCR1 &= ~USART_CR1_TE;
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//rCR1 |= USART_CR1_TE;
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perf_end(_pc_dmasetup);
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/* compute the deadline for a 10ms timeout */
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struct timespec abstime;
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clock_gettime(CLOCK_REALTIME, &abstime);
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abstime.tv_nsec += 10 * 1000 * 1000;
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if (abstime.tv_nsec >= 1000 * 1000 * 1000) {
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abstime.tv_sec++;
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abstime.tv_nsec -= 1000 * 1000 * 1000;
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}
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/* wait for the transaction to complete - 64 bytes @ 1.5Mbps ~426µs */
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int ret;
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for (;;) {
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ret = sem_timedwait(&_completion_semaphore, &abstime);
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if (ret == OK) {
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/* check for DMA errors */
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if (_rx_dma_status & DMA_STATUS_TEIF) {
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perf_count(_pc_dmaerrs);
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ret = -EIO;
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break;
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}
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/* check packet CRC - corrupt packet errors mean IO receive CRC error */
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uint8_t crc = _current_packet->crc;
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_current_packet->crc = 0;
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if ((crc != crc_packet(_current_packet)) || (PKT_CODE(*_current_packet) == PKT_CODE_CORRUPT)) {
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perf_count(_pc_crcerrs);
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ret = -EIO;
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break;
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}
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/* successful txn (may still be reporting an error) */
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break;
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}
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if (errno == ETIMEDOUT) {
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/* something has broken - clear out any partial DMA state and reconfigure */
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_abort_dma();
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perf_count(_pc_timeouts);
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perf_cancel(_pc_txns); /* don't count this as a transaction */
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break;
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}
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/* we might? see this for EINTR */
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syslog(LOG_ERR, "unexpected ret %d/%d\n", ret, errno);
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}
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/* reset DMA status */
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_rx_dma_status = _dma_status_inactive;
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/* update counters */
|
||||
perf_end(_pc_txns);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void
|
||||
PX4IO_serial_f7::_dma_callback(DMA_HANDLE handle, uint8_t status, void *arg)
|
||||
{
|
||||
if (arg != nullptr) {
|
||||
PX4IO_serial_f7 *ps = reinterpret_cast<PX4IO_serial_f7 *>(arg);
|
||||
|
||||
ps->_do_rx_dma_callback(status);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
PX4IO_serial_f7::_do_rx_dma_callback(unsigned status)
|
||||
{
|
||||
/* on completion of a reply, wake the waiter */
|
||||
if (_rx_dma_status == _dma_status_waiting) {
|
||||
|
||||
/* check for packet overrun - this will occur after DMA completes */
|
||||
uint32_t sr = rISR;
|
||||
|
||||
if (sr & (USART_ISR_ORE | USART_ISR_RXNE)) {
|
||||
(void)rRDR;
|
||||
rICR = sr & (USART_ISR_ORE | USART_ISR_RXNE);
|
||||
status = DMA_STATUS_TEIF;
|
||||
}
|
||||
|
||||
/* save RX status */
|
||||
_rx_dma_status = status;
|
||||
|
||||
/* disable UART DMA */
|
||||
rCR3 &= ~(USART_CR3_DMAT | USART_CR3_DMAR);
|
||||
|
||||
/* complete now */
|
||||
px4_sem_post(&_completion_semaphore);
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
PX4IO_serial_f7::_interrupt(int irq, void *context, void *arg)
|
||||
{
|
||||
if (arg != nullptr) {
|
||||
PX4IO_serial_f7 *instance = reinterpret_cast<PX4IO_serial_f7 *>(arg);
|
||||
|
||||
instance->_do_interrupt();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
PX4IO_serial_f7::_do_interrupt()
|
||||
{
|
||||
uint32_t sr = rISR; /* get UART status register */
|
||||
if (sr & USART_ISR_RXNE) {
|
||||
(void)rRDR; /* read DR to clear RXNE */
|
||||
}
|
||||
rICR = sr & rISR_ERR_FLAGS_MASK; /* clear flags */
|
||||
|
||||
if (sr & (USART_ISR_ORE | /* overrun error - packet was too big for DMA or DMA was too slow */
|
||||
USART_ISR_NF | /* noise error - we have lost a byte due to noise */
|
||||
USART_ISR_FE)) { /* framing error - start/stop bit lost or line break */
|
||||
|
||||
/*
|
||||
* If we are in the process of listening for something, these are all fatal;
|
||||
* abort the DMA with an error.
|
||||
*/
|
||||
if (_rx_dma_status == _dma_status_waiting) {
|
||||
_abort_dma();
|
||||
|
||||
perf_count(_pc_uerrs);
|
||||
/* complete DMA as though in error */
|
||||
_do_rx_dma_callback(DMA_STATUS_TEIF);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* XXX we might want to use FE / line break as an out-of-band handshake ... handle it here */
|
||||
|
||||
/* don't attempt to handle IDLE if it's set - things went bad */
|
||||
return;
|
||||
}
|
||||
|
||||
if (sr & USART_ISR_IDLE) {
|
||||
|
||||
/* if there is DMA reception going on, this is a short packet */
|
||||
if (_rx_dma_status == _dma_status_waiting) {
|
||||
/* Invalidate _current_packet, so we get fresh data from RAM */
|
||||
arch_invalidate_dcache((uintptr_t)_current_packet,
|
||||
(uintptr_t)_current_packet + sizeof(*_current_packet));
|
||||
|
||||
/* verify that the received packet is complete */
|
||||
size_t length = sizeof(*_current_packet) - stm32_dmaresidual(_rx_dma);
|
||||
|
||||
if ((length < 1) || (length < PKT_SIZE(*_current_packet))) {
|
||||
perf_count(_pc_badidle);
|
||||
|
||||
/* stop the receive DMA */
|
||||
stm32_dmastop(_rx_dma);
|
||||
|
||||
/* complete the short reception */
|
||||
_do_rx_dma_callback(DMA_STATUS_TEIF);
|
||||
return;
|
||||
}
|
||||
|
||||
perf_count(_pc_idle);
|
||||
|
||||
/* stop the receive DMA */
|
||||
stm32_dmastop(_rx_dma);
|
||||
|
||||
/* complete the short reception */
|
||||
_do_rx_dma_callback(DMA_STATUS_TCIF);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
PX4IO_serial_f7::_abort_dma()
|
||||
{
|
||||
/* stop DMA */
|
||||
stm32_dmastop(_tx_dma);
|
||||
stm32_dmastop(_rx_dma);
|
||||
|
||||
/* disable UART DMA */
|
||||
rCR3 &= ~(USART_CR3_DMAT | USART_CR3_DMAR);
|
||||
|
||||
/* clear data that may be in the RDR and clear overrun error: */
|
||||
if (rISR & USART_ISR_RXNE) {
|
||||
(void)rRDR;
|
||||
}
|
||||
rICR = rISR & rISR_ERR_FLAGS_MASK; /* clear the flags */
|
||||
}
|
||||
|
||||
#endif /* PX4IO_INTERFACE_F7 */
|
||||
Loading…
Reference in New Issue