forked from Archive/PX4-Autopilot
invensense/icm20689 driver minor improvements
- interupt pin set active low and latch - relax retry timeout if configure failed - improve configured empty rate (sample rate) rounding - fix RegisterCheck - check FIFO count as part of full transfer and reset or adjust timing if necessary
This commit is contained in:
Daniel Agar
parent
f5fe50f839
commit
c6825aa177
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@ -35,6 +35,7 @@ px4_add_module(
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MODULE drivers__imu__invensense__icm20689
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MAIN icm20689
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COMPILE_FLAGS
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-Wno-error
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SRCS
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ICM20689.cpp
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ICM20689.hpp
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@ -45,8 +45,8 @@ ICM20689::ICM20689(I2CSPIBusOption bus_option, int bus, uint32_t device, enum Ro
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SPI(MODULE_NAME, nullptr, bus, device, spi_mode, bus_frequency),
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I2CSPIDriver(MODULE_NAME, px4::device_bus_to_wq(get_device_id()), bus_option, bus),
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_drdy_gpio(drdy_gpio),
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_px4_accel(get_device_id(), ORB_PRIO_VERY_HIGH, rotation),
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_px4_gyro(get_device_id(), ORB_PRIO_VERY_HIGH, rotation)
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_px4_accel(get_device_id(), ORB_PRIO_HIGH, rotation),
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_px4_gyro(get_device_id(), ORB_PRIO_HIGH, rotation)
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{
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set_device_type(DRV_IMU_DEVTYPE_ICM20689);
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@ -131,7 +131,7 @@ void ICM20689::RunImpl()
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RegisterWrite(Register::PWR_MGMT_1, PWR_MGMT_1_BIT::DEVICE_RESET);
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_reset_timestamp = hrt_absolute_time();
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_state = STATE::WAIT_FOR_RESET;
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ScheduleDelayed(100);
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ScheduleDelayed(1_ms);
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break;
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case STATE::WAIT_FOR_RESET:
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@ -147,14 +147,14 @@ void ICM20689::RunImpl()
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} else {
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// RESET not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 10_ms) {
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PX4_ERR("Reset failed, retrying");
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if (hrt_elapsed_time(&_reset_timestamp) > 100_ms) {
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PX4_DEBUG("Reset failed, retrying");
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_state = STATE::RESET;
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ScheduleDelayed(10_ms);
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ScheduleDelayed(100_ms);
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} else {
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PX4_DEBUG("Reset not complete, check again in 1 ms");
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ScheduleDelayed(1_ms);
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PX4_DEBUG("Reset not complete, check again in 10 ms");
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ScheduleDelayed(10_ms);
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}
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}
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@ -180,8 +180,8 @@ void ICM20689::RunImpl()
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} else {
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PX4_DEBUG("Configure failed, retrying");
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// try again in 1 ms
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ScheduleDelayed(1_ms);
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// try again in 10 ms
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ScheduleDelayed(10_ms);
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}
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break;
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@ -195,7 +195,14 @@ void ICM20689::RunImpl()
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ScheduleDelayed(10_ms);
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// timestamp set in data ready interrupt
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samples = _fifo_read_samples.load();
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if (!_force_fifo_count_check) {
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samples = _fifo_read_samples.load();
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} else {
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const uint16_t fifo_count = FIFOReadCount();
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samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) * SAMPLES_PER_TRANSFER; // round down to nearest
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}
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timestamp_sample = _fifo_watermark_interrupt_timestamp;
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}
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@ -208,13 +215,7 @@ void ICM20689::RunImpl()
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// use the time now roughly corresponding with the last sample we'll pull from the FIFO
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timestamp_sample = hrt_absolute_time();
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const uint16_t fifo_count = FIFOReadCount();
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if (fifo_count == 0) {
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failure = true;
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perf_count(_fifo_empty_perf);
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}
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samples = (fifo_count / sizeof(FIFO::DATA) / 2) * 2; // round down to nearest 2
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samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) * SAMPLES_PER_TRANSFER; // round down to nearest
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}
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if (samples > FIFO_MAX_SAMPLES) {
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@ -223,13 +224,17 @@ void ICM20689::RunImpl()
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failure = true;
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FIFOReset();
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} else if (samples >= 2) {
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// require at least 2 samples (we want at least 1 new accel sample per transfer)
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} else if (samples >= SAMPLES_PER_TRANSFER) {
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// require at least SAMPLES_PER_TRANSFER (we want at least 1 new accel sample per transfer)
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if (!FIFORead(timestamp_sample, samples)) {
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failure = true;
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_px4_accel.increase_error_count();
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_px4_gyro.increase_error_count();
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}
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} else if (samples == 0) {
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failure = true;
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perf_count(_fifo_empty_perf);
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}
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if (failure || hrt_elapsed_time(&_last_config_check_timestamp) > 10_ms) {
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@ -291,23 +296,23 @@ void ICM20689::ConfigureGyro()
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switch (FS_SEL) {
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case FS_SEL_250_DPS:
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_px4_gyro.set_scale(math::radians(1.0f / 131.f));
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_px4_gyro.set_scale(math::radians(1.f / 131.f));
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_px4_gyro.set_range(math::radians(250.f));
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break;
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case FS_SEL_500_DPS:
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_px4_gyro.set_scale(math::radians(1.0f / 65.5f));
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_px4_gyro.set_scale(math::radians(1.f / 65.5f));
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_px4_gyro.set_range(math::radians(500.f));
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break;
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case FS_SEL_1000_DPS:
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_px4_gyro.set_scale(math::radians(1.0f / 32.8f));
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_px4_gyro.set_range(math::radians(1000.0f));
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_px4_gyro.set_scale(math::radians(1.f / 32.8f));
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_px4_gyro.set_range(math::radians(1000.f));
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break;
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case FS_SEL_2000_DPS:
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_px4_gyro.set_scale(math::radians(1.0f / 16.4f));
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_px4_gyro.set_range(math::radians(2000.0f));
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_px4_gyro.set_scale(math::radians(1.f / 16.4f));
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_px4_gyro.set_range(math::radians(2000.f));
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break;
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}
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}
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@ -318,16 +323,19 @@ void ICM20689::ConfigureSampleRate(int sample_rate)
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sample_rate = 1000; // default to 1 kHz
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}
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_fifo_empty_interval_us = math::max(((1000000 / sample_rate) / 250) * 250, 250); // round down to nearest 250 us
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_fifo_gyro_samples = math::min(_fifo_empty_interval_us / (1000000 / GYRO_RATE), FIFO_MAX_SAMPLES);
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// round down to nearest FIFO sample dt * SAMPLES_PER_TRANSFER
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const float min_interval = SAMPLES_PER_TRANSFER * FIFO_SAMPLE_DT;
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_fifo_empty_interval_us = math::max(roundf((1e6f / (float)sample_rate) / min_interval) * min_interval, min_interval);
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_fifo_gyro_samples = math::min((float)_fifo_empty_interval_us / (1e6f / GYRO_RATE), (float)FIFO_MAX_SAMPLES);
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// recompute FIFO empty interval (us) with actual gyro sample limit
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_fifo_empty_interval_us = _fifo_gyro_samples * (1000000 / GYRO_RATE);
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_fifo_empty_interval_us = _fifo_gyro_samples * (1e6f / GYRO_RATE);
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_fifo_accel_samples = math::min(_fifo_empty_interval_us / (1000000 / ACCEL_RATE), FIFO_MAX_SAMPLES);
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_fifo_accel_samples = math::min(_fifo_empty_interval_us / (1e6f / ACCEL_RATE), (float)FIFO_MAX_SAMPLES);
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_px4_accel.set_update_rate(1000000 / _fifo_empty_interval_us);
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_px4_gyro.set_update_rate(1000000 / _fifo_empty_interval_us);
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_px4_accel.set_update_rate(1e6f / _fifo_empty_interval_us);
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_px4_gyro.set_update_rate(1e6f / _fifo_empty_interval_us);
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}
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bool ICM20689::Configure()
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@ -354,14 +362,14 @@ int ICM20689::DataReadyInterruptCallback(int irq, void *context, void *arg)
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void ICM20689::DataReady()
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{
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perf_count(_drdy_interval_perf);
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if (_data_ready_count.fetch_add(1) >= (_fifo_gyro_samples - 1)) {
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_data_ready_count.store(0);
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_fifo_watermark_interrupt_timestamp = hrt_absolute_time();
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_fifo_read_samples.store(_fifo_gyro_samples);
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ScheduleNow();
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}
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perf_count(_drdy_interval_perf);
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}
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bool ICM20689::DataReadyInterruptConfigure()
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@ -370,8 +378,8 @@ bool ICM20689::DataReadyInterruptConfigure()
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return false;
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}
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// Setup data ready on rising edge
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return px4_arch_gpiosetevent(_drdy_gpio, true, false, true, &ICM20689::DataReadyInterruptCallback, this) == 0;
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// Setup data ready on falling edge
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return px4_arch_gpiosetevent(_drdy_gpio, false, true, true, &ICM20689::DataReadyInterruptCallback, this) == 0;
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}
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bool ICM20689::DataReadyInterruptDisable()
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@ -389,12 +397,12 @@ bool ICM20689::RegisterCheck(const register_config_t ®_cfg, bool notify)
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const uint8_t reg_value = RegisterRead(reg_cfg.reg);
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if (reg_cfg.set_bits && !(reg_value & reg_cfg.set_bits)) {
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if (reg_cfg.set_bits && ((reg_value & reg_cfg.set_bits) != reg_cfg.set_bits)) {
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PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not set)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.set_bits);
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success = false;
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}
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if (reg_cfg.clear_bits && (reg_value & reg_cfg.clear_bits)) {
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if (reg_cfg.clear_bits && ((reg_value & reg_cfg.clear_bits) != 0)) {
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PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not cleared)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.clear_bits);
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success = false;
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}
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@ -402,13 +410,6 @@ bool ICM20689::RegisterCheck(const register_config_t ®_cfg, bool notify)
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if (!success) {
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RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
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if (reg_cfg.reg == Register::ACCEL_CONFIG) {
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ConfigureAccel();
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} else if (reg_cfg.reg == Register::GYRO_CONFIG) {
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ConfigureGyro();
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}
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if (notify) {
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perf_count(_bad_register_perf);
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_px4_accel.increase_error_count();
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@ -449,16 +450,6 @@ void ICM20689::RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t cl
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RegisterWrite(reg, val);
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}
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void ICM20689::RegisterSetBits(Register reg, uint8_t setbits)
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{
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RegisterSetAndClearBits(reg, setbits, 0);
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}
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void ICM20689::RegisterClearBits(Register reg, uint8_t clearbits)
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{
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RegisterSetAndClearBits(reg, 0, clearbits);
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}
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uint16_t ICM20689::FIFOReadCount()
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{
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// read FIFO count
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@ -477,7 +468,7 @@ bool ICM20689::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples)
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{
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perf_begin(_transfer_perf);
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FIFOTransferBuffer buffer{};
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const size_t transfer_size = math::min(samples * sizeof(FIFO::DATA) + 1, FIFO::SIZE);
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const size_t transfer_size = math::min(samples * sizeof(FIFO::DATA) + 3, FIFO::SIZE);
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if (transfer((uint8_t *)&buffer, (uint8_t *)&buffer, transfer_size) != PX4_OK) {
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perf_end(_transfer_perf);
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@ -487,8 +478,41 @@ bool ICM20689::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples)
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perf_end(_transfer_perf);
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ProcessGyro(timestamp_sample, buffer, samples);
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return ProcessAccel(timestamp_sample, buffer, samples);
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const uint16_t fifo_count_bytes = combine(buffer.FIFO_COUNTH, buffer.FIFO_COUNTL);
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const uint16_t fifo_count_samples = fifo_count_bytes / sizeof(FIFO::DATA);
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if (fifo_count_samples == 0) {
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perf_count(_fifo_empty_perf);
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return false;
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}
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if (fifo_count_bytes >= FIFO::SIZE) {
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perf_count(_fifo_overflow_perf);
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FIFOReset();
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return false;
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}
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const uint16_t valid_samples = math::min(samples, fifo_count_samples);
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if (fifo_count_samples < samples) {
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// force check if there is somehow fewer samples actually in the FIFO (potentially a serious error)
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_force_fifo_count_check = true;
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} else if (fifo_count_samples > samples + 4) {
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// if we're more than a few samples behind force FIFO_COUNT check
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_force_fifo_count_check = true;
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} else {
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// skip earlier FIFO_COUNT and trust DRDY count if we're in sync
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_force_fifo_count_check = false;
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}
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if (valid_samples > 0) {
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ProcessGyro(timestamp_sample, buffer, valid_samples);
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return ProcessAccel(timestamp_sample, buffer, valid_samples);
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}
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return false;
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}
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void ICM20689::FIFOReset()
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@ -498,9 +522,8 @@ void ICM20689::FIFOReset()
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// FIFO_EN: disable FIFO
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RegisterWrite(Register::FIFO_EN, 0);
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// USER_CTRL: disable FIFO and reset all signal paths
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RegisterSetAndClearBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_RST | USER_CTRL_BIT::SIG_COND_RST,
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USER_CTRL_BIT::FIFO_EN);
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// USER_CTRL: reset FIFO
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RegisterSetAndClearBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_RST, USER_CTRL_BIT::FIFO_EN);
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// reset while FIFO is disabled
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_data_ready_count.store(0);
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@ -521,7 +544,8 @@ static bool fifo_accel_equal(const FIFO::DATA &f0, const FIFO::DATA &f1)
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return (memcmp(&f0.ACCEL_XOUT_H, &f1.ACCEL_XOUT_H, 6) == 0);
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}
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bool ICM20689::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, uint8_t samples)
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bool ICM20689::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer,
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const uint8_t samples)
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{
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PX4Accelerometer::FIFOSample accel;
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accel.timestamp_sample = timestamp_sample;
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@ -532,8 +556,8 @@ bool ICM20689::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTrans
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// accel data is doubled in FIFO, but might be shifted
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int accel_first_sample = 1;
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if (samples >= 3) {
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if (fifo_accel_equal(buffer.f[0], buffer.f[1])) {
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if (samples >= 4) {
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if (fifo_accel_equal(buffer.f[0], buffer.f[1]) && fifo_accel_equal(buffer.f[2], buffer.f[3])) {
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// [A0, A1, A2, A3]
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// A0==A1, A2==A3
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accel_first_sample = 1;
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@ -572,7 +596,7 @@ bool ICM20689::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTrans
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return !bad_data;
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}
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void ICM20689::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, uint8_t samples)
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void ICM20689::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples)
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{
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PX4Gyroscope::FIFOSample gyro;
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gyro.timestamp_sample = timestamp_sample;
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@ -76,19 +76,23 @@ protected:
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void custom_method(const BusCLIArguments &cli) override;
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void exit_and_cleanup() override;
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private:
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// Sensor Configuration
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static constexpr uint32_t GYRO_RATE{8000}; // 8 kHz gyro
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static constexpr uint32_t ACCEL_RATE{4000}; // 4 kHz accel
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static constexpr uint32_t FIFO_MAX_SAMPLES{ math::min(FIFO::SIZE / sizeof(FIFO::DATA) + 1, sizeof(PX4Gyroscope::FIFOSample::x) / sizeof(PX4Gyroscope::FIFOSample::x[0]))};
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static constexpr float FIFO_SAMPLE_DT{125.f};
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static constexpr uint32_t SAMPLES_PER_TRANSFER{2}; // ensure at least 1 new accel sample per transfer
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static constexpr float GYRO_RATE{1000000 / FIFO_SAMPLE_DT}; // 8 kHz gyro
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static constexpr float ACCEL_RATE{GYRO_RATE / 2.f}; // 4 kHz accel
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static constexpr uint32_t FIFO_MAX_SAMPLES{math::min(FIFO::SIZE / sizeof(FIFO::DATA), sizeof(PX4Gyroscope::FIFOSample::x) / sizeof(PX4Gyroscope::FIFOSample::x[0]))};
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// Transfer data
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struct FIFOTransferBuffer {
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uint8_t cmd{static_cast<uint8_t>(Register::FIFO_R_W) | DIR_READ};
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uint8_t cmd{static_cast<uint8_t>(Register::FIFO_COUNTH) | DIR_READ};
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uint8_t FIFO_COUNTH{0};
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uint8_t FIFO_COUNTL{0};
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FIFO::DATA f[FIFO_MAX_SAMPLES] {};
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};
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// ensure no struct padding
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static_assert(sizeof(FIFOTransferBuffer) == (sizeof(uint8_t) + FIFO_MAX_SAMPLES *sizeof(FIFO::DATA)));
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static_assert(sizeof(FIFOTransferBuffer) == (3 + FIFO_MAX_SAMPLES *sizeof(FIFO::DATA)));
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struct register_config_t {
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Register reg;
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@ -113,15 +117,15 @@ private:
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uint8_t RegisterRead(Register reg);
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void RegisterWrite(Register reg, uint8_t value);
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void RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t clearbits);
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void RegisterSetBits(Register reg, uint8_t setbits);
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void RegisterClearBits(Register reg, uint8_t clearbits);
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void RegisterSetBits(Register reg, uint8_t setbits) { RegisterSetAndClearBits(reg, setbits, 0); }
|
||||
void RegisterClearBits(Register reg, uint8_t clearbits) { RegisterSetAndClearBits(reg, 0, clearbits); }
|
||||
|
||||
uint16_t FIFOReadCount();
|
||||
bool FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples);
|
||||
void FIFOReset();
|
||||
|
||||
bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, uint8_t samples);
|
||||
void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, uint8_t samples);
|
||||
bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
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||||
void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
|
||||
void UpdateTemperature();
|
||||
|
||||
const spi_drdy_gpio_t _drdy_gpio;
|
||||
|
|
@ -145,7 +149,7 @@ private:
|
|||
px4::atomic<uint8_t> _data_ready_count{0};
|
||||
px4::atomic<uint8_t> _fifo_read_samples{0};
|
||||
bool _data_ready_interrupt_enabled{false};
|
||||
uint8_t _checked_register{0};
|
||||
bool _force_fifo_count_check{true};
|
||||
|
||||
enum class STATE : uint8_t {
|
||||
RESET,
|
||||
|
|
@ -156,20 +160,22 @@ private:
|
|||
|
||||
STATE _state{STATE::RESET};
|
||||
|
||||
uint16_t _fifo_empty_interval_us{1000}; // 1000 us / 1000 Hz transfer interval
|
||||
uint16_t _fifo_empty_interval_us{1000}; // default 1000 us / 1000 Hz transfer interval
|
||||
uint8_t _fifo_gyro_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
|
||||
uint8_t _fifo_accel_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / ACCEL_RATE))};
|
||||
|
||||
static constexpr uint8_t size_register_cfg{11};
|
||||
uint8_t _checked_register{0};
|
||||
static constexpr uint8_t size_register_cfg{9};
|
||||
register_config_t _register_cfg[size_register_cfg] {
|
||||
// Register | Set bits, Clear bits
|
||||
{ Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::DEVICE_RESET | PWR_MGMT_1_BIT::SLEEP },
|
||||
{ Register::ACCEL_CONFIG, ACCEL_CONFIG_BIT::ACCEL_FS_SEL_16G, 0 },
|
||||
{ Register::ACCEL_CONFIG2, ACCEL_CONFIG2_BIT::ACCEL_FCHOICE_B, ACCEL_CONFIG2_BIT::FIFO_SIZE },
|
||||
{ Register::GYRO_CONFIG, GYRO_CONFIG_BIT::FS_SEL_2000_DPS, GYRO_CONFIG_BIT::FCHOICE_B_8KHZ_BYPASS_DLPF },
|
||||
{ Register::CONFIG, CONFIG_BIT::DLPF_CFG_BYPASS_DLPF_8KHZ, Bit7 | CONFIG_BIT::FIFO_MODE },
|
||||
{ Register::CONFIG, CONFIG_BIT::FIFO_MODE | CONFIG_BIT::DLPF_CFG_BYPASS_DLPF_8KHZ, 0 },
|
||||
{ Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN | USER_CTRL_BIT::I2C_IF_DIS, USER_CTRL_BIT::FIFO_RST | USER_CTRL_BIT::SIG_COND_RST },
|
||||
{ Register::FIFO_EN, FIFO_EN_BIT::XG_FIFO_EN | FIFO_EN_BIT::YG_FIFO_EN | FIFO_EN_BIT::ZG_FIFO_EN | FIFO_EN_BIT::ACCEL_FIFO_EN, FIFO_EN_BIT::TEMP_FIFO_EN },
|
||||
{ Register::INT_PIN_CFG, INT_PIN_CFG_BIT::INT_LEVEL, 0 },
|
||||
{ Register::INT_ENABLE, INT_ENABLE_BIT::DATA_RDY_INT_EN, 0 }
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ static constexpr uint8_t Bit7 = (1 << 7);
|
|||
|
||||
namespace InvenSense_ICM20689
|
||||
{
|
||||
static constexpr uint32_t SPI_SPEED = 8 * 1000 * 1000; // 8MHz SPI serial interface for communicating with all registers
|
||||
static constexpr uint32_t SPI_SPEED = 8 * 1000 * 1000; // 8MHz SPI serial interface
|
||||
static constexpr uint8_t DIR_READ = 0x80;
|
||||
|
||||
static constexpr uint8_t WHOAMI = 0x98;
|
||||
|
|
@ -70,6 +70,7 @@ enum class Register : uint8_t {
|
|||
|
||||
FIFO_EN = 0x23,
|
||||
|
||||
INT_PIN_CFG = 0x37,
|
||||
INT_ENABLE = 0x38,
|
||||
|
||||
TEMP_OUT_H = 0x41,
|
||||
|
|
@ -127,6 +128,12 @@ enum FIFO_EN_BIT : uint8_t {
|
|||
ACCEL_FIFO_EN = Bit3,
|
||||
};
|
||||
|
||||
// INT_PIN_CFG
|
||||
enum INT_PIN_CFG_BIT : uint8_t {
|
||||
INT_LEVEL = Bit7,
|
||||
INT_RD_CLEAR = Bit4,
|
||||
};
|
||||
|
||||
// INT_ENABLE
|
||||
enum INT_ENABLE_BIT : uint8_t {
|
||||
FIFO_OFLOW_EN = Bit4,
|
||||
|
|
|
|||
Loading…
Reference in New Issue