Definitions for ARMv7-M AIRCR register, Fixes for ADS7843 and SSD1289 driver, Missing build logic for examples/watchdog

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5198 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-09-27 15:29:53 +00:00
parent 9a0be89531
commit c3bc22f07c
6 changed files with 60 additions and 2 deletions

View File

@ -345,3 +345,4 @@
either the nuttx/ or the apps/ source trees. This kludge makes it
possible to configure NxWidgets/NxWM without too much trouble (with
the tradeoff being a kind ugly structure and some maintenance issues).
* apps/examples/Make.defs: Missing support for apps/examples/watchdog.

View File

@ -218,6 +218,10 @@ ifeq ($(CONFIG_EXAMPLES_USBTERM),y)
CONFIGURED_APPS += examples/usbterm
endif
ifeq ($(CONFIG_EXAMPLES_WATCHDOG),y)
CONFIGURED_APPS += examples/watchdog
endif
ifeq ($(CONFIG_EXAMPLES_WGET),y)
CONFIGURED_APPS += examples/wget
endif

View File

@ -3419,4 +3419,10 @@
on the Shenzhou board.
* graphics/nxmu: Correct some bad parameter checking that caused
failures when DEBUG was enabled.
* arch/arm/src/armv7-m/nvic.h: Add bit definitions for the AIRCR
register.
* drivers/input/ads7843.c: Need semaphore protection in logic
that samples the position.
* drivers/lcd/ssd1289.c: On some platforms we are unable to
read the device ID -- reason unknown; workaround in place.

View File

@ -500,6 +500,14 @@
#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
/* Application Interrupt and Reset Control Register (AIRCR) */
/* Bit 0: Reserved */
#define NVIC_AIRC_VECTCLRACTIVE (1 << 1) /* Bit 1: Reserved for debug use */
#define NVIC_AIRC_SYSRESETREQ (1 << 2) /* Bit 2: System reset */
/* Bits 3-14: Reserved */
#define NVIC_AIRC_ENDIANNESS (1 << 15) /* Bit 15: 1=Big endian */
/* Bits 16-31: Reserved */
/* Debug Exception and Monitor Control Register (DEMCR) */
#define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */

View File

@ -555,6 +555,7 @@ static void ads7843e_worker(FAR void *arg)
FAR struct ads7843e_dev_s *priv = (FAR struct ads7843e_dev_s *)arg;
FAR struct ads7843e_config_s *config;
bool pendown;
int ret;
ASSERT(priv != NULL);
@ -565,10 +566,26 @@ static void ads7843e_worker(FAR void *arg)
config = priv->config;
DEBUGASSERT(config != NULL);
/* Disable the watchdog timer */
/* Disable the watchdog timer. This is safe because it is started only
* by this function and this function is serialized on the worker thread.
*/
wd_cancel(priv->wdog);
/* Get exclusive access to the driver data structure */
do
{
ret = sem_wait(&priv->devsem);
/* This should only fail if the wait was canceled by an signal
* (and the worker thread will receive a lot of signals).
*/
DEBUGASSERT(ret == OK || errno == EINTR);
}
while (ret < 0);
/* Check for pen up or down by reading the PENIRQ GPIO. */
pendown = config->pendown(config);
@ -645,6 +662,10 @@ static void ads7843e_worker(FAR void *arg)
errout:
(void)ads7843e_sendcmd(priv, ADS7843_CMD_ENABPINIRQ);
config->enable(config, true);
/* Release our lock on the state structure */
sem_post(&priv->devsem);
}
/****************************************************************************

View File

@ -931,9 +931,27 @@ static inline int ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv)
lcd->select(lcd);
/* Read the device ID. Skip verification of the device ID is the LCD is
* write-only. What choice do we have?
*/
#ifndef CONFIG_LCD_NOGETRUN
id = ssd1289_readreg(lcd, SSD1289_DEVCODE);
lcddbg("LCD ID: %04x\n", id);
if (id != 0)
{
lcddbg("LCD ID: %04x\n", id);
}
/* If we could not get the ID, then let's just assume that this is an SSD1289.
* Perhaps we have some early register access issues. This seems to happen.
* But then perhaps we should not even bother to read the device ID at all?
*/
else
{
lcddbg("No LCD ID, assuming SSD1289\n");
id = SSD1289_DEVCODE_VALUE;
}
/* Check if the ID is for the SSD1289 */