forked from Archive/PX4-Autopilot
fmurt1062-v1:Rev to match Rev A HW
This commit is contained in:
David Sidrane
Daniel Agar
parent
59693dc48e
commit
b4b597251f
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@ -131,20 +131,18 @@
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/* Pin drive characteristics */
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#define USDHC1_DATAX_IOMUX (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | \
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IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
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#define USDHC1_CMD_IOMUX (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | \
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IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
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#define USDHC1_DATAX_IOMUX (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
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#define USDHC1_CMD_IOMUX (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
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#define USDHC1_CLK_IOMUX (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_SPEED_MAX)
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#define USDHC1_CD_IOMUX (0)
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#define USDHC1_CD_IOMUX (IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
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#define PIN_USDHC1_D0 (GPIO_USDHC1_DATA0_1 | USDHC1_DATAX_IOMUX)
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#define PIN_USDHC1_D1 (GPIO_USDHC1_DATA1_1 | USDHC1_DATAX_IOMUX)
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#define PIN_USDHC1_D2 (GPIO_USDHC1_DATA2_1 | USDHC1_DATAX_IOMUX)
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#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3_1 | USDHC1_DATAX_IOMUX)
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#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | USDHC1_CLK_IOMUX)
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#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | USDHC1_CMD_IOMUX)
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#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | USDHC1_CD_IOMUX)
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#define PIN_USDHC1_D0 (GPIO_USDHC1_DATA0_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_02 */
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#define PIN_USDHC1_D1 (GPIO_USDHC1_DATA1_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_03 */
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#define PIN_USDHC1_D2 (GPIO_USDHC1_DATA2_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_04 */
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#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_05 */
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#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | USDHC1_CLK_IOMUX) /* GPIO_SD_B0_01 */
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#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | USDHC1_CMD_IOMUX) /* GPIO_SD_B0_00 */
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#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | USDHC1_CD_IOMUX) /* GPIO_B1_12 */
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/* Ideal 400Khz for initial inquiry.
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* Given input clock 198 Mhz.
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@ -221,51 +219,54 @@
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/* PIO Disambiguation ***************************************************************/
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/* LPUARTs
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*/
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#define LPUART_IOMUX (IOMUX_PULL_UP_22K | IOMUX_DRIVE_40OHM | IOMUX_SLEW_SLOW | IOMUX_SPEED_LOW | IOMUX_SCHMITT_TRIGGER)
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/* GPS 1 */
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#define GPIO_LPUART2_RX (GPIO_LPUART2_RX_1 | IOMUX_UART_DEFAULT) /* EVK J22-8 */ /* GPIO_AD_B1_03 */
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#define GPIO_LPUART2_TX (GPIO_LPUART2_TX_1 | IOMUX_UART_DEFAULT) /* EVK J22-7 */ /* GPIO_AD_B1_02 */
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#define GPIO_LPUART2_RX (GPIO_LPUART2_RX_1 | LPUART_IOMUX) /* EVK J22-8 */ /* GPIO_AD_B1_03 */
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#define GPIO_LPUART2_TX (GPIO_LPUART2_TX_1 | LPUART_IOMUX) /* EVK J22-7 */ /* GPIO_AD_B1_02 */
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#if defined(ON_EVK)
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#define GPIO_LPUART1_RX (GPIO_LPUART1_RX_1 | LPUART_IOMUX) /* GPIO_AD_B0_13 EVK J46-2 */
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#define GPIO_LPUART1_TX (GPIO_LPUART1_TX_1 | LPUART_IOMUX) /* GPIO_AD_B0_12 EVK J46-2 */
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#define GPIO_LPUART3_RX (GPIO_LPUART3_RX_1 | LPUART_IOMUX) /* GPIO_AD_B1_07 EVK J22-1 */
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#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_1 | LPUART_IOMUX) /* GPIO_AD_B1_06 EVK J22-2 */
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#else
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/* Telem 2 */
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#define HS_INPUT_IOMUX (IOMUX_CMOS_INPUT | IOMUX_SLEW_SLOW | IOMUX_DRIVE_HIZ | IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_47K)
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#define HS_OUTPUT_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_SLEW_FAST | IOMUX_DRIVE_33OHM | IOMUX_SPEED_MEDIUM | IOMUX_PULL_KEEP)
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#if defined(ON_EVK)
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#define GPIO_LPUART1_RX (GPIO_LPUART1_RX_1 | IOMUX_UART_DEFAULT) /* GPIO_AD_B0_13 EVK J46-2 */
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#define GPIO_LPUART1_TX (GPIO_LPUART1_TX_1 | IOMUX_UART_DEFAULT) /* GPIO_AD_B0_12 EVK J46-2 */
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#define GPIO_LPUART3_RX (GPIO_LPUART3_RX_1 | IOMUX_UART_DEFAULT) /* GPIO_AD_B1_07 EVK J22-1 */
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#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_1 | IOMUX_UART_DEFAULT) /* GPIO_AD_B1_06 EVK J22-2 */
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#else
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#define GPIO_LPUART3_RX (GPIO_LPUART3_RX_3 | IOMUX_UART_DEFAULT) /* GPIO_B0_09 */
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#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_3 | IOMUX_UART_DEFAULT) /* GPIO_B0_08 */
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#define GPIO_LPUART3_CTS /* GPIO_AD_B0_08 GPIO1 Pin 8 (GPIO only, no HW Flow control) */ (GPIO_PORT1 | GPIO_PIN8 | GPIO_INPUT | HS_INPUT_IOMUX)
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#define GPIO_LPUART3_RTS /* GPIO_EMC_24 GPIO4 Pin 24 (GPIO only, no HW Flow control) */ (GPIO_PORT4 | GPIO_PIN14 | GPIO_OUTPUT | HS_OUTPUT_IOMUX)
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#define GPIO_LPUART3_RX (GPIO_LPUART3_RX_3 | LPUART_IOMUX) /* GPIO_B0_09 */
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#define GPIO_LPUART3_TX (GPIO_LPUART3_TX_3 | LPUART_IOMUX) /* GPIO_B0_08 */
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#define GPIO_LPUART3_CTS (GPIO_PORT1 | GPIO_PIN8 | GPIO_INPUT | HS_INPUT_IOMUX) /* GPIO_AD_B0_08 GPIO1 Pin 8 (GPIO only, no HW Flow control) */
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#define GPIO_LPUART3_RTS (GPIO_PORT4 | GPIO_PIN24 | GPIO_OUTPUT | HS_OUTPUT_IOMUX) /* GPIO_EMC_24 GPIO4 Pin 24 (GPIO only, no HW Flow control) */
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#endif
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/* Telem 1 */
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#define GPIO_LPUART4_RX GPIO_LPUART4_RX_1 /* GPIO_EMC_20 */
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#define GPIO_LPUART4_TX GPIO_LPUART4_TX_1 /* GPIO_EMC_19 */
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/* GPIO_LPUART4_CTS GPIO_EMC_17 No Alternate */
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/* GPIO_LPUART4_RTS GPIO_EMC_18 No Alternate */
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#define GPIO_LPUART4_RX (GPIO_LPUART4_RX_2 | LPUART_IOMUX) /* GPIO_EMC_20 */
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#define GPIO_LPUART4_TX (GPIO_LPUART4_TX_2 | LPUART_IOMUX) /* GPIO_EMC_19 */
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#define GPIO_LPUART4_CTS (GPIO_LPUART4_CTS_1 | LPUART_IOMUX) /* GPIO_EMC_17 */
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#define GPIO_LPUART4_RTS (GPIO_LPUART4_RTS_1 | LPUART_IOMUX) /* GPIO_EMC_18 */
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/* GPS2 */
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#define GPIO_LPUART5_RX GPIO_LPUART5_RX_1 /* GPIO_B1_13 */
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#define GPIO_LPUART5_TX GPIO_LPUART5_TX_1 /* GPIO_B1_12 */
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#define GPIO_LPUART5_RX (GPIO_LPUART5_RX_1 | LPUART_IOMUX) /* GPIO_B1_13 */
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#define GPIO_LPUART5_TX (GPIO_LPUART5_TX_2 | LPUART_IOMUX) /* GPIO_EMC_23 */
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/* RC INPUT single wire mode on TX, RX is not used */
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#define GPIO_LPUART6_RX GPIO_LPUART6_RX_1 /* GPIO_EMC_26 */
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#define GPIO_LPUART6_TX GPIO_LPUART6_TX_1 /* GPIO_EMC_25 */
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#define GPIO_LPUART6_RX (GPIO_LPUART6_RX_2 | LPUART_IOMUX) /* GPIO_EMC_26 */
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#define GPIO_LPUART6_TX (GPIO_LPUART6_TX_2 | LPUART_IOMUX) /* GPIO_EMC_25 */
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#define GPIO_LPUART7_RX GPIO_LPUART7_RX_1 /* GPIO_EMC_32 */
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#define GPIO_LPUART7_TX GPIO_LPUART7_TX_1 /* GPIO_EMC_31 */
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#define GPIO_LPUART7_RX (GPIO_LPUART7_RX_1 | LPUART_IOMUX) /* GPIO_EMC_32 */
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#define GPIO_LPUART7_TX (GPIO_LPUART7_TX_1 | LPUART_IOMUX) /* GPIO_EMC_31 */
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#define GPIO_LPUART8_RX GPIO_LPUART3_RX_1 /* GPIO_EMC_39 */
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#define GPIO_LPUART8_TX GPIO_LPUART3_TX_1 /* GPIO_EMC_38 */
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#define GPIO_LPUART8_RX (GPIO_LPUART3_RX_2 | LPUART_IOMUX) /* GPIO_EMC_39 */
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#define GPIO_LPUART8_TX (GPIO_LPUART3_TX_3 | LPUART_IOMUX) /* GPIO_EMC_38 */
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/* CAN
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*
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@ -273,58 +274,62 @@
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* CAN2 is routed to transceiver.
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* CAN3 is routed to transceiver.
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*/
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#define GPIO_FLEXCAN1_RX GPIO_FLEXCAN1_RX_2 /* GPIO_B0_03 */
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#define GPIO_FLEXCAN1_TX GPIO_FLEXCAN1_TX_2 /* GPIO_B0_02 */
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#define GPIO_FLEXCAN2_RX GPIO_FLEXCAN2_RX_1 /* GPIO_AD_B0_03 */
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#define GPIO_FLEXCAN2_TX GPIO_FLEXCAN2_TX_1 /* GPIO_AD_B0_02 */
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#define GPIO_FLEXCAN3_RX GPIO_FLEXCAN3_RX_1 /* GPIO_AD_B0_11 */
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#define GPIO_FLEXCAN3_TX GPIO_FLEXCAN3_TX_3 /* GPIO_EMC_36 */
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#define FLEXCAN_IOMUX (IOMUX_PULL_UP_100K | IOMUX_DRIVE_40OHM | IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM)
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#define GPIO_FLEXCAN1_RX (GPIO_FLEXCAN1_RX_2 | FLEXCAN_IOMUX) /* GPIO_B0_03 */
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#define GPIO_FLEXCAN1_TX (GPIO_FLEXCAN1_TX_4 | FLEXCAN_IOMUX) /* GPIO_SD_B1_02 */
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#define GPIO_FLEXCAN2_RX (GPIO_FLEXCAN2_RX_1 | FLEXCAN_IOMUX) /* GPIO_AD_B0_03 */
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#define GPIO_FLEXCAN2_TX (GPIO_FLEXCAN2_TX_1 | FLEXCAN_IOMUX) /* GPIO_AD_B0_02 */
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#define GPIO_FLEXCAN3_RX (GPIO_FLEXCAN3_RX_1 | FLEXCAN_IOMUX) /* GPIO_AD_B0_11 */
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#define GPIO_FLEXCAN3_TX (GPIO_FLEXCAN3_TX_3 | FLEXCAN_IOMUX) /* GPIO_EMC_36 */
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/* LPSPI */
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#define LPSPI_IOMUX (IOMUX_PULL_UP_100K | IOMUX_DRIVE_33OHM | IOMUX_SLEW_FAST | IOMUX_SPEED_MAX)
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#define GPIO_LPSPI1_SCK GPIO_LPSPI1_SCK_1 /* GPIO_EMC_27 */
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#define GPIO_LPSPI1_MISO GPIO_LPSPI1_SDI_1 /* GPIO_EMC_29 */
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#define GPIO_LPSPI1_MOSI GPIO_LPSPI1_SDO_1 /* GPIO_EMC_28 */
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#define GPIO_LPSPI1_SCK (GPIO_LPSPI1_SCK_1 | LPSPI_IOMUX) /* GPIO_EMC_27 */
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#define GPIO_LPSPI1_MISO (GPIO_LPSPI1_SDI_1 | LPSPI_IOMUX) /* GPIO_EMC_29 */
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#define GPIO_LPSPI1_MOSI (GPIO_LPSPI1_SDO_1 | LPSPI_IOMUX) /* GPIO_EMC_28 */
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#if defined(ON_EVK)
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#define GPIO_LPSPI2_SCK GPIO_LPSPI2_SCK_2 /* EVK J24-6 POP R280 GPIO_SD_B0_00 */
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#define GPIO_LPSPI2_MISO GPIO_LPSPI1_SDI_2 /* EVK J24-5 POP R278 GPIO_SD_B0_03 */
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#define GPIO_LPSPI2_MOSI GPIO_LPSPI1_SDO_2 /* EVK J24-4 POP R279 GPIO_SD_B0_02 */
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#define GPIO_LPSPI2_SCK (GPIO_LPSPI2_SCK_2 | LPSPI_IOMUX) /* EVK J24-6 POP R280 GPIO_SD_B0_00 */
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#define GPIO_LPSPI2_MISO (GPIO_LPSPI1_SDI_2 | LPSPI_IOMUX) /* EVK J24-5 POP R278 GPIO_SD_B0_03 */
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#define GPIO_LPSPI2_MOSI (GPIO_LPSPI1_SDO_2 | LPSPI_IOMUX) /* EVK J24-4 POP R279 GPIO_SD_B0_02 */
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#else
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#define GPIO_LPSPI2_SCK GPIO_LPSPI2_SCK_1 /* GPIO_EMC_00 */
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#define GPIO_LPSPI2_MISO GPIO_LPSPI2_SDI_1 /* GPIO_EMC_03 */
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#define GPIO_LPSPI2_MOSI GPIO_LPSPI2_SDO_1 /* GPIO_EMC_02 */
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#define GPIO_LPSPI2_SCK (GPIO_LPSPI2_SCK_1 | LPSPI_IOMUX) /* GPIO_EMC_00 */
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#define GPIO_LPSPI2_MISO (GPIO_LPSPI2_SDI_1 | LPSPI_IOMUX) /* GPIO_EMC_03 */
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#define GPIO_LPSPI2_MOSI (GPIO_LPSPI2_SDO_1 | LPSPI_IOMUX) /* GPIO_EMC_02 */
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#endif
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#define GPIO_LPSPI3_SCK GPIO_LPSPI3_SCK_1 /* GPIO_AD_B1_15 */
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#define GPIO_LPSPI3_MISO GPIO_LPSPI3_SDI_1 /* GPIO_AD_B1_13 */
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#define GPIO_LPSPI3_MOSI GPIO_LPSPI3_SDO_1 /* GPIO_AD_B1_14 */
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#define GPIO_LPSPI3_SCK (GPIO_LPSPI3_SCK_1 | LPSPI_IOMUX) /* GPIO_AD_B1_15 */
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#define GPIO_LPSPI3_MISO (GPIO_LPSPI3_SDI_1 | LPSPI_IOMUX) /* GPIO_AD_B1_13 */
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#define GPIO_LPSPI3_MOSI (GPIO_LPSPI3_SDO_1 | LPSPI_IOMUX) /* GPIO_AD_B1_14 */
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#define GPIO_LPSPI4_SCK GPIO_LPSPI4_SCK_1 /* GPIO_B1_07 */
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#define GPIO_LPSPI4_MISO GPIO_LPSPI4_SDI_1 /* GPIO_B1_05 */
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#define GPIO_LPSPI4_MOSI GPIO_LPSPI4_SDO_1 /* GPIO_B1_06 */
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#define GPIO_LPSPI4_SCK (GPIO_LPSPI4_SCK_1 | LPSPI_IOMUX) /* GPIO_B1_07 */
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#define GPIO_LPSPI4_MISO (GPIO_LPSPI4_SDI_1 | LPSPI_IOMUX) /* GPIO_B1_05 */
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#define GPIO_LPSPI4_MOSI (GPIO_LPSPI4_SDO_2 | LPSPI_IOMUX) /* GPIO_B0_02 */
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/* LPI2Cs */
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#define LPI2C_IOMUX (GPIO_OUTPUT | IOMUX_SPEED_MAX | IOMUX_SLEW_FAST | IOMUX_DRIVE_33OHM | IOMUX_OPENDRAIN | IOMUX_PULL_NONE)
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#define LPI2C_IOMUX (GPIO_OUTPUT | IOMUX_SPEED_MAX | IOMUX_SLEW_FAST | IOMUX_DRIVE_33OHM | IOMUX_OPENDRAIN | IOMUX_PULL_NONE)
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#define LPI2C_IO_IOMUX (GPIO_OUTPUT | IOMUX_SPEED_MAX | IOMUX_SLEW_FAST | IOMUX_DRIVE_33OHM | IOMUX_CMOS_OUTPUT | IOMUX_PULL_NONE)
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#define GPIO_LPI2C1_SDA GPIO_LPI2C1_SDA_2 /* EVK J24-9 R276 */ /* GPIO_AD_B1_01 */
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#define GPIO_LPI2C1_SCL GPIO_LPI2C1_SCL_2 /* EVK J24-10 R277 */ /* GPIO_AD_B1_00 */
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#define GPIO_LPI2C1_SDA (GPIO_LPI2C1_SDA_2 | LPI2C_IOMUX) /* EVK J24-9 R276 */ /* GPIO_AD_B1_01 */
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#define GPIO_LPI2C1_SCL (GPIO_LPI2C1_SCL_2 | LPI2C_IOMUX) /* EVK J24-10 R277 */ /* GPIO_AD_B1_00 */
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#define GPIO_LPI2C1_SDA_GPIO (GPIO_PORT1 | GPIO_PIN17 | LPI2C_IOMUX)
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#define GPIO_LPI2C1_SCL_GPIO (GPIO_PORT1 | GPIO_PIN16 | LPI2C_IOMUX)
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#define GPIO_LPI2C1_SDA_GPIO (GPIO_PORT1 | GPIO_PIN17 | LPI2C_IO_IOMUX) /* GPIO_AD_B1_01 GPIO1_IO17 */
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#define GPIO_LPI2C1_SCL_GPIO (GPIO_PORT1 | GPIO_PIN16 | LPI2C_IO_IOMUX) /* GPIO_AD_B1_00 GPIO1_IO16 */
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#define GPIO_LPI2C2_SDA GPIO_LPI2C2_SDA_1 /* EVK J8-A25 */ /* GPIO_B0_05 */
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#define GPIO_LPI2C2_SCL GPIO_LPI2C2_SCL_1 /* EVK J8-A24 */ /* GPIO_B0_04 */
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#define GPIO_LPI2C2_SDA (GPIO_LPI2C2_SDA_1 | LPI2C_IOMUX) /* EVK J8-A25 */ /* GPIO_B0_05 */
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#define GPIO_LPI2C2_SCL (GPIO_LPI2C2_SCL_1 | LPI2C_IOMUX) /* EVK J8-A24 */ /* GPIO_B0_04 */
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#define GPIO_LPI2C2_SDA_GPIO (GPIO_PORT2 | GPIO_PIN5 | LPI2C_IOMUX)
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#define GPIO_LPI2C2_SCL_GPIO (GPIO_PORT2 | GPIO_PIN4 | LPI2C_IOMUX)
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#define GPIO_LPI2C2_SDA_GPIO (GPIO_PORT2 | GPIO_PIN5 | LPI2C_IO_IOMUX) /* GPIO_B0_05 GPIO2_IO5 */
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#define GPIO_LPI2C2_SCL_GPIO (GPIO_PORT2 | GPIO_PIN4 | LPI2C_IO_IOMUX) /* GPIO_B0_04 GPIO2_IO4 */
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#define GPIO_LPI2C3_SDA GPIO_LPI2C3_SDA_2 /* GPIO_EMC_21 */
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#define GPIO_LPI2C3_SCL GPIO_LPI2C3_SCL_2 /* GPIO_EMC_22 */
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#define GPIO_LPI2C3_SDA (GPIO_LPI2C3_SDA_2 | LPI2C_IOMUX) /* GPIO_EMC_21 */
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#define GPIO_LPI2C3_SCL (GPIO_LPI2C3_SCL_2 | LPI2C_IOMUX) /* GPIO_EMC_22 */
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#define GPIO_LPI2C3_SDA_GPIO (GPIO_PORT4 | GPIO_PIN21 | LPI2C_IOMUX)
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#define GPIO_LPI2C3_SCL_GPIO (GPIO_PORT4 | GPIO_PIN22 | LPI2C_IOMUX)
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#define GPIO_LPI2C3_SDA_GPIO (GPIO_PORT4 | GPIO_PIN21 | LPI2C_IO_IOMUX) /* GPIO_EMC_21 GPIO4_IO21 */
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#define GPIO_LPI2C3_SCL_GPIO (GPIO_PORT4 | GPIO_PIN22 | LPI2C_IO_IOMUX) /* GPIO_EMC_22 GPIO4_IO22 */
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/* Board provides GPIO or other Hardware for signaling to timing analyzer */
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@ -38,7 +38,7 @@ px4_add_library(drivers_board
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init.c
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led.c
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sdhc.c
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spi.c
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spi.cpp
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timer_config.c
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usb.c
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manifest.c
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/* PX4IO connection configuration */
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#if 0 // There is no PX4 Support on first out
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#if 0 // There is no PX4IO Support on first out
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// This requires serial DMA driver
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#define BOARD_USES_PX4IO_VERSION 2
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#define PX4IO_SERIAL_DEVICE "/dev/ttyS6"
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/* Configuration ************************************************************************************/
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/* FMURT1062 GPIOs ***********************************************************************************/
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/* LEDs */
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/* An RGB LED is connected through GPIO as shown below:
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*/
|
||||
#define LED_IOMUX (IOMUX_OPENDRAIN | IOMUX_PULL_NONE | IOMUX_DRIVE_33OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_SLOW)
|
||||
#define GPIO_nLED_RED (GPIO_PORT2 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | LED_IOMUX)
|
||||
#define GPIO_nLED_GREEN (GPIO_PORT2 | GPIO_PIN1 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | LED_IOMUX)
|
||||
#define GPIO_nLED_BLUE (GPIO_PORT2 | GPIO_PIN24 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | LED_IOMUX)
|
||||
#define GPIO_nLED_RED /* GPIO_B0_00 QTIMER1_TIMER0 GPIO2_IO0 */ (GPIO_PORT2 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | LED_IOMUX)
|
||||
#define GPIO_nLED_GREEN /* GPIO_B0_01 QTIMER1_TIMER1 GPIO2_IO1 */ (GPIO_PORT2 | GPIO_PIN1 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | LED_IOMUX)
|
||||
#define GPIO_nLED_BLUE /* GPIO_B1_08 QTIMER1_TIMER3 GPIO2_IO24 */ (GPIO_PORT2 | GPIO_PIN24 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | LED_IOMUX)
|
||||
|
||||
#define BOARD_HAS_CONTROL_STATUS_LEDS 1
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_STATE_LED LED_BLUE
|
||||
#define BOARD_HAS_CONTROL_STATUS_LEDS 1
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_STATE_LED LED_BLUE
|
||||
|
||||
/* SENSORS are on SPI1, 3
|
||||
* MEMORY is on bus SPI2
|
||||
* MS5611 is on bus SPI4
|
||||
*/
|
||||
|
||||
#define PX4_SPI_BUS_SENSORS 1
|
||||
#define PX4_SPI_BUS_MEMORY 2
|
||||
#define PX4_SPI_BUS_BARO 3
|
||||
#define PX4_SPI_BUS_EXTERNAL1 4
|
||||
#define PX4_SPI_BUS_SENSORS 1
|
||||
#define PX4_SPI_BUS_MEMORY 2
|
||||
#define PX4_SPI_BUS_BARO 3
|
||||
#define PX4_SPI_BUS_EXTERNAL1 4
|
||||
|
||||
/*
|
||||
* Define the ability to shut off off the sensor signals
|
||||
|
|
@ -124,58 +123,67 @@
|
|||
#if defined(ON_EVK) && defined(ON_EVK_SPI)
|
||||
#define GPIO_SPI1_CS1_ICM20689 /* J24-3 POP R280 GPIO_SD_B0_01 */ (GPIO_PORT3 | GPIO_PIN13 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#else
|
||||
#define GPIO_SPI1_CS1_ICM20689 (GPIO_PORT3 | GPIO_PIN26 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define GPIO_SPI1_CS2_ICM20602 (GPIO_PORT3 | GPIO_PIN27 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define GPIO_SPI1_CS3_BMI055_GYRO (GPIO_PORT2 | GPIO_PIN26 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define GPIO_SPI1_CS4_BMI055_ACC (GPIO_PORT2 | GPIO_PIN31 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define GPIO_SPI1_CS1_ICM20689 /* GPIO_EMC_40 GPIO3_IO26 */ (GPIO_PORT3 | GPIO_PIN26 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
// GPIO_SPI1_CS2_ICM20602 is not wired from CPU
|
||||
#define GPIO_SPI1_CS3_BMI055_GYRO /* GPIO_B1_10 GPIO2_IO26 */ (GPIO_PORT2 | GPIO_PIN26 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define GPIO_SPI1_CS4_BMI055_ACCEL /* GPIO_B1_15 GPIO2_IO31 */ (GPIO_PORT2 | GPIO_PIN31 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#endif
|
||||
|
||||
#define SPI1_CS5_AUX_MEM /* GPIO_SD_B1_00 GPIO3_IO00 */ (GPIO_PORT3 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
|
||||
/* Define the SPI1 Data Ready interrupts */
|
||||
|
||||
#define DRDY_IOMUX (IOMUX_SCHMITT_TRIGGER | IOMUX_PULL_UP_47K | IOMUX_DRIVE_HIZ)
|
||||
|
||||
// todo add IRQ-ness!
|
||||
#define GPIO_SPI1_DRDY1_ICM20689 (GPIO_PORT4 | GPIO_PIN15 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define GPIO_SPI1_DRDY2_BMI055_GYRO (GPIO_PORT4 | GPIO_PIN16 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define GPIO_SPI1_DRDY3_BMI055_ACC (GPIO_PORT3 | GPIO_PIN23 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define GPIO_SPI1_DRDY4_ICM20602 (GPIO_PORT3 | GPIO_PIN27 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define GPIO_SPI1_DRDY5_BMI055_GYRO (GPIO_PORT4 | GPIO_PIN13 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define GPIO_SPI1_DRDY6_BMI055_ACC (GPIO_PORT2 | GPIO_PIN7 | GPIO_INPUT | DRDY_IOMUX)
|
||||
|
||||
#define GPIO_SPIAUX_CS_MEM (GPIO_PORT5 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define GPIO_SPI1_DRDY1_ICM20689 /* GPIO_EMC_15 GPIO4_IO15 */ (GPIO_PORT4 | GPIO_PIN15 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define GPIO_SPI1_DRDY2_BMI055_GYRO /* GPIO_EMC_16 GPIO4_IO16 */ (GPIO_PORT4 | GPIO_PIN16 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define GPIO_SPI1_DRDY3_BMI055_ACCEL /* GPIO_EMC_37 GPIO3_IO23 */ (GPIO_PORT3 | GPIO_PIN23 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define SPI1_DRDY4_ICM20602 /* GPIO_EMC_12 GPIO4_IO12 N.B . The ICM20602 CS is not wired */ (GPIO_PORT4 | GPIO_PIN27 | GPIO_INPUT | DRDY_IOMUX)
|
||||
|
||||
/* SPI1 off */
|
||||
|
||||
#define GPIO_SPI1_SCK_OFF _PIN_OFF(GPIO_LPSPI1_SCK)
|
||||
#define GPIO_SPI1_MISO_OFF _PIN_OFF(GPIO_LPSPI1_MISO)
|
||||
#define GPIO_SPI1_MOSI_OFF _PIN_OFF(GPIO_LPSPI1_MOSI)
|
||||
#define _GPIO_LPSPI1_SCK /* GPIO_EMC_27 GPIO4_IO27 */ (GPIO_PORT4 | GPIO_PIN27 | CS_IOMUX)
|
||||
#define _GPIO_LPSPI1_MISO /* GPIO_EMC_29 GPIO4_IO29 */ (GPIO_PORT4 | GPIO_PIN29 | CS_IOMUX)
|
||||
#define _GPIO_LPSPI1_MOSI /* GPIO_EMC_28 GPIO4_IO28 */ (GPIO_PORT4 | GPIO_PIN28 | CS_IOMUX)
|
||||
|
||||
#define GPIO_SPI1_SCK_OFF _PIN_OFF(_GPIO_LPSPI1_SCK)
|
||||
#define GPIO_SPI1_MISO_OFF _PIN_OFF(_GPIO_LPSPI1_MISO)
|
||||
#define GPIO_SPI1_MOSI_OFF _PIN_OFF(_GPIO_LPSPI1_MOSI)
|
||||
|
||||
#define GPIO_DRDY_OFF_SPI1_DRDY1_ICM20689 _PIN_OFF(GPIO_SPI1_DRDY1_ICM20689)
|
||||
#define GPIO_DRDY_OFF_SPI1_DRDY2_BMI055_GYRO _PIN_OFF(GPIO_SPI1_DRDY2_BMI055_GYRO)
|
||||
#define GPIO_DRDY_OFF_SPI1_DRDY3_BMI055_ACC _PIN_OFF(GPIO_SPI1_DRDY3_BMI055_ACC)
|
||||
#define GPIO_DRDY_OFF_SPI1_DRDY3_BMI055_ACC _PIN_OFF(GPIO_SPI1_DRDY3_BMI055_ACCEL)
|
||||
#define GPIO_DRDY_OFF_SPI1_DRDY4_ICM20602 _PIN_OFF(GPIO_SPI1_DRDY4_ICM20602)
|
||||
#define GPIO_DRDY_OFF_SPI1_DRDY5_BMI055_GYRO _PIN_OFF(GPIO_SPI1_DRDY5_BMI055_GYRO)
|
||||
#define GPIO_DRDY_OFF_SPI1_DRDY6_BMI055_ACC _PIN_OFF(GPIO_SPI1_DRDY6_BMI055_ACC)
|
||||
|
||||
/* SPI 2 CS */
|
||||
|
||||
#define GPIO_SPI2_CS_FRAM (GPIO_PORT3 | GPIO_PIN20 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define GPIO_SPI2_CS_FRAM /* GPIO_EMC_34 G GPIO3_IO20 */ (GPIO_PORT3 | GPIO_PIN20 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
|
||||
/* SPI 3 CS */
|
||||
|
||||
#define GPIO_SPI3_CS1_MS5611 (GPIO_PORT4 | GPIO_PIN14 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define GPIO_SPI3_CS1_MS5611 /* GPIO_EMC_14 GPIO4_IO14 */ (GPIO_PORT4 | GPIO_PIN14 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
|
||||
#define _GPIO_LPSPI3_SCK /* GPIO_AD_B1_15 GPIO1_IO27 */ (GPIO_PORT1 | GPIO_PIN31 | CS_IOMUX)
|
||||
#define _GPIO_LPSPI3_MISO /* GPIO_AD_B1_13 GPIO1_IO27 */ (GPIO_PORT1 | GPIO_PIN29 | CS_IOMUX)
|
||||
#define _GPIO_LPSPI3_MOSI /* GPIO_AD_B1_14 GPIO1_IO27 */ (GPIO_PORT1 | GPIO_PIN30 | CS_IOMUX)
|
||||
|
||||
#define GPIO_SPI3_SCK_OFF _PIN_OFF(_GPIO_LPSPI3_SCK)
|
||||
#define GPIO_SPI3_MISO_OFF _PIN_OFF(_GPIO_LPSPI3_MISO)
|
||||
#define GPIO_SPI3_MOSI_OFF _PIN_OFF(_GPIO_LPSPI3_MOSI)
|
||||
|
||||
/* SPI 4 CS */
|
||||
|
||||
#define SPI4_CS1_EXTERNAL1 (GPIO_PORT4 | GPIO_PIN7 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define SPI4_CS2_EXTERNAL1 (GPIO_PORT2 | GPIO_PIN30 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define SPI4_CS3_EXTERNAL1 (GPIO_PORT4 | GPIO_PIN11 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define SPI4_CS1_EXTERNAL1 /* GPIO_EMC_07 GPIO4_IO07 */ (GPIO_PORT4 | GPIO_PIN7 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define SPI4_CS2_EXTERNAL1 /* GPIO_B1_14 GPIO2_IO30 */ (GPIO_PORT2 | GPIO_PIN30 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
#define SPI4_CS3_EXTERNAL1 /* GPIO_EMC_11 GPIO4_IO011 */ (GPIO_PORT4 | GPIO_PIN11 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | CS_IOMUX)
|
||||
|
||||
/* Define the SPI4 Data Ready and Control signals */
|
||||
|
||||
#define GPIO_SPI4_DRDY7_EXTERNAL1 (GPIO_PORT3 | GPIO_PIN21 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define GPIO_nSPI4_RESET_EXTERNAL1 (GPIO_PORT2 | GPIO_PIN16 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | OUT_IOMUX)
|
||||
#define GPIO_SPI4_SYNC_EXTERNAL1 (GPIO_PORT4 | GPIO_PIN5 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | OUT_IOMUX)
|
||||
#define GPIO_SPI4_DRDY7_EXTERNAL1 /* GPIO_EMC_35 GPIO3_IO21*/ (GPIO_PORT3 | GPIO_PIN21 | GPIO_INPUT | DRDY_IOMUX)
|
||||
#define GPIO_nSPI4_RESET_EXTERNAL1 /* GPIO_B1_00 GPIO2_IO16 */ (GPIO_PORT2 | GPIO_PIN16 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | OUT_IOMUX)
|
||||
#define GPIO_SPI4_SYNC_EXTERNAL1 /* GPIO_EMC_05 GPIO4_IO5 */(GPIO_PORT4 | GPIO_PIN5 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | OUT_IOMUX)
|
||||
|
||||
#define GPIO_DRDY_OFF_SPI4_DRDY7_EXTERNAL1 _PIN_OFF(GPIO_SPI4_DRDY7_EXTERNAL1)
|
||||
#define GPIO_nSPI4_RESET_EXTERNAL1_OFF _PIN_OFF(GPIO_nSPI4_RESET_EXTERNAL1)
|
||||
|
|
@ -191,12 +199,11 @@
|
|||
/* ^ END Legacy SPI defines TODO: fix this with enumeration */
|
||||
|
||||
#define PX4_SPIDEV_ICM_20689 PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,0)
|
||||
#define PX4_SPIDEV_ICM_20602 PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,1)
|
||||
#define PX4_SPIDEV_BMI055_GYR PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,2)
|
||||
#define PX4_SPIDEV_BMI055_ACC PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,3)
|
||||
#define PX4_SPIDEV_AUX_MEM PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,4)
|
||||
#define PX4_SPIDEV_BMI055_GYR PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,1)
|
||||
#define PX4_SPIDEV_BMI055_ACC PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,2)
|
||||
#define PX4_SPIDEV_AUX_MEM PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,3)
|
||||
|
||||
#define PX4_SENSOR_BUS_CS_GPIO {GPIO_SPI1_CS1_ICM20689, GPIO_SPI1_CS2_ICM20602, GPIO_SPI1_CS3_BMI055_GYRO, GPIO_SPI1_CS4_BMI055_ACC, GPIO_SPIAUX_CS_MEM}
|
||||
#define PX4_SENSOR_BUS_CS_GPIO {GPIO_SPI1_CS1_ICM20689, GPIO_SPI1_CS3_BMI055_GYRO, GPIO_SPI1_CS4_BMI055_ACCEL, SPI1_CS5_AUX_MEM}
|
||||
#define PX4_SENSORS_BUS_FIRST_CS PX4_SPIDEV_ICM_20689
|
||||
#define PX4_SENSORS_BUS_LAST_CS PX4_SPIDEV_AUX_MEM
|
||||
|
||||
|
|
@ -219,8 +226,6 @@
|
|||
|
||||
/* I2C busses */
|
||||
|
||||
/* I2C busses */
|
||||
|
||||
#define PX4_I2C_BUS_EXPANSION 1
|
||||
#define PX4_I2C_BUS_EXPANSION1 2
|
||||
#define PX4_I2C_BUS_ONBOARD 3
|
||||
|
|
@ -293,9 +298,8 @@
|
|||
(1 << ADC_HW_VER_SENSE_CHANNEL) | \
|
||||
(1 << ADC_HW_REV_SENSE_CHANNEL) | \
|
||||
(1 << ADC1_SPARE_1_CHANNEL))
|
||||
#endif
|
||||
/* Define Battery 1 Voltage Divider and A per V
|
||||
*/
|
||||
|
||||
/* Define Battery 1 Voltage Divider and A per V */
|
||||
|
||||
#define BOARD_BATTERY1_V_DIV (18.1f) /* measured with the provided PM board */
|
||||
#define BOARD_BATTERY1_A_PER_V (36.367515152f)
|
||||
|
|
@ -310,13 +314,12 @@
|
|||
|
||||
#define HW_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_NONE | IOMUX_DRIVE_33OHM | IOMUX_SPEED_MAX | IOMUX_SLEW_FAST)
|
||||
|
||||
#define GPIO_HW_REV_DRIVE /* GPIO_AD_B0_00 GPIO1_IO00 */ (GPIO_PORT1 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_SET | HW_IOMUX)
|
||||
#define GPIO_HW_REV_SENSE /* GPIO_AD_B1_08 GPIO1 Pin 24 */ ADC1_GPIO(13, 24)
|
||||
#define GPIO_HW_VER_DRIVE /* GPIO_AD_B0_04 GPIO1_IO04 */ (GPIO_PORT1 | GPIO_PIN4 | GPIO_OUTPUT | GPIO_OUTPUT_SET | HW_IOMUX)
|
||||
#define GPIO_HW_VER_SENSE /* GPIO_AD_B1_04 GPIO1 Pin 20 */ ADC1_GPIO(9, 20)
|
||||
#define HW_INFO_INIT {'V','5','x', 'x',0}
|
||||
#define HW_INFO_INIT_VER 2
|
||||
#define HW_INFO_INIT_REV 3
|
||||
#define GPIO_HW_VER_REV_DRIVE /* GPIO_AD_B0_01 GPIO1_IO01 */ (GPIO_PORT1 | GPIO_PIN1 | GPIO_OUTPUT | GPIO_OUTPUT_SET | HW_IOMUX)
|
||||
#define GPIO_HW_REV_SENSE /* GPIO_AD_B1_08 GPIO1 Pin 24 */ ADC1_GPIO(13, 24)
|
||||
#define GPIO_HW_VER_SENSE /* GPIO_AD_B1_04 GPIO1 Pin 20 */ ADC1_GPIO(9, 20)
|
||||
#define HW_INFO_INIT {'V','5','x', 'x',0}
|
||||
#define HW_INFO_INIT_VER 2
|
||||
#define HW_INFO_INIT_REV 3
|
||||
/* CAN Silence
|
||||
*
|
||||
* Silent mode control \ ESC Mux select
|
||||
|
|
@ -330,13 +333,17 @@
|
|||
/* HEATER
|
||||
* PWM in future
|
||||
*/
|
||||
#define GPIO_HEATER_OUTPUT /* GPIO_B1_09 QTIMER2_TIMER3 GPIO2 Pin 25 */ GPIO_QTIMER2_TIMER3_1
|
||||
#define HEATER_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_NONE | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_FAST)
|
||||
#define GPIO_HEATER_OUTPUT /* GPIO_B1_09 QTIMER2_TIMER3 GPIO2_IO25 */ (GPIO_QTIMER2_TIMER3_1 | HEATER_IOMUX)
|
||||
|
||||
/* PWM Capture
|
||||
*
|
||||
* 3 PWM Capture inputs are not supported
|
||||
* 2 PWM Capture inputs are supported
|
||||
*/
|
||||
#define DIRECT_PWM_CAPTURE_CHANNELS 0
|
||||
#define DIRECT_PWM_CAPTURE_CHANNELS 2
|
||||
#define CAP_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_NONE | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_FAST)
|
||||
#define PIN_FLEXPWM2_PWMB0 /* P2:7 PWM2 B0 FMU_CAP1 */ (CAP_IOMUX | GPIO_FLEXPWM2_PWMB00_2)
|
||||
#define PIN_FLEXPWM2_PWMB3 /* P3:3 PWM2 A1 FMU_CAP2 */ (CAP_IOMUX | GPIO_FLEXPWM2_PWMB03_3)
|
||||
|
||||
/* PWM
|
||||
*
|
||||
|
|
@ -355,14 +362,14 @@
|
|||
*
|
||||
*/
|
||||
#define PWM_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_NONE | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_FAST)
|
||||
#define PIN_FLEXPWM2_PWMA00 /* P2:6 PWM2 A0 FMU1 */ (PWM_IOMUX | GPIO_FLEXPWM2_PWMA00_2)
|
||||
#define PIN_FLEXPWM2_PWMA01 /* P4:8 PWM2 A1 FMU2 */ (PWM_IOMUX | GPIO_FLEXPWM2_PWMA01_1)
|
||||
#define PIN_FLEXPWM2_PWMA02 /* P4:10 PWM2 A2 FMU3 */ (PWM_IOMUX | GPIO_FLEXPWM2_PWMA02_1)
|
||||
#define PIN_FLEXPWM2_PWMA03 /* P1:9 PWM2 A3 FMU4 */ (PWM_IOMUX | GPIO_FLEXPWM2_PWMA03_2)
|
||||
#define PIN_FLEXPWM3_PWMA02 /* P3:19 PWM3 A2 FMU5 */ (PWM_IOMUX | GPIO_FLEXPWM3_PWMA02_1)
|
||||
#define PIN_FLEXPWM3_PWMB00 /* P4:30 PWM3 B0 FMU6 */ (PWM_IOMUX | GPIO_FLEXPWM3_PWMB00_1)
|
||||
#define PIN_FLEXPWM4_PWMA02 /* P4:4 PWM4 A2 FMU7 */ (PWM_IOMUX | GPIO_FLEXPWM4_PWMA02_2)
|
||||
#define PIN_FLEXPWM4_PWMB00 /* P4:1 PWM4 B0 FMU8 */ (PWM_IOMUX | GPIO_FLEXPWM4_PWMB00_1)
|
||||
#define PIN_FLEXPWM2_PWMA00 /* P2:6 GPIO_B0_06 PWM2 A0 FMU1 */ (PWM_IOMUX | GPIO_FLEXPWM2_PWMA00_2)
|
||||
#define PIN_FLEXPWM2_PWMA01 /* P4:8 GPIO_EMC_08 PWM2 A1 FMU2 */ (PWM_IOMUX | GPIO_FLEXPWM2_PWMA01_1)
|
||||
#define PIN_FLEXPWM2_PWMA02 /* P4:10 GPIO_EMC_10 PWM2 A2 FMU3 */ (PWM_IOMUX | GPIO_FLEXPWM2_PWMA02_1)
|
||||
#define PIN_FLEXPWM2_PWMA03 /* P1:9 GPIO_AD_B0_09 PWM2 A3 FMU4 */ (PWM_IOMUX | GPIO_FLEXPWM2_PWMA03_2)
|
||||
#define PIN_FLEXPWM3_PWMA02 /* P3:19 GPIO_EMC_33 PWM3 A2 FMU5 */ (PWM_IOMUX | GPIO_FLEXPWM3_PWMA02_1)
|
||||
#define PIN_FLEXPWM3_PWMB00 /* P4:30 GPIO_EMC_30 PWM3 B0 FMU6 */ (PWM_IOMUX | GPIO_FLEXPWM3_PWMB00_1)
|
||||
#define PIN_FLEXPWM4_PWMA02 /* P4:4 GPIO_EMC_04 PWM4 A2 FMU7 */ (PWM_IOMUX | GPIO_FLEXPWM4_PWMA02_2)
|
||||
#define PIN_FLEXPWM4_PWMB00 /* P4:1 GPIO_EMC_01 PWM4 B0 FMU8 */ (PWM_IOMUX | GPIO_FLEXPWM4_PWMB00_1)
|
||||
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 8
|
||||
|
||||
|
|
@ -391,27 +398,27 @@
|
|||
|
||||
#define _MK_GPIO_INPUT(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT|FMU_INPUT_IOMUX))
|
||||
|
||||
#define GPIO_GPIO0_INPUT /* P2:6 PWM2 A0 FMU1 */ (GPIO_PORT2 | GPIO_PIN6 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO1_INPUT /* P4:8 PWM2 A1 FMU2 */ (GPIO_PORT4 | GPIO_PIN8 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO2_INPUT /* P4:10 PWM2 A2 FMU3 */ (GPIO_PORT4 | GPIO_PIN10 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO3_INPUT /* P1:9 PWM2 A3 FMU4 */ (GPIO_PORT1 | GPIO_PIN9 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO4_INPUT /* P3:19 PWM3 A2 FMU5 */ (GPIO_PORT3 | GPIO_PIN19 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO5_INPUT /* P4:30 PWM3 B0 FMU6 */ (GPIO_PORT4 | GPIO_PIN30 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO6_INPUT /* P4:4 PWM4 A2 FMU7 */ (GPIO_PORT4 | GPIO_PIN4 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO7_INPUT /* P4:1 PWM4 B0 FMU8 */ (GPIO_PORT1 | GPIO_PIN1 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO0_INPUT /* P2:6 GPIO_B0_06 PWM2 A0 FMU1 */ (GPIO_PORT2 | GPIO_PIN6 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO1_INPUT /* P4:8 GPIO_EMC_08 PWM2 A1 FMU2 */ (GPIO_PORT4 | GPIO_PIN8 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO2_INPUT /* P4:10 GPIO_EMC_10 PWM2 A2 FMU3 */ (GPIO_PORT4 | GPIO_PIN10 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO3_INPUT /* P1:9 GPIO_AD_B0_09 PWM2 A3 FMU4 */ (GPIO_PORT1 | GPIO_PIN9 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO4_INPUT /* P3:19 GPIO_EMC_33 PWM3 A2 FMU5 */ (GPIO_PORT3 | GPIO_PIN19 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO5_INPUT /* P4:30 GPIO_EMC_30 PWM3 B0 FMU6 */ (GPIO_PORT4 | GPIO_PIN30 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO6_INPUT /* P4:4 GPIO_EMC_04 PWM4 A2 FMU7 */ (GPIO_PORT4 | GPIO_PIN4 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
#define GPIO_GPIO7_INPUT /* P4:1 GPIO_EMC_01 PWM4 B0 FMU8 */ (GPIO_PORT4 | GPIO_PIN1 | GPIO_INPUT | FMU_INPUT_IOMUX)
|
||||
|
||||
#define FMU_OUTPUT_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_KEEP | IOMUX_DRIVE_33OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_FAST)
|
||||
|
||||
#define _MK_GPIO_OUTPUT(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_OUTPUT|GPIO_OUTPUT_CLEAR|FMU_OUTPUT_IOMUX))
|
||||
|
||||
#define GPIO_GPIO0_OUTPUT /* P2:6 PWM2 A0 FMU1 */ (GPIO_PORT2 | GPIO_PIN6 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO1_OUTPUT /* P4:8 PWM2 A1 FMU2 */ (GPIO_PORT4 | GPIO_PIN8 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO2_OUTPUT /* P4:10 PWM2 A2 FMU3 */ (GPIO_PORT4 | GPIO_PIN10 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO3_OUTPUT /* P1:9 PWM2 A3 FMU4 */ (GPIO_PORT1 | GPIO_PIN9 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO4_OUTPUT /* P3:19 PWM3 A2 FMU5 */ (GPIO_PORT3 | GPIO_PIN19 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO5_OUTPUT /* P4:30 PWM3 B0 FMU6 */ (GPIO_PORT4 | GPIO_PIN30 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO6_OUTPUT /* P4:4 PWM4 A2 FMU7 */ (GPIO_PORT4 | GPIO_PIN4 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO7_OUTPUT /* P4:1 PWM4 B0 FMU8 */ (GPIO_PORT1 | GPIO_PIN1 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO0_OUTPUT /* P2:6 GPIO_B0_06 PWM2 A0 FMU1 */ (GPIO_PORT2 | GPIO_PIN6 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO1_OUTPUT /* P4:8 GPIO_EMC_08 PWM2 A1 FMU2 */ (GPIO_PORT4 | GPIO_PIN8 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO2_OUTPUT /* P4:10 GPIO_EMC_10 PWM2 A2 FMU3 */ (GPIO_PORT4 | GPIO_PIN10 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO3_OUTPUT /* P1:9 GPIO_AD_B0_09 PWM2 A3 FMU4 */ (GPIO_PORT1 | GPIO_PIN9 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO4_OUTPUT /* P3:19 GPIO_EMC_33 PWM3 A2 FMU5 */ (GPIO_PORT3 | GPIO_PIN19 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO5_OUTPUT /* P4:30 GPIO_EMC_30 PWM3 B0 FMU6 */ (GPIO_PORT4 | GPIO_PIN30 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO6_OUTPUT /* P4:4 GPIO_EMC_04 PWM4 A2 FMU7 */ (GPIO_PORT4 | GPIO_PIN4 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
#define GPIO_GPIO7_OUTPUT /* P4:1 GPIO_EMC_01 PWM4 B0 FMU8 */ (GPIO_PORT4 | GPIO_PIN1 | GPIO_OUTPUT | FMU_OUTPUT_IOMUX)
|
||||
|
||||
/* Power supply control and monitoring GPIOs */
|
||||
|
||||
|
|
@ -427,19 +434,25 @@
|
|||
#define BOARD_NUMBER_BRICKS 2
|
||||
#define GPIO_nVDD_USB_VALID GPIO_nPOWER_IN_C /* USB Is Chosen */
|
||||
|
||||
#define GPIO_nVDD_5V_PERIPH_EN /* GPIO_B1_03 GPIO2_IO19 */ (GPIO_PORT2 | GPIO_PIN19 | GPIO_OUTPUT | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_nVDD_5V_PERIPH_OC /* GPIO_B1_04 GPIO2_IO20 */ (GPIO_PORT2 | GPIO_PIN20 | GPIO_INPUT | GENERAL_INPUT_IOMUX)
|
||||
#define GPIO_nVDD_5V_HIPOWER_EN /* GPIO_B1_01 GPIO2_IO17 */ (GPIO_PORT2 | GPIO_PIN17 | GPIO_OUTPUT | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_nVDD_5V_HIPOWER_OC /* GPIO_B1_02 GPIO2_IO18 */ (GPIO_PORT2 | GPIO_PIN18 | GPIO_INPUT | GENERAL_INPUT_IOMUX)
|
||||
#define GPIO_VDD_3V3_SENSORS_EN /* PMIC_STBY_REQ GPIO5_IO02 */ (GPIO_PORT5 | GPIO_PIN2 | GPIO_OUTPUT | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_VDD_3V3_SD_CARD_EN /* PMIC_ON_REQ GPIO5_IO01 */ (GPIO_PORT5 | GPIO_PIN1 | GPIO_OUTPUT | GENERAL_OUTPUT_IOMUX)
|
||||
|
||||
#define GPIO_nVDD_5V_PERIPH_EN /* GPIO_B1_04 GPIO2_IO20 */ (GPIO_PORT2 | GPIO_PIN20 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_nVDD_5V_PERIPH_OC /* GPIO_B1_03 GPIO2_IO19 */ (GPIO_PORT2 | GPIO_PIN19 | GPIO_INPUT | GENERAL_INPUT_IOMUX)
|
||||
#define GPIO_nVDD_5V_HIPOWER_EN /* GPIO_B1_02 GPIO2_IO18 */ (GPIO_PORT2 | GPIO_PIN18 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_nVDD_5V_HIPOWER_OC /* GPIO_B1_01 GPIO2_IO17 */ (GPIO_PORT2 | GPIO_PIN17 | GPIO_INPUT | GENERAL_INPUT_IOMUX)
|
||||
#define GPIO_VDD_3V3_SENSORS_EN /* GPIO_EMC_41 GPIO3_IO27 */ (GPIO_PORT3 | GPIO_PIN27 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_VDD_3V3_SPEKTRUM_POWER_EN /* GPIO_AD_B0_00 GPIO1_IO00 */ (GPIO_PORT1 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_VDD_5V_RC_EN /* GPIO_AD_B0_08 GPIO1_IO08 */ (GPIO_PORT1 | GPIO_PIN8 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_VDD_5V_WIFI_EN /* PMIC_STBY_REQ GPIO5_IO02 */ (GPIO_PORT5 | GPIO_PIN2 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_VDD_3V3_SD_CARD_EN /* GPIO_EMC_13 GPIO4_IO13 */ (GPIO_PORT4 | GPIO_PIN13 | GPIO_OUTPUT | GPIO_OUTPUT_CLEAR |GENERAL_OUTPUT_IOMUX)
|
||||
|
||||
/* Define True logic Power Control in arch agnostic form */
|
||||
|
||||
#define VDD_5V_PERIPH_EN(on_true) px4_arch_gpiowrite(GPIO_nVDD_5V_PERIPH_EN, !(on_true))
|
||||
#define VDD_5V_HIPOWER_EN(on_true) px4_arch_gpiowrite(GPIO_nVDD_5V_HIPOWER_EN, !(on_true))
|
||||
#define VDD_3V3_SENSORS_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, (on_true))
|
||||
#define VDD_3V3_SPEKTRUM_POWER_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SPEKTRUM_POWER_EN, (on_true))
|
||||
#define READ_VDD_3V3_SPEKTRUM_POWER_EN() px4_arch_gpioread(GPIO_VDD_3V3_SPEKTRUM_POWER_EN)
|
||||
#define VDD_5V_RC_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_5V_RC_EN, (on_true))
|
||||
#define VDD_5V_WIFI_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_5V_WIFI_EN, (on_true))
|
||||
#define VDD_3V3_SD_CARD_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SD_CARD_EN, (on_true))
|
||||
|
||||
/* Tone alarm output */
|
||||
|
|
@ -447,10 +460,10 @@
|
|||
#define TONE_ALARM_TIMER 2 /* GPT 2 */
|
||||
#define TONE_ALARM_CHANNEL 3 /* GPIO_AD_B1_07 GPT2_COMPARE3 */
|
||||
|
||||
#define GPIO_BUZZER_1 /* GPIO_AD_B1_07 GPIO1 Pin 23 */ (GPIO_PORT1 | GPIO_PIN23 | GPIO_OUTPUT | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_BUZZER_1 /* GPIO_AD_B1_07 GPIO1_IO23 */ (GPIO_PORT1 | GPIO_PIN23 | GPIO_OUTPUT | GENERAL_OUTPUT_IOMUX)
|
||||
|
||||
#define GPIO_TONE_ALARM_IDLE GPIO_BUZZER_1
|
||||
#define GPIO_TONE_ALARM GPIO_GPT2_COMPARE3
|
||||
#define GPIO_TONE_ALARM GPIO_GPT2_COMPARE3_1
|
||||
#endif
|
||||
/* USB OTG FS
|
||||
*
|
||||
|
|
@ -461,32 +474,24 @@
|
|||
#define HRT_TIMER 1 /* use GPT1 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel 1 */
|
||||
|
||||
#define HRT_PPM_CHANNEL /* GPT1_CAPTURE2 */ 2 /* use capture/compare channel 2 */
|
||||
#define GPIO_PPM_IN /* GPT1_CAPTURE2 */ (GPIO_GPT1_CAPTURE2_1 | GENERAL_INPUT_IOMUX)
|
||||
#if defined(ON_EVK)
|
||||
#define BOARD_HAS_SINGLE_WIRE 1 /* HW is capable of Single Wire */
|
||||
#else
|
||||
#define RC_UXART_BASE IMXRT_LPUART6_BASE
|
||||
#define RC_SERIAL_PORT "/dev/ttyS4"
|
||||
#define BOARD_HAS_SINGLE_WIRE 1 /* HW is capable of Single Wire */
|
||||
#define BOARD_HAS_SINGLE_WIRE_ON_TX 1 /* HW default is wired as Single Wire On TX pin */
|
||||
#define BOARD_HAS_RX_TX_SWAP 0 /* HW Can swap TX and RX */
|
||||
#define RC_SERIAL_PORT_IS_SWAPED 0 /* Board wired with RC's TX is on cpu RX */
|
||||
#endif
|
||||
#define HRT_PPM_CHANNEL /* GPIO_B1_06 GPT1_CAPTURE2 */ 2 /* use capture/compare channel 2 */
|
||||
#define GPIO_PPM_IN /* GPIO_B1_06 GPT1_CAPTURE2 */ (GPIO_GPT1_CAPTURE2_2 | GENERAL_INPUT_IOMUX)
|
||||
|
||||
/* PWM input driver. Use FMU AUX5 pins attached to GPIO_EMC_33 GPIO3 Pin 19 FLEXPWM3_PWMA2 */
|
||||
#define RC_SERIAL_PORT "/dev/ttyS4"
|
||||
|
||||
/* PWM input driver. Use FMU AUX5 pins attached to GPIO_EMC_33 GPIO3_IO19 FLEXPWM3_PWMA2 */
|
||||
|
||||
#define PWMIN_TIMER /* FLEXPWM3_PWMA2 */ 3
|
||||
#define PWMIN_TIMER_CHANNEL /* FLEXPWM3_PWMA2 */ 2
|
||||
#define GPIO_PWM_IN /* GPIO_EMC_33 GPIO3 Pin 19 */ FLEXPWM3_PWMA2
|
||||
#define GPIO_PWM_IN /* GPIO_EMC_33 GPIO3_IO19 */ (GPIO_FLEXPWM3_PWMA02_1 | GENERAL_INPUT_IOMUX)
|
||||
|
||||
/* Shared pins Both FMU and PX4IO control/monitor
|
||||
* FMU Initializes these pins to passive input until it is known
|
||||
* if we have and PX4IO on board
|
||||
*/
|
||||
|
||||
#define GPIO_RSSI_IN /* GPIO_AD_B1_10 GPIO1 Pin 26 */ (GPIO_PORT1 | GPIO_PIN26 | GPIO_INPUT | ADC_IOMUX)
|
||||
#define GPIO_RSSI_IN_INIT /* GPIO1 Pin 26 */ 0 /* Using 0 will Leave as ADC RSSI_IN */
|
||||
#define GPIO_RSSI_IN /* GPIO_AD_B1_10 GPIO1_IO26 */ (GPIO_PORT1 | GPIO_PIN26 | GPIO_INPUT | ADC_IOMUX)
|
||||
#define GPIO_RSSI_IN_INIT /* GPIO_AD_B1_10 GPIO1_IO26 */ 0 /* Using 0 will Leave as ADC RSSI_IN */
|
||||
|
||||
/* Safety Switch is HW version dependent on having an PX4IO
|
||||
* So we init to a benign state with the _INIT definition
|
||||
|
|
@ -497,8 +502,8 @@
|
|||
#define SAFETY_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_NONE | IOMUX_DRIVE_33OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_SLOW)
|
||||
#define SAFETY_SW_IOMUX (IOMUX_CMOS_INPUT | IOMUX_PULL_UP_22K | IOMUX_DRIVE_HIZ)
|
||||
|
||||
#define GPIO_nSAFETY_SWITCH_LED_OUT_INIT /* GPIO_B0_15 GPIO2_IO15 */ (GPIO_PORT2 | GPIO_PIN15 | GPIO_INPUT | SAFETY_INIT_IOMUX)
|
||||
#define GPIO_nSAFETY_SWITCH_LED_OUT /* GPIO_B0_15 GPIO2_IO15 */ (GPIO_PORT2 | GPIO_PIN15 | GPIO_OUTPUT | SAFETY_IOMUX)
|
||||
#define GPIO_nSAFETY_SWITCH_LED_OUT_INIT /* GPIO_B0_15 GPIO2_IO15 */ (GPIO_PORT2 | GPIO_PIN15 | GPIO_INPUT | SAFETY_INIT_IOMUX)
|
||||
#define GPIO_nSAFETY_SWITCH_LED_OUT /* GPIO_B0_15 GPIO2_IO15 */ (GPIO_PORT2 | GPIO_PIN15 | GPIO_OUTPUT | SAFETY_IOMUX)
|
||||
|
||||
/* Enable the FMU to control it if there is no px4io fixme:This should be BOARD_SAFETY_LED(__ontrue) */
|
||||
#define GPIO_LED_SAFETY GPIO_nSAFETY_SWITCH_LED_OUT
|
||||
|
|
@ -513,7 +518,7 @@
|
|||
* Inversion is possible in the UART and can drive GPIO PPM_IN as an output
|
||||
*/
|
||||
|
||||
#define GPIO_PPM_IN_AS_OUT /* GPIO_EMC_23 GPIO4 Pin 23 GPT1_CAPTURE2 */ (GPIO_PORT4 | GPIO_PIN23 | GPIO_OUTPUT | GENERAL_OUTPUT_IOMUX)
|
||||
#define GPIO_PPM_IN_AS_OUT /* GPIO_B1_06 GPIO2_IO23 GPT1_CAPTURE2 GPT1_CAPTURE2 */ (GPIO_PORT2 | GPIO_PIN23 | GPIO_OUTPUT | GENERAL_OUTPUT_IOMUX)
|
||||
|
||||
#define SDIO_SLOTNO 0 /* Only one slot */
|
||||
#define SDIO_MINOR 0
|
||||
|
|
@ -579,8 +584,7 @@
|
|||
#else
|
||||
#define PX4_GPIO_INIT_LIST { \
|
||||
PX4_ADC_GPIO, \
|
||||
GPIO_HW_REV_DRIVE, \
|
||||
GPIO_HW_VER_DRIVE, \
|
||||
GPIO_HW_VER_REV_DRIVE, \
|
||||
GPIO_FLEXCAN1_TX, \
|
||||
GPIO_FLEXCAN1_RX, \
|
||||
GPIO_FLEXCAN2_TX, \
|
||||
|
|
@ -600,6 +604,9 @@
|
|||
GPIO_nVDD_5V_HIPOWER_OC, \
|
||||
GPIO_VDD_3V3_SENSORS_EN, \
|
||||
GPIO_VDD_3V3_SD_CARD_EN, \
|
||||
GPIO_VDD_3V3_SPEKTRUM_POWER_EN, \
|
||||
GPIO_VDD_5V_RC_EN, \
|
||||
GPIO_VDD_5V_WIFI_EN, \
|
||||
GPIO_TONE_ALARM_IDLE, \
|
||||
GPIO_RSSI_IN_INIT, \
|
||||
GPIO_nSAFETY_SWITCH_LED_OUT_INIT, \
|
||||
|
|
|
|||
|
|
@ -97,46 +97,6 @@ extern void led_on(int led);
|
|||
extern void led_off(int led);
|
||||
__END_DECLS
|
||||
|
||||
/************************************************************************************
|
||||
* Name: board_rc_input
|
||||
*
|
||||
* Description:
|
||||
* All boards my optionally provide this API to invert the Serial RC input.
|
||||
* This is needed on SoCs that support the notion RXINV or TXINV as apposed to
|
||||
* and external XOR controlled by a GPIO
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void board_rc_input(bool invert_on, uint32_t uxart_base)
|
||||
{
|
||||
|
||||
irqstate_t irqstate = px4_enter_critical_section();
|
||||
|
||||
uint32_t cr = getreg32(IMXRT_LPUART_CTRL_OFFSET + uxart_base);
|
||||
uint32_t sr = getreg32(IMXRT_LPUART_STAT_OFFSET + uxart_base);
|
||||
uint32_t regval = cr;
|
||||
|
||||
/* RXINV bit field can only be written when the receiver is disabled (RE=0). */
|
||||
|
||||
regval &= ~LPUART_CTRL_RE;
|
||||
|
||||
putreg32(regval, IMXRT_LPUART_CTRL_OFFSET + uxart_base);
|
||||
|
||||
if (invert_on) {
|
||||
cr |= LPUART_CTRL_TXINV;
|
||||
sr |= LPUART_STAT_RXINV;
|
||||
|
||||
} else {
|
||||
cr &= ~LPUART_CTRL_TXINV;
|
||||
sr &= ~LPUART_STAT_RXINV;
|
||||
}
|
||||
|
||||
putreg32(sr, IMXRT_LPUART_STAT_OFFSET + uxart_base);
|
||||
putreg32(cr, IMXRT_LPUART_CTRL_OFFSET + uxart_base);
|
||||
|
||||
leave_critical_section(irqstate);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: board_peripheral_reset
|
||||
*
|
||||
|
|
@ -148,7 +108,7 @@ __EXPORT void board_peripheral_reset(int ms)
|
|||
/* set the peripheral rails off */
|
||||
|
||||
VDD_5V_PERIPH_EN(false);
|
||||
VDD_3V3_SENSORS_EN(false);
|
||||
VDD_5V_HIPOWER_EN(false);
|
||||
|
||||
/* wait for the peripheral rail to reach GND */
|
||||
usleep(ms * 1000);
|
||||
|
|
@ -157,7 +117,7 @@ __EXPORT void board_peripheral_reset(int ms)
|
|||
/* re-enable power */
|
||||
|
||||
/* switch the peripheral rail back on */
|
||||
VDD_3V3_SENSORS_EN(true);
|
||||
VDD_5V_HIPOWER_EN(true);
|
||||
VDD_5V_PERIPH_EN(true);
|
||||
|
||||
}
|
||||
|
|
@ -248,10 +208,14 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
|||
|
||||
/* Power on Interfaces */
|
||||
|
||||
|
||||
VDD_3V3_SD_CARD_EN(true);
|
||||
VDD_5V_PERIPH_EN(true);
|
||||
VDD_5V_HIPOWER_EN(true);
|
||||
VDD_3V3_SENSORS_EN(true);
|
||||
VDD_3V3_SPEKTRUM_POWER_EN(true);
|
||||
|
||||
board_spi_reset(10);
|
||||
|
||||
if (OK == board_determine_hw_info()) {
|
||||
syslog(LOG_INFO, "[boot] Rev 0x%1x : Ver 0x%1x %s\n", board_get_hw_revision(), board_get_hw_version(),
|
||||
|
|
@ -291,6 +255,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
|||
|
||||
/* initial LED state */
|
||||
drv_led_start();
|
||||
|
||||
led_off(LED_RED);
|
||||
led_off(LED_GREEN);
|
||||
led_off(LED_BLUE);
|
||||
|
|
@ -299,7 +264,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
|||
int ret = fmurt1062_usdhc_initialize();
|
||||
|
||||
if (ret != OK) {
|
||||
board_autoled_on(LED_RED);
|
||||
led_on(LED_RED);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -310,8 +275,8 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
|||
ret = imxrt1062_spi_bus_initialize();
|
||||
|
||||
if (ret != OK) {
|
||||
board_autoled_on(LED_RED);
|
||||
return ret
|
||||
led_on(LED_RED);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -63,10 +63,10 @@ __END_DECLS
|
|||
|
||||
|
||||
static uint32_t g_ledmap[] = {
|
||||
0, // Indexed by LED_BLUE
|
||||
GPIO_nLED_RED, // Indexed by LED_RED, LED_AMBER
|
||||
GPIO_nLED_BLUE, // Indexed by LED_BLUE
|
||||
GPIO_nLED_RED, // Indexed by LED_RED, LED_AMBER
|
||||
GPIO_LED_SAFETY, // Indexed by LED_SAFETY
|
||||
GPIO_nLED_GREEN, // Indexed by LED_GREEN
|
||||
GPIO_nLED_GREEN, // Indexed by LED_GREEN
|
||||
};
|
||||
|
||||
__EXPORT void led_init(void)
|
||||
|
|
@ -81,10 +81,10 @@ __EXPORT void led_init(void)
|
|||
|
||||
static void phy_set_led(int led, bool state)
|
||||
{
|
||||
/* Drive High to switch on */
|
||||
/* Drive Low to switch on */
|
||||
|
||||
if (g_ledmap[led] != 0) {
|
||||
imxrt_gpio_write(g_ledmap[led], state);
|
||||
imxrt_gpio_write(g_ledmap[led], !state);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -92,7 +92,7 @@ static bool phy_get_led(int led)
|
|||
{
|
||||
|
||||
if (g_ledmap[led] != 0) {
|
||||
return imxrt_gpio_read(g_ledmap[led]);
|
||||
return imxrt_gpio_read(!g_ledmap[led]);
|
||||
}
|
||||
|
||||
return false;
|
||||
|
|
|
|||
|
|
@ -45,9 +45,10 @@
|
|||
* CD/DAT3 USDHC1_DATA3 GPIO_SD_B0_05
|
||||
* CMD USDHC1_CMD GPIO_SD_B0_00
|
||||
* CLK USDHC1_CLK GPIO_SD_B0_01
|
||||
* CD USDHC1_CD GPIO_B1_12
|
||||
* ------------ ------------- --------
|
||||
*
|
||||
* There are no Write Protect or Card detection pins available to the IMXRT.
|
||||
* There are no Write Protect available to the IMXRT.
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@ __EXPORT int imxrt1062_spi_bus_initialize(void)
|
|||
|
||||
/* Get the SPI port for the BARO */
|
||||
|
||||
spi_ext = px4_spibus_initialize(PX4_SPI_BUS_BARO);
|
||||
spi_baro = px4_spibus_initialize(PX4_SPI_BUS_BARO);
|
||||
|
||||
if (!spi_baro) {
|
||||
PX4_ERR("[boot] FAILED to initialize SPI port %d\n", PX4_SPI_BUS_BARO);
|
||||
|
|
@ -234,10 +234,8 @@ __EXPORT void imxrt_lpspi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool
|
|||
|
||||
/* Making sure the other peripherals are not selected */
|
||||
|
||||
for (size_t cs = 0; arraySize(spi1selects_gpio) > 1 && cs < arraySize(spi1selects_gpio); cs++) {
|
||||
if (spi1selects_gpio[cs] != 0) {
|
||||
imxrt_gpio_write(spi1selects_gpio[cs], 1);
|
||||
}
|
||||
for (auto cs : spi1selects_gpio) {
|
||||
imxrt_gpio_write(cs, 1);
|
||||
}
|
||||
|
||||
uint32_t gpio = spi1selects_gpio[PX4_SPI_DEV_ID(sel)];
|
||||
|
|
@ -268,10 +266,8 @@ __EXPORT void imxrt_lpspi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool
|
|||
|
||||
/* Making sure the other peripherals are not selected */
|
||||
|
||||
for (int cs = 0; arraySize(spi2selects_gpio) > 1 && cs < arraySize(spi2selects_gpio); cs++) {
|
||||
if (spi2selects_gpio[cs] != 0) {
|
||||
imxrt_gpio_write(spi2selects_gpio[cs], 1);
|
||||
}
|
||||
for (auto cs : spi2selects_gpio) {
|
||||
imxrt_gpio_write(cs, 1);
|
||||
}
|
||||
|
||||
uint32_t gpio = spi2selects_gpio[PX4_SPI_DEV_ID(sel)];
|
||||
|
|
@ -297,10 +293,8 @@ __EXPORT void imxrt_lpspi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool
|
|||
|
||||
/* Making sure the other peripherals are not selected */
|
||||
|
||||
for (int cs = 0; arraySize(spi3selects_gpio) > 1 && cs < arraySize(spi3selects_gpio); cs++) {
|
||||
if (spi3selects_gpio[cs] != 0) {
|
||||
imxrt_gpio_write(spi3selects_gpio[cs], 1);
|
||||
}
|
||||
for (auto cs : spi3selects_gpio) {
|
||||
imxrt_gpio_write(cs, 1);
|
||||
}
|
||||
|
||||
uint32_t gpio = spi3selects_gpio[PX4_SPI_DEV_ID(sel)];
|
||||
|
|
@ -321,11 +315,11 @@ __EXPORT void imxrt_lpspi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool
|
|||
{
|
||||
int sel = (int) devid;
|
||||
|
||||
ASSERT(PX4_SPI_BUS_ID(sel) == PX4_SPI_BUS_BARO);
|
||||
ASSERT(PX4_SPI_BUS_ID(sel) == PX4_SPI_BUS_EXTERNAL1);
|
||||
|
||||
/* Making sure the other peripherals are not selected */
|
||||
for (size_t cs = 0; arraySize(spi4selects_gpio) > 1 && cs < arraySize(spi4selects_gpio); cs++) {
|
||||
imxrt_gpio_write(spi4selects_gpio[cs], 1);
|
||||
for (auto cs : spi4selects_gpio) {
|
||||
imxrt_gpio_write(cs, 1);
|
||||
}
|
||||
|
||||
uint32_t gpio = spi4selects_gpio[PX4_SPI_DEV_ID(sel)];
|
||||
|
|
@ -354,24 +348,31 @@ __EXPORT void board_spi_reset(int ms)
|
|||
#ifdef CONFIG_IMXRT_LPSPI1
|
||||
|
||||
/* Goal not to back feed the chips on the bus via IO lines */
|
||||
for (size_t cs = 0; arraySize(spi1selects_gpio) > 1 && cs < arraySize(spi1selects_gpio); cs++) {
|
||||
if (spi1selects_gpio[cs] != 0) {
|
||||
imxrt_config_gpio(_PIN_OFF(spi1selects_gpio[cs]));
|
||||
}
|
||||
for (auto cs : spi1selects_gpio) {
|
||||
imxrt_config_gpio(_PIN_OFF(cs));
|
||||
}
|
||||
|
||||
imxrt_config_gpio(GPIO_SPI1_SCK_OFF);
|
||||
imxrt_config_gpio(GPIO_SPI1_MISO_OFF);
|
||||
imxrt_config_gpio(GPIO_SPI1_MOSI_OFF);
|
||||
|
||||
for (auto cs : spi3selects_gpio) {
|
||||
imxrt_config_gpio(_PIN_OFF(cs));
|
||||
}
|
||||
|
||||
imxrt_config_gpio(GPIO_SPI3_SCK_OFF);
|
||||
imxrt_config_gpio(GPIO_SPI3_MISO_OFF);
|
||||
imxrt_config_gpio(GPIO_SPI3_MOSI_OFF);
|
||||
|
||||
|
||||
imxrt_config_gpio(_PIN_OFF(GPIO_LPI2C3_SDA_GPIO));
|
||||
imxrt_config_gpio(_PIN_OFF(GPIO_LPI2C3_SCL_GPIO));
|
||||
|
||||
# if BOARD_USE_DRDY
|
||||
imxrt_config_gpio(GPIO_DRDY_OFF_SPI1_DRDY1_ICM20689);
|
||||
imxrt_config_gpio(GPIO_DRDY_OFF_SPI1_DRDY2_BMI055_GYRO);
|
||||
imxrt_config_gpio(GPIO_DRDY_OFF_SPI1_DRDY3_BMI055_ACC);
|
||||
imxrt_config_gpio(GPIO_DRDY_OFF_SPI1_DRDY4_ICM20602);
|
||||
imxrt_config_gpio(GPIO_DRDY_OFF_SPI1_DRDY5_BMI055_GYRO);
|
||||
imxrt_config_gpio(GPIO_DRDY_OFF_SPI1_DRDY6_BMI055_ACC);
|
||||
# endif
|
||||
/* set the sensor rail off */
|
||||
imxrt_gpio_write(GPIO_VDD_3V3_SENSORS_EN, 0);
|
||||
|
|
@ -389,23 +390,31 @@ __EXPORT void board_spi_reset(int ms)
|
|||
usleep(100);
|
||||
|
||||
/* reconfigure the SPI pins */
|
||||
for (size_t cs = 0; arraySize(spi1selects_gpio) > 1 && cs < arraySize(spi1selects_gpio); cs++) {
|
||||
if (spi1selects_gpio[cs] != 0) {
|
||||
imxrt_config_gpio(spi1selects_gpio[cs]);
|
||||
}
|
||||
for (auto cs : spi1selects_gpio) {
|
||||
imxrt_config_gpio(cs);
|
||||
}
|
||||
|
||||
imxrt_config_gpio(GPIO_LPSPI1_SCK);
|
||||
imxrt_config_gpio(GPIO_LPSPI1_MISO);
|
||||
imxrt_config_gpio(GPIO_LPSPI1_MOSI);
|
||||
|
||||
/* reconfigure the SPI pins */
|
||||
for (auto cs : spi3selects_gpio) {
|
||||
imxrt_config_gpio(cs);
|
||||
}
|
||||
|
||||
imxrt_config_gpio(GPIO_LPSPI3_SCK);
|
||||
imxrt_config_gpio(GPIO_LPSPI3_MISO);
|
||||
imxrt_config_gpio(GPIO_LPSPI3_MOSI);
|
||||
|
||||
imxrt_config_gpio(GPIO_LPI2C3_SDA);
|
||||
imxrt_config_gpio(GPIO_LPI2C3_SCL);
|
||||
|
||||
# if BOARD_USE_DRDY
|
||||
imxrt_config_gpio(GPIO_SPI1_DRDY1_ICM20689);
|
||||
imxrt_config_gpio(GPIO_SPI1_DRDY2_BMI055_GYRO);
|
||||
imxrt_config_gpio(GPIO_SPI1_DRDY3_BMI055_ACC);
|
||||
imxrt_config_gpio(GPIO_SPI1_DRDY4_ICM20602);
|
||||
imxrt_config_gpio(GPIO_SPI1_DRDY5_BMI055_GYRO);
|
||||
imxrt_config_gpio(GPIO_SPI1_DRDY6_BMI055_ACC);
|
||||
# endif
|
||||
#endif /* CONFIG_IMXRT_LPSPI1 */
|
||||
|
||||
Loading…
Reference in New Issue