forked from Archive/PX4-Autopilot
The STM32 F2/4 OTG FS device driver seems to be functional
git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5587 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
4a3b0823cb
commit
b433eca18d
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@ -509,7 +509,7 @@ static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv);
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static void stm32_txfifo_write(FAR struct stm32_ep_s *privep,
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FAR uint8_t *buf, int nbytes);
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static void stm32_epin_transfer(FAR struct stm32_ep_s *privep,
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FAR uint8_t *buf, int nbytes);
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FAR uint8_t *buf, int nbytes);
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static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
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FAR struct stm32_ep_s *privep);
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@ -556,7 +556,9 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv);
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static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv);
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static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno);
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#ifndef ENABLE_DTXFSTS_POLLHACK
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static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int epno);
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#endif
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static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv);
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/* Other second level interrupt processing */
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@ -963,7 +965,7 @@ static void stm32_txfifo_write(FAR struct stm32_ep_s *privep,
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regval |= ((uint32_t)*buf++) << 16;
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regval |= ((uint32_t)*buf++) << 24;
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/* Then write the packed data to the TxFIFO */
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/* Then write the packet data to the TxFIFO */
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stm32_putreg(regval, regaddr);
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}
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@ -1153,13 +1155,20 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
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privep->zlp = true;
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}
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/* Loop while there are still bytes to be transferred (or a zero-length-
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* packet, ZLP, to be sent). The loop will also be terminated if there
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* is insufficient space remaining in the TxFIFO to send a complete
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* packet.
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/* Add one more packet to the TxFIFO. We will wait for the transfer
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* complete event before we add the next packet (or part of a packet
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* to the TxFIFO).
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*
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* The documentation says that we can can multiple packets to the TxFIFO,
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* but it seems that we need to get the transfer complete event before
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* we can add the next (or maybe I have got something wrong?)
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*/
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#if 0
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while (privreq->req.xfrd < privreq->req.len || privep->zlp)
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#else
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if (privreq->req.xfrd < privreq->req.len || privep->zlp)
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#endif
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{
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/* Get the number of bytes left to be sent in the request */
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@ -1240,8 +1249,11 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
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* anyway.
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*/
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DEBUGASSERT(avail < nwords);
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if (avail < nwords)
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{
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/* We will probably not recover from what we are about to do */
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usbtrace(TRACE_DEVERROR(STM32_TRACEERR_POLLTIMEOUT), avail);
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return;
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}
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@ -1265,9 +1277,11 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
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empmsk |= OTGFS_DIEPEMPMSK(privep->epphy);
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stm32_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK);
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/* Terminate the transfer loop */
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/* Terminate the transfer loop. We will try again when the
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* TxFIFO empty interrupt is received.
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*/
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break;
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return;
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}
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#endif
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@ -2698,17 +2712,19 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno)
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*
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****************************************************************************/
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#ifndef ENABLE_DTXFSTS_POLLHACK
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static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int epno)
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{
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FAR struct stm32_ep_s *privep = &priv->epin[epno];
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/* Continue processing the write request queue. This may mean sending
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* more dat from the exisiting request or terminating the current requests
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* more data from the exisiting request or terminating the current requests
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* and (perhaps) starting the IN transfer from the next write request.
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*/
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stm32_epin_request(priv, privep);
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}
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#endif
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/*******************************************************************************
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* Name: stm32_epin_interrupt
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@ -2754,16 +2770,20 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
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mask = stm32_getreg(STM32_OTGFS_DIEPMSK);
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/* Check for FIFO not empty. Bits n corresponds to endpoint n.
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* That condition corresponds to bit 7 of the DIEPINT interrupt
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* status register.
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/* Check if the TxFIFO not empty interrupt is enabled for this
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* endpoint in the DIEPMSK register. Bits n corresponds to
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* endpoint n in the register. That condition corresponds to
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* bit 7 of the DIEPINT interrupt status register. There is
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* no TXFE bit in the mask register, so we fake one here.
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*/
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#ifndef ENABLE_DTXFSTS_POLLHACK
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empty = stm32_getreg(STM32_OTGFS_DIEPEMPMSK);
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if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0)
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{
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mask |= OTGFS_DIEPINT_TXFE;
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}
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#endif
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/* Now, read the interrupt status and mask out all disabled
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* interrupts.
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@ -2776,15 +2796,19 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
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if ((diepint & OTGFS_DIEPINT_XFRC) != 0)
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{
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usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), (uint16_t)diepint);
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usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC),
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(uint16_t)diepint);
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/* It is possible that logic may be waiting for a the TxFIFO to become
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* empty. We disable the TxFIFO empty interrupt here; it will be
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* re-enabled if there is still insufficient space in the TxFIFO.
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#ifndef ENABLE_DTXFSTS_POLLHACK
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/* It is possible that logic may be waiting for a the
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* TxFIFO to become empty. We disable the TxFIFO empty
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* interrupt here; it will be re-enabled if there is still
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* insufficient space in the TxFIFO.
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*/
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empty &= ~OTGFS_DIEPEMPMSK(epno);
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stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK);
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#endif
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stm32_putreg(OTGFS_DIEPINT_XFRC, STM32_OTGFS_DIEPINT(epno));
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/* IN transfer complete */
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@ -2836,12 +2860,13 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
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#endif
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/* Transmit FIFO empty */
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#ifndef ENABLE_DTXFSTS_POLLHACK
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if ((diepint & OTGFS_DIEPINT_TXFE) != 0)
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{
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usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint);
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/* If we were waiting for TxFIFO to become empty, the we might have both
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* XFRC and TXFE interrups pending. Since we do the same thing for both
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* XFRC and TXFE interrupts pending. Since we do the same thing for both
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* cases, ignore the TXFE if we have already processed the XFRC.
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*/
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@ -2863,6 +2888,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
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stm32_putreg(OTGFS_DIEPINT_TXFE, STM32_OTGFS_DIEPINT(epno));
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}
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#endif
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}
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epno++;
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@ -4970,8 +4996,9 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
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/* At startup the core is in FS mode. */
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/* Disable the USB global interrupt by clearing GINTMSK in the global OTG
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* FS AHB configuration register.
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/* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG
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* register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO
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* interrupts will occur when the TxFIFO is truly empty (not just half full).
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*/
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stm32_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG);
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@ -5087,6 +5114,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
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stm32_putreg(0, STM32_OTGFS_DIEPMSK);
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stm32_putreg(0, STM32_OTGFS_DOEPMSK);
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stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK);
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stm32_putreg(0xffffffff, STM32_OTGFS_DAINT);
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stm32_putreg(0, STM32_OTGFS_DAINTMSK);
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@ -5168,10 +5196,13 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
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stm32_putreg(regval, STM32_OTGFS_GINTMSK);
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/* Enable the USB global interrupt by setting GINTMSK in the global OTG
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* FS AHB configuration register.
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* FS AHB configuration register; Set the TXFELVL bit in the GAHBCFG
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* register so that TxFIFO interrupts will occur when the TxFIFO is truly
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* empty (not just half full).
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*/
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stm32_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG);
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stm32_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL,
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STM32_OTGFS_GAHBCFG);
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}
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/*******************************************************************************
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@ -5327,6 +5358,7 @@ void up_usbuninitialize(void)
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stm32_putreg(0, STM32_OTGFS_DIEPMSK);
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stm32_putreg(0, STM32_OTGFS_DOEPMSK);
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stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK);
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stm32_putreg(0, STM32_OTGFS_DAINTMSK);
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stm32_putreg(0xffffffff, STM32_OTGFS_DAINT);
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