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@ -42,11 +42,6 @@ static constexpr int16_t combine(uint8_t msb, uint8_t lsb)
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return (msb << 8u) | lsb;
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}
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static bool fifo_accel_equal(const FIFO::DATA &f0, const FIFO::DATA &f1)
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{
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return (memcmp(&f0.ACCEL_XOUT_H, &f1.ACCEL_XOUT_H, 6) == 0);
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}
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ICM20602::ICM20602(int bus, uint32_t device, enum Rotation rotation) :
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SPI(MODULE_NAME, nullptr, bus, device, SPIDEV_MODE3, SPI_SPEED),
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ScheduledWorkItem(MODULE_NAME, px4::device_bus_to_wq(get_device_id())),
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@ -54,8 +49,11 @@ ICM20602::ICM20602(int bus, uint32_t device, enum Rotation rotation) :
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_px4_gyro(get_device_id(), ORB_PRIO_VERY_HIGH, rotation)
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{
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set_device_type(DRV_ACC_DEVTYPE_ICM20602);
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_px4_accel.set_device_type(DRV_ACC_DEVTYPE_ICM20602);
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_px4_gyro.set_device_type(DRV_GYR_DEVTYPE_ICM20602);
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ConfigureSampleRate(_px4_gyro.get_max_rate_hz());
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}
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ICM20602::~ICM20602()
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@ -75,50 +73,6 @@ ICM20602::~ICM20602()
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perf_free(_drdy_interval_perf);
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}
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void ICM20602::ConfigureSampleRate(int sample_rate)
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{
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if (sample_rate == 0) {
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sample_rate = 1000; // default to 1 kHz
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}
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sample_rate = math::constrain(sample_rate, 250, 2000); // limit 250 - 2000 Hz
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_fifo_empty_interval_us = math::max(((1000000 / sample_rate) / 250) * 250, 500); // round down to nearest 250 us
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_fifo_gyro_samples = math::min(_fifo_empty_interval_us / (1000000 / GYRO_RATE), FIFO_MAX_SAMPLES);
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// recompute FIFO empty interval (us) with actual gyro sample limit
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_fifo_empty_interval_us = _fifo_gyro_samples * (1000000 / GYRO_RATE);
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_fifo_accel_samples = math::min(_fifo_empty_interval_us / (1000000 / ACCEL_RATE), FIFO_MAX_SAMPLES);
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_px4_accel.set_update_rate(1000000 / _fifo_empty_interval_us);
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_px4_gyro.set_update_rate(1000000 / _fifo_empty_interval_us);
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// FIFO watermark threshold in number of bytes
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const uint16_t fifo_watermark_threshold = _fifo_gyro_samples * sizeof(FIFO::DATA);
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for (auto &r : _register_cfg) {
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if (r.reg == Register::FIFO_WM_TH1) {
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r.set_bits = (fifo_watermark_threshold >> 8) & 0b00000011;
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} else if (r.reg == Register::FIFO_WM_TH2) {
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r.set_bits = fifo_watermark_threshold & 0xFF;
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}
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}
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}
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int ICM20602::probe()
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{
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const uint8_t whoami = RegisterRead(Register::WHO_AM_I);
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if (whoami != WHOAMI) {
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PX4_WARN("unexpected WHO_AM_I 0x%02x", whoami);
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return PX4_ERROR;
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}
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return PX4_OK;
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}
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bool ICM20602::Init()
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{
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if (SPI::init() != PX4_OK) {
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@ -134,32 +88,193 @@ bool ICM20602::Init()
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return false;
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}
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if (!Reset()) {
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PX4_ERR("reset failed");
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return false;
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return Reset();
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}
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void ICM20602::Stop()
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{
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// wait until stopped
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while (_state.load() != STATE::STOPPED) {
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_state.store(STATE::REQUEST_STOP);
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ScheduleNow();
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px4_usleep(10);
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}
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Start();
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return true;
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}
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bool ICM20602::Reset()
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{
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// PWR_MGMT_1: Device Reset
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RegisterWrite(Register::PWR_MGMT_1, PWR_MGMT_1_BIT::DEVICE_RESET);
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_state.store(STATE::RESET);
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ScheduleClear();
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ScheduleNow();
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return true;
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}
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void ICM20602::PrintInfo()
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{
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PX4_INFO("FIFO empty interval: %d us (%.3f Hz)", _fifo_empty_interval_us,
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static_cast<double>(1000000 / _fifo_empty_interval_us));
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perf_print_counter(_transfer_perf);
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perf_print_counter(_bad_register_perf);
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perf_print_counter(_bad_transfer_perf);
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perf_print_counter(_fifo_empty_perf);
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perf_print_counter(_fifo_overflow_perf);
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perf_print_counter(_fifo_reset_perf);
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perf_print_counter(_drdy_interval_perf);
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_px4_accel.print_status();
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_px4_gyro.print_status();
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}
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int ICM20602::probe()
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{
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const uint8_t whoami = RegisterRead(Register::WHO_AM_I);
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if (whoami != WHOAMI) {
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PX4_WARN("unexpected WHO_AM_I 0x%02x", whoami);
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return PX4_ERROR;
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}
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return PX4_OK;
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}
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void ICM20602::Run()
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{
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switch (_state.load()) {
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case STATE::RESET:
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// PWR_MGMT_1: Device Reset
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RegisterWrite(Register::PWR_MGMT_1, PWR_MGMT_1_BIT::DEVICE_RESET);
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_reset_timestamp = hrt_absolute_time();
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_state.store(STATE::WAIT_FOR_RESET);
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ScheduleDelayed(100);
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break;
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case STATE::WAIT_FOR_RESET:
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for (int i = 0; i < 100; i++) {
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// The reset value is 0x00 for all registers other than the registers below
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// Document Number: DS-000176 Page 31 of 57
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if ((RegisterRead(Register::WHO_AM_I) == WHOAMI)
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&& (RegisterRead(Register::PWR_MGMT_1) == 0x41)
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&& (RegisterRead(Register::CONFIG) == 0x80)) {
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return true;
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}
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}
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return false;
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// if reset succeeded then configure
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_state.store(STATE::CONFIGURE);
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ScheduleNow();
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} else {
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// RESET not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 10_ms) {
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PX4_ERR("Reset failed, retrying");
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_state.store(STATE::RESET);
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ScheduleDelayed(10_ms);
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} else {
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PX4_DEBUG("Reset not complete, check again in 1 ms");
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ScheduleDelayed(1_ms);
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}
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}
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break;
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case STATE::CONFIGURE:
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if (Configure()) {
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// if configure succeeded then start reading from FIFO
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_state.store(STATE::FIFO_READ);
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if (DataReadyInterruptConfigure()) {
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_data_ready_interrupt_enabled = true;
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// backup schedule as a watchdog timeout
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ScheduleDelayed(10_ms);
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} else {
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_data_ready_interrupt_enabled = false;
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ScheduleOnInterval(_fifo_empty_interval_us, _fifo_empty_interval_us);
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}
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FIFOReset();
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} else {
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PX4_DEBUG("Configure failed, retrying");
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// try again in 1 ms
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ScheduleDelayed(1_ms);
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}
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break;
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case STATE::FIFO_READ: {
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hrt_abstime timestamp_sample = 0;
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uint8_t samples = 0;
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if (_data_ready_interrupt_enabled) {
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// re-schedule as watchdog timeout
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ScheduleDelayed(10_ms);
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// timestamp set in data ready interrupt
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samples = _fifo_read_samples.load();
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timestamp_sample = _fifo_watermark_interrupt_timestamp;
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}
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bool failure = false;
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// manually check FIFO count if no samples from DRDY or timestamp looks bogus
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if (!_data_ready_interrupt_enabled || (samples == 0)
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|| (hrt_elapsed_time(×tamp_sample) > (_fifo_empty_interval_us / 2))) {
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// use the time now roughly corresponding with the last sample we'll pull from the FIFO
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timestamp_sample = hrt_absolute_time();
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const uint16_t fifo_count = FIFOReadCount();
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if (fifo_count == 0) {
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failure = true;
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perf_count(_fifo_empty_perf);
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}
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samples = (fifo_count / sizeof(FIFO::DATA) / 2) * 2; // round down to nearest 2
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}
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if (samples > FIFO_MAX_SAMPLES) {
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// not technically an overflow, but more samples than we expected or can publish
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perf_count(_fifo_overflow_perf);
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failure = true;
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FIFOReset();
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} else if (samples >= 2) {
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// require at least 2 samples (we want at least 1 new accel sample per transfer)
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if (!FIFORead(timestamp_sample, samples)) {
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failure = true;
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_px4_accel.increase_error_count();
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_px4_gyro.increase_error_count();
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}
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}
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if (failure || hrt_elapsed_time(&_last_config_check_timestamp) > 10_ms) {
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// check registers incrementally
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if (RegisterCheck(_register_cfg[_checked_register], true)) {
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_last_config_check_timestamp = timestamp_sample;
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_checked_register = (_checked_register + 1) % size_register_cfg;
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} else {
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// register check failed, force reconfigure
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PX4_DEBUG("Health check failed, reconfiguring");
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_state.store(STATE::CONFIGURE);
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ScheduleNow();
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}
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}
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}
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break;
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case STATE::REQUEST_STOP:
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DataReadyInterruptDisable();
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ScheduleClear();
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_state.store(STATE::STOPPED);
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break;
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case STATE::STOPPED:
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// DO NOTHING
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break;
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}
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}
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void ICM20602::ConfigureAccel()
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@ -216,54 +331,126 @@ void ICM20602::ConfigureGyro()
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}
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}
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void ICM20602::ResetFIFO()
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void ICM20602::ConfigureSampleRate(int sample_rate)
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{
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perf_count(_fifo_reset_perf);
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if (sample_rate == 0) {
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sample_rate = 1000; // default to 1 kHz
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}
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// USER_CTRL: disable FIFO and reset all signal paths
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RegisterSetAndClearBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_RST | USER_CTRL_BIT::SIG_COND_RST,
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USER_CTRL_BIT::FIFO_EN);
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_fifo_empty_interval_us = math::max(((1000000 / sample_rate) / 250) * 250, 250); // round down to nearest 250 us
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_fifo_gyro_samples = math::min(_fifo_empty_interval_us / (1000000 / GYRO_RATE), FIFO_MAX_SAMPLES);
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// FIFO_EN: enable both gyro and accel
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RegisterSetBits(Register::FIFO_EN, FIFO_EN_BIT::GYRO_FIFO_EN | FIFO_EN_BIT::ACCEL_FIFO_EN);
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// recompute FIFO empty interval (us) with actual gyro sample limit
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_fifo_empty_interval_us = _fifo_gyro_samples * (1000000 / GYRO_RATE);
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// USER_CTRL: re-enable FIFO
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RegisterSetAndClearBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN,
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USER_CTRL_BIT::FIFO_RST | USER_CTRL_BIT::SIG_COND_RST);
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_fifo_accel_samples = math::min(_fifo_empty_interval_us / (1000000 / ACCEL_RATE), FIFO_MAX_SAMPLES);
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_px4_accel.set_update_rate(1000000 / _fifo_empty_interval_us);
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_px4_gyro.set_update_rate(1000000 / _fifo_empty_interval_us);
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// FIFO watermark threshold in number of bytes
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const uint16_t fifo_watermark_threshold = _fifo_gyro_samples * sizeof(FIFO::DATA);
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for (auto &r : _register_cfg) {
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if (r.reg == Register::FIFO_WM_TH1) {
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r.set_bits = (fifo_watermark_threshold >> 8) & 0b00000011;
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|
|
|
|
|
} else if (r.reg == Register::FIFO_WM_TH2) {
|
|
|
|
|
r.set_bits = fifo_watermark_threshold & 0xFF;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20602::Configure(bool notify)
|
|
|
|
|
bool ICM20602::Configure()
|
|
|
|
|
{
|
|
|
|
|
bool success = true;
|
|
|
|
|
|
|
|
|
|
for (const auto ® : _register_cfg) {
|
|
|
|
|
if (!CheckRegister(reg, notify)) {
|
|
|
|
|
if (!RegisterCheck(reg)) {
|
|
|
|
|
success = false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ConfigureAccel();
|
|
|
|
|
ConfigureGyro();
|
|
|
|
|
|
|
|
|
|
return success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20602::CheckRegister(const register_config_t ®_cfg, bool notify)
|
|
|
|
|
int ICM20602::DataReadyInterruptCallback(int irq, void *context, void *arg)
|
|
|
|
|
{
|
|
|
|
|
static_cast<ICM20602 *>(arg)->DataReady();
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20602::DataReady()
|
|
|
|
|
{
|
|
|
|
|
_fifo_watermark_interrupt_timestamp = hrt_absolute_time();
|
|
|
|
|
_fifo_read_samples.store(_fifo_gyro_samples);
|
|
|
|
|
ScheduleNow();
|
|
|
|
|
perf_count(_drdy_interval_perf);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20602::DataReadyInterruptConfigure()
|
|
|
|
|
{
|
|
|
|
|
int ret_setevent = -1;
|
|
|
|
|
|
|
|
|
|
// Setup data ready on rising edge
|
|
|
|
|
// TODO: cleanup horrible DRDY define mess
|
|
|
|
|
#if defined(GPIO_DRDY_PORTC_PIN14)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_DRDY_PORTC_PIN14, true, false, true, &ICM20602::DataReadyInterruptCallback,
|
|
|
|
|
this);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY1_ICM20602)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_SPI1_DRDY1_ICM20602, true, false, true, &ICM20602::DataReadyInterruptCallback,
|
|
|
|
|
this);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY4_ICM20602)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_SPI1_DRDY4_ICM20602, true, false, true, &ICM20602::DataReadyInterruptCallback,
|
|
|
|
|
this);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY1_ICM20602)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_SPI1_DRDY1_ICM20602, true, false, true, &ICM20602::DataReadyInterruptCallback,
|
|
|
|
|
this);
|
|
|
|
|
#elif defined(GPIO_DRDY_ICM_2060X)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_DRDY_ICM_2060X, true, false, true, &ICM20602::DataReadyInterruptCallback,
|
|
|
|
|
this);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
return (ret_setevent == 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20602::DataReadyInterruptDisable()
|
|
|
|
|
{
|
|
|
|
|
int ret_setevent = -1;
|
|
|
|
|
|
|
|
|
|
// Disable data ready callback
|
|
|
|
|
// TODO: cleanup horrible DRDY define mess
|
|
|
|
|
#if defined(GPIO_DRDY_PORTC_PIN14)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_DRDY_PORTC_PIN14, false, false, false, nullptr, nullptr);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY1_ICM20602)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_SPI1_DRDY1_ICM20602, false, false, false, nullptr, nullptr);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY4_ICM20602)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_SPI1_DRDY4_ICM20602, false, false, false, nullptr, nullptr);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY1_ICM20602)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_SPI1_DRDY1_ICM20602, false, false, false, nullptr, nullptr);
|
|
|
|
|
#elif defined(GPIO_DRDY_ICM_2060X)
|
|
|
|
|
ret_setevent = px4_arch_gpiosetevent(GPIO_DRDY_ICM_2060X, false, false, false, nullptr, nullptr);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
return (ret_setevent == 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20602::RegisterCheck(const register_config_t ®_cfg, bool notify)
|
|
|
|
|
{
|
|
|
|
|
bool success = true;
|
|
|
|
|
|
|
|
|
|
const uint8_t reg_value = RegisterRead(reg_cfg.reg);
|
|
|
|
|
|
|
|
|
|
if (reg_cfg.set_bits && !(reg_value & reg_cfg.set_bits)) {
|
|
|
|
|
if (notify) {
|
|
|
|
|
PX4_ERR("0x%02hhX: 0x%02hhX (0x%02hhX not set)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.set_bits);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not set)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.set_bits);
|
|
|
|
|
success = false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (reg_cfg.clear_bits && (reg_value & reg_cfg.clear_bits)) {
|
|
|
|
|
if (notify) {
|
|
|
|
|
PX4_ERR("0x%02hhX: 0x%02hhX (0x%02hhX not cleared)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.clear_bits);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not cleared)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.clear_bits);
|
|
|
|
|
success = false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@ -279,6 +466,8 @@ bool ICM20602::CheckRegister(const register_config_t ®_cfg, bool notify)
|
|
|
|
|
|
|
|
|
|
if (notify) {
|
|
|
|
|
perf_count(_bad_register_perf);
|
|
|
|
|
_px4_accel.increase_error_count();
|
|
|
|
|
_px4_gyro.increase_error_count();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@ -325,148 +514,22 @@ void ICM20602::RegisterClearBits(Register reg, uint8_t clearbits)
|
|
|
|
|
RegisterSetAndClearBits(reg, 0, clearbits);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int ICM20602::DataReadyInterruptCallback(int irq, void *context, void *arg)
|
|
|
|
|
uint16_t ICM20602::FIFOReadCount()
|
|
|
|
|
{
|
|
|
|
|
ICM20602 *dev = reinterpret_cast<ICM20602 *>(arg);
|
|
|
|
|
dev->DataReady();
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20602::DataReady()
|
|
|
|
|
{
|
|
|
|
|
perf_count(_drdy_interval_perf);
|
|
|
|
|
|
|
|
|
|
// make another measurement
|
|
|
|
|
ScheduleNow();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20602::Start()
|
|
|
|
|
{
|
|
|
|
|
ConfigureSampleRate(_px4_gyro.get_max_rate_hz());
|
|
|
|
|
|
|
|
|
|
// attempt to configure 3 times
|
|
|
|
|
for (int i = 0; i < 3; i++) {
|
|
|
|
|
if (Configure(false)) {
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// TODO: cleanup horrible DRDY define mess
|
|
|
|
|
#if defined(GPIO_DRDY_PORTC_PIN14)
|
|
|
|
|
_using_data_ready_interrupt_enabled = true;
|
|
|
|
|
// Setup data ready on rising edge
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_DRDY_PORTC_PIN14, true, false, true, &ICM20602::DataReadyInterruptCallback, this);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY1_ICM20602)
|
|
|
|
|
_using_data_ready_interrupt_enabled = true;
|
|
|
|
|
// Setup data ready on rising edge
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_SPI1_DRDY1_ICM20602, true, false, true, &ICM20602::DataReadyInterruptCallback, this);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY4_ICM20602)
|
|
|
|
|
_using_data_ready_interrupt_enabled = true;
|
|
|
|
|
// Setup data ready on rising edge
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_SPI1_DRDY4_ICM20602, true, false, true, &ICM20602::DataReadyInterruptCallback, this);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY1_ICM20602)
|
|
|
|
|
_using_data_ready_interrupt_enabled = true;
|
|
|
|
|
// Setup data ready on rising edge
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_SPI1_DRDY1_ICM20602, true, false, true, &ICM20602::DataReadyInterruptCallback, this);
|
|
|
|
|
#elif defined(GPIO_DRDY_ICM_2060X)
|
|
|
|
|
_using_data_ready_interrupt_enabled = true;
|
|
|
|
|
// Setup data ready on rising edge
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_DRDY_ICM_2060X, true, false, true, &ICM20602::DataReadyInterruptCallback, this);
|
|
|
|
|
#else
|
|
|
|
|
_using_data_ready_interrupt_enabled = false;
|
|
|
|
|
ScheduleOnInterval(FIFO_EMPTY_INTERVAL_US, FIFO_EMPTY_INTERVAL_US);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
ResetFIFO();
|
|
|
|
|
|
|
|
|
|
// schedule as watchdog
|
|
|
|
|
if (_using_data_ready_interrupt_enabled) {
|
|
|
|
|
ScheduleDelayed(100_ms);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20602::Stop()
|
|
|
|
|
{
|
|
|
|
|
Reset();
|
|
|
|
|
|
|
|
|
|
// TODO: cleanup horrible DRDY define mess
|
|
|
|
|
#if defined(GPIO_DRDY_PORTC_PIN14)
|
|
|
|
|
// Disable data ready callback
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_DRDY_PORTC_PIN14, false, false, false, nullptr, nullptr);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY1_ICM20602)
|
|
|
|
|
// Disable data ready callback
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_SPI1_DRDY1_ICM20602, false, false, false, nullptr, nullptr);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY4_ICM20602)
|
|
|
|
|
// Disable data ready callback
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_SPI1_DRDY4_ICM20602, false, false, false, nullptr, nullptr);
|
|
|
|
|
#elif defined(GPIO_SPI1_DRDY1_ICM20602)
|
|
|
|
|
// Disable data ready callback
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_SPI1_DRDY1_ICM20602, false, false, false, nullptr, nullptr);
|
|
|
|
|
#elif defined(GPIO_DRDY_ICM_2060X)
|
|
|
|
|
// Disable data ready callback
|
|
|
|
|
px4_arch_gpiosetevent(GPIO_DRDY_ICM_2060X, false, false, false, nullptr, nullptr);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
ScheduleClear();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20602::Run()
|
|
|
|
|
{
|
|
|
|
|
// use the time now roughly corresponding with the last sample we'll pull from the FIFO
|
|
|
|
|
const hrt_abstime timestamp_sample = hrt_absolute_time();
|
|
|
|
|
|
|
|
|
|
// read FIFO count
|
|
|
|
|
uint8_t fifo_count_buf[3] {};
|
|
|
|
|
fifo_count_buf[0] = static_cast<uint8_t>(Register::FIFO_COUNTH) | DIR_READ;
|
|
|
|
|
|
|
|
|
|
if (transfer(fifo_count_buf, fifo_count_buf, sizeof(fifo_count_buf)) != PX4_OK) {
|
|
|
|
|
perf_count(_bad_transfer_perf);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (_using_data_ready_interrupt_enabled) {
|
|
|
|
|
// re-schedule as watchdog
|
|
|
|
|
ScheduleDelayed(100_ms);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// check registers
|
|
|
|
|
if (hrt_elapsed_time(&_last_config_check) > 100_ms) {
|
|
|
|
|
_checked_register = (_checked_register + 1) % size_register_cfg;
|
|
|
|
|
|
|
|
|
|
if (CheckRegister(_register_cfg[_checked_register])) {
|
|
|
|
|
// delay next register check if current succeeded
|
|
|
|
|
_last_config_check = hrt_absolute_time();
|
|
|
|
|
|
|
|
|
|
} else {
|
|
|
|
|
// if register check failed reconfigure all
|
|
|
|
|
Configure();
|
|
|
|
|
ResetFIFO();
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const uint16_t fifo_count = combine(fifo_count_buf[1], fifo_count_buf[2]);
|
|
|
|
|
const uint8_t samples = (fifo_count / sizeof(FIFO::DATA) / 2) * 2; // round down to nearest 2
|
|
|
|
|
|
|
|
|
|
if (samples < 2) {
|
|
|
|
|
perf_count(_fifo_empty_perf);
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
} else if (samples > FIFO_MAX_SAMPLES) {
|
|
|
|
|
// not technically an overflow, but more samples than we expected or can publish
|
|
|
|
|
perf_count(_fifo_overflow_perf);
|
|
|
|
|
ResetFIFO();
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Transfer data
|
|
|
|
|
struct TransferBuffer {
|
|
|
|
|
uint8_t cmd;
|
|
|
|
|
FIFO::DATA f[FIFO_MAX_SAMPLES];
|
|
|
|
|
};
|
|
|
|
|
// ensure no struct padding
|
|
|
|
|
static_assert(sizeof(TransferBuffer) == (sizeof(uint8_t) + FIFO_MAX_SAMPLES * sizeof(FIFO::DATA)));
|
|
|
|
|
return combine(fifo_count_buf[1], fifo_count_buf[2]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20602::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples)
|
|
|
|
|
{
|
|
|
|
|
TransferBuffer *report = (TransferBuffer *)_dma_data_buffer;
|
|
|
|
|
const size_t transfer_size = math::min(samples * sizeof(FIFO::DATA) + 1, FIFO::SIZE);
|
|
|
|
|
memset(report, 0, transfer_size);
|
|
|
|
@ -477,18 +540,70 @@ void ICM20602::Run()
|
|
|
|
|
if (transfer(_dma_data_buffer, _dma_data_buffer, transfer_size) != PX4_OK) {
|
|
|
|
|
perf_end(_transfer_perf);
|
|
|
|
|
perf_count(_bad_transfer_perf);
|
|
|
|
|
return;
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
perf_end(_transfer_perf);
|
|
|
|
|
|
|
|
|
|
bool bad_data = false;
|
|
|
|
|
|
|
|
|
|
ProcessGyro(timestamp_sample, report, samples);
|
|
|
|
|
|
|
|
|
|
if (!ProcessAccel(timestamp_sample, report, samples)) {
|
|
|
|
|
bad_data = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// limit temperature updates to 1 Hz
|
|
|
|
|
if (hrt_elapsed_time(&_temperature_update_timestamp) > 1_s) {
|
|
|
|
|
_temperature_update_timestamp = timestamp_sample;
|
|
|
|
|
|
|
|
|
|
if (!ProcessTemperature(report, samples)) {
|
|
|
|
|
bad_data = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return !bad_data;
|
|
|
|
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}
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void ICM20602::FIFOReset()
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{
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perf_count(_fifo_reset_perf);
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// FIFO_EN: disable FIFO
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RegisterWrite(Register::FIFO_EN, 0);
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// USER_CTRL: disable FIFO and reset all signal paths
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RegisterSetAndClearBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_RST | USER_CTRL_BIT::SIG_COND_RST,
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USER_CTRL_BIT::FIFO_EN);
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// reset while FIFO is disabled
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_fifo_watermark_interrupt_timestamp = 0;
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_fifo_read_samples.store(0);
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// FIFO_EN: enable both gyro and accel
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// USER_CTRL: re-enable FIFO
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for (const auto &r : _register_cfg) {
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if ((r.reg == Register::FIFO_EN) || (r.reg == Register::USER_CTRL)) {
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RegisterSetAndClearBits(r.reg, r.set_bits, r.clear_bits);
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}
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}
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}
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static bool fifo_accel_equal(const FIFO::DATA &f0, const FIFO::DATA &f1)
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{
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return (memcmp(&f0.ACCEL_XOUT_H, &f1.ACCEL_XOUT_H, 6) == 0);
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}
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bool ICM20602::ProcessAccel(const hrt_abstime ×tamp_sample, const TransferBuffer *const report, uint8_t samples)
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{
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PX4Accelerometer::FIFOSample accel;
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accel.timestamp_sample = timestamp_sample;
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accel.dt = _fifo_empty_interval_us / _fifo_accel_samples;
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bool bad_data = false;
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// accel data is doubled in FIFO, but might be shifted
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int accel_first_sample = 0;
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int accel_first_sample = 1;
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if (samples >= 3) {
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if (fifo_accel_equal(report->f[0], report->f[1])) {
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@ -503,7 +618,7 @@ void ICM20602::Run()
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} else {
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perf_count(_bad_transfer_perf);
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return;
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bad_data = true;
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}
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}
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@ -515,7 +630,8 @@ void ICM20602::Run()
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int16_t accel_y = combine(fifo_sample.ACCEL_YOUT_H, fifo_sample.ACCEL_YOUT_L);
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int16_t accel_z = combine(fifo_sample.ACCEL_ZOUT_H, fifo_sample.ACCEL_ZOUT_L);
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// sensor's frame is +x forward, +y left, +z up, flip y & z to publish right handed (x forward, y right, z down)
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// sensor's frame is +x forward, +y left, +z up
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// flip y & z to publish right handed with z down (x forward, y right, z down)
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accel.x[accel_samples] = accel_x;
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accel.y[accel_samples] = (accel_y == INT16_MIN) ? INT16_MAX : -accel_y;
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accel.z[accel_samples] = (accel_z == INT16_MIN) ? INT16_MAX : -accel_z;
|
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|
@ -524,30 +640,44 @@ void ICM20602::Run()
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accel.samples = accel_samples;
|
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|
|
_px4_accel.updateFIFO(accel);
|
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|
|
return !bad_data;
|
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|
|
}
|
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|
void ICM20602::ProcessGyro(const hrt_abstime ×tamp_sample, const TransferBuffer *const report, uint8_t samples)
|
|
|
|
|
{
|
|
|
|
|
PX4Gyroscope::FIFOSample gyro;
|
|
|
|
|
gyro.timestamp_sample = timestamp_sample;
|
|
|
|
|
gyro.samples = samples;
|
|
|
|
|
gyro.dt = _fifo_empty_interval_us / _fifo_gyro_samples;
|
|
|
|
|
|
|
|
|
|
int16_t temperature[samples];
|
|
|
|
|
|
|
|
|
|
for (int i = 0; i < samples; i++) {
|
|
|
|
|
const FIFO::DATA &fifo_sample = report->f[i];
|
|
|
|
|
|
|
|
|
|
temperature[i] = combine(fifo_sample.TEMP_OUT_H, fifo_sample.TEMP_OUT_L);
|
|
|
|
|
|
|
|
|
|
const int16_t gyro_x = combine(fifo_sample.GYRO_XOUT_H, fifo_sample.GYRO_XOUT_L);
|
|
|
|
|
const int16_t gyro_y = combine(fifo_sample.GYRO_YOUT_H, fifo_sample.GYRO_YOUT_L);
|
|
|
|
|
const int16_t gyro_z = combine(fifo_sample.GYRO_ZOUT_H, fifo_sample.GYRO_ZOUT_L);
|
|
|
|
|
|
|
|
|
|
// sensor's frame is +x forward, +y left, +z up, flip y & z to publish right handed (x forward, y right, z down)
|
|
|
|
|
// sensor's frame is +x forward, +y left, +z up
|
|
|
|
|
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
|
|
|
|
gyro.x[i] = gyro_x;
|
|
|
|
|
gyro.y[i] = (gyro_y == INT16_MIN) ? INT16_MAX : -gyro_y;
|
|
|
|
|
gyro.z[i] = (gyro_z == INT16_MIN) ? INT16_MAX : -gyro_z;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Temperature
|
|
|
|
|
_px4_gyro.updateFIFO(gyro);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20602::ProcessTemperature(const TransferBuffer *const report, uint8_t samples)
|
|
|
|
|
{
|
|
|
|
|
int16_t temperature[samples];
|
|
|
|
|
|
|
|
|
|
for (int i = 0; i < samples; i++) {
|
|
|
|
|
const FIFO::DATA &fifo_sample = report->f[i];
|
|
|
|
|
temperature[i] = combine(fifo_sample.TEMP_OUT_H, fifo_sample.TEMP_OUT_L);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int32_t temperature_sum{0};
|
|
|
|
|
|
|
|
|
|
for (auto t : temperature) {
|
|
|
|
@ -560,7 +690,7 @@ void ICM20602::Run()
|
|
|
|
|
// temperature changing wildly is an indication of a transfer error
|
|
|
|
|
if (fabsf(t - temperature_avg) > 1000) {
|
|
|
|
|
perf_count(_bad_transfer_perf);
|
|
|
|
|
return;
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@ -569,24 +699,5 @@ void ICM20602::Run()
|
|
|
|
|
_px4_accel.set_temperature(temperature_C);
|
|
|
|
|
_px4_gyro.set_temperature(temperature_C);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
_px4_gyro.updateFIFO(gyro);
|
|
|
|
|
_px4_accel.updateFIFO(accel);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20602::PrintInfo()
|
|
|
|
|
{
|
|
|
|
|
PX4_INFO("FIFO empty interval: %d us (%.3f Hz)", _fifo_empty_interval_us,
|
|
|
|
|
static_cast<double>(1000000 / _fifo_empty_interval_us));
|
|
|
|
|
|
|
|
|
|
perf_print_counter(_transfer_perf);
|
|
|
|
|
perf_print_counter(_bad_register_perf);
|
|
|
|
|
perf_print_counter(_bad_transfer_perf);
|
|
|
|
|
perf_print_counter(_fifo_empty_perf);
|
|
|
|
|
perf_print_counter(_fifo_overflow_perf);
|
|
|
|
|
perf_print_counter(_fifo_reset_perf);
|
|
|
|
|
perf_print_counter(_drdy_interval_perf);
|
|
|
|
|
|
|
|
|
|
_px4_accel.print_status();
|
|
|
|
|
_px4_gyro.print_status();
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|