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PIC32MX1/2 pin selection logic; Mirtoo LEDs, SPI2, and UART2 configuration 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4853 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2012-06-20 17:37:20 +00:00
parent 048a62dba9
commit a81c274be8
18 changed files with 1227 additions and 192 deletions
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256
nuttx/arch/mips/include/pic32mx/chip.h
View File

@ -47,7 +47,7 @@
****************************************************************************/
/* Configuration ************************************************************/
#if defined(PIC32MX110F016B)
#if defined(CONFIG_ARCH_CHIP_PIC32MX110F016B)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -60,13 +60,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -81,7 +83,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX110F016C)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX110F016C)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -94,13 +96,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -115,7 +119,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX110F016D)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX110F016D)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -128,13 +132,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -149,7 +155,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX120F032B)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX120F032B)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -162,13 +168,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -183,7 +191,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX120F032C)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX120F032C)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -196,13 +204,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -217,7 +227,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX120F032D)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX120F032D)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -230,13 +240,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -251,7 +263,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX130F064B)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX130F064B)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -264,13 +276,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -285,7 +299,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX130F064C)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX130F064C)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -298,13 +312,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -319,7 +335,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX130F064D)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX130F064D)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -332,13 +348,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -353,7 +371,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX150F128B)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX150F128B)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -366,13 +384,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -387,7 +407,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX150F128C)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX150F128C)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -400,13 +420,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -421,7 +443,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX150F128D)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX150F128D)
# define CHIP_PIC32MX1 1
# undef CHIP_PIC32MX2
# undef CHIP_PIC32MX3
@ -434,13 +456,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -455,7 +479,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX210F016B)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX210F016B)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -468,13 +492,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -489,7 +515,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX210F016C)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX210F016C)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -502,13 +528,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -523,7 +551,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX210F016D)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX210F016D)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -536,13 +564,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -557,7 +587,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX220F032B)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX220F032B)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -570,13 +600,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -591,7 +623,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX220F032C)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX220F032C)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -604,13 +636,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -625,7 +659,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX220F032D)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX220F032D)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -638,13 +672,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -659,7 +695,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX230F064B)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX230F064B)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -672,13 +708,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -693,7 +731,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX230F064C)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX230F064C)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -706,13 +744,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -727,7 +767,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX230F064D)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX230F064D)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -740,13 +780,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -761,7 +803,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX250F128B)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX250F128B)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -774,13 +816,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -795,7 +839,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX250F128C)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX250F128C)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -808,13 +852,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -829,7 +875,7 @@
# define CHIP_PSP 0 /* No parallel slave port (?) */
# define CHIP_NETHERNET 0 /* No Ethernet */
# define CHIP_JTAG 1 /* Has JTAG */
#elif defined(PIC32MX250F128D)
#elif defined(CONFIG_ARCH_CHIP_PIC32MX250F128D)
# undef CHIP_PIC32MX1
# define CHIP_PIC32MX2 1
# undef CHIP_PIC32MX3
@ -842,13 +888,15 @@
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# undef CHIP_CHE /* No pre-fetch cache controller */
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
# define CHIP_CTMU 1 /* Has CTMU */
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
@ -876,6 +924,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -907,6 +957,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -938,6 +990,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -969,6 +1023,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1000,6 +1056,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1031,6 +1089,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1062,6 +1122,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1093,6 +1155,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1124,6 +1188,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1155,6 +1221,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1186,6 +1254,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1217,6 +1287,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1248,6 +1320,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1279,6 +1353,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1310,6 +1386,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1341,6 +1419,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1372,6 +1452,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1403,8 +1485,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1434,8 +1518,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1465,8 +1551,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1496,8 +1584,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1527,8 +1617,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1558,8 +1650,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1589,8 +1683,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1620,8 +1716,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1651,8 +1749,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1682,8 +1782,10 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
@ -1713,9 +1815,11 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */ /* 5 output compare */
# define CHIP_NOC 5 /* 5 output compare */
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
# define CHIP_NUSBDMACHAN tbd
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
@ -1744,6 +1848,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1775,6 +1881,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1806,6 +1914,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1837,6 +1947,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1868,6 +1980,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1899,6 +2013,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1930,6 +2046,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1961,6 +2079,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -1992,6 +2112,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -2023,6 +2145,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -2054,6 +2178,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -2085,6 +2211,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -2116,6 +2244,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -2147,6 +2277,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -2178,6 +2310,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -2209,6 +2343,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */
@ -2240,6 +2376,8 @@
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
# define CHIP_NTIMERS 5 /* 5 timers */
# define CHIP_NIC 5 /* 5 input capture */
# define CHIP_NOC 5 /* 5 output compare */

178
nuttx/arch/mips/src/pic32mx/pic32mx-can.h
View File

@ -1,89 +1,89 @@
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx-can.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx-memorymap.h"
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#warning "To be provided"
/* Register Addresses *******************************************************/
#warning "To be provided"
/* Register Bit-Field Definitions *******************************************/
#warning "To be provided"
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H */
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx-can.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx-memorymap.h"
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#warning "To be provided"
/* Register Addresses *******************************************************/
#warning "To be provided"
/* Register Bit-Field Definitions *******************************************/
#warning "To be provided"
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H */

8
nuttx/arch/mips/src/pic32mx/pic32mx-config.h
View File

@ -601,6 +601,14 @@
# define CONFIG_PIC32MX_USERID 0x584e /* "NutX" */
#endif
#ifndef CONFIG_PIC32MX_PMDL1WAY /* Peripheral module disable configuration */
# define CONFIG_PIC32MX_PMDL1WAY 0
#endif
#ifndef CONFIG_PIC32MX_IOL1WAY /* Peripheral pin select configuration */
# define CONFIG_PIC32MX_IOL1WAY 0
#endif
#ifndef CONFIG_PIC32MX_SRSSEL /* Shadow register interrupt priority */
# define CONFIG_PIC32MX_SRSSEL INT_IPC_MIN_PRIORITY
#endif

35
nuttx/arch/mips/src/pic32mx/pic32mx-gpio.c
View File

@ -48,6 +48,7 @@
#include <arch/board/board.h>
#include "up_arch.h"
#include "chip.h"
#include "pic32mx-ioport.h"
#include "pic32mx-internal.h"
@ -55,8 +56,6 @@
* Pre-processor Definitions
****************************************************************************/
#define GPIO_NPORTS 7
/****************************************************************************
* Public Data
****************************************************************************/
@ -65,11 +64,27 @@
* Private Data
****************************************************************************/
static const uintptr_t g_gpiobase[GPIO_NPORTS] =
static const uintptr_t g_gpiobase[CHIP_NPORTS] =
{
PIC32MX_IOPORTA_K1BASE, PIC32MX_IOPORTB_K1BASE, PIC32MX_IOPORTC_K1BASE,
PIC32MX_IOPORTD_K1BASE, PIC32MX_IOPORTE_K1BASE, PIC32MX_IOPORTF_K1BASE,
PIC32MX_IOPORTG_K1BASE
PIC32MX_IOPORTA_K1BASE
#if CHIP_NPORTS > 1
, PIC32MX_IOPORTB_K1BASE
#endif
#if CHIP_NPORTS > 2
, PIC32MX_IOPORTC_K1BASE
#endif
#if CHIP_NPORTS > 3
, PIC32MX_IOPORTD_K1BASE
#endif
#if CHIP_NPORTS > 4
, PIC32MX_IOPORTE_K1BASE
#endif
#if CHIP_NPORTS > 5
, PIC32MX_IOPORTF_K1BASE
#endif
#if CHIP_NPORTS > 6
, PIC32MX_IOPORTG_K1BASE
#endif
};
/****************************************************************************
@ -134,7 +149,7 @@ int pic32mx_configgpio(uint16_t cfgset)
/* Verify that the port number is within range */
if (port < GPIO_NPORTS)
if (port < CHIP_NPORTS)
{
/* Get the base address of the ports */
@ -205,7 +220,7 @@ void pic32mx_gpiowrite(uint16_t pinset, bool value)
/* Verify that the port number is within range */
if (port < GPIO_NPORTS)
if (port < CHIP_NPORTS)
{
/* Get the base address of the ports */
@ -240,7 +255,7 @@ bool pic32mx_gpioread(uint16_t pinset)
/* Verify that the port number is within range */
if (port < GPIO_NPORTS)
if (port < CHIP_NPORTS)
{
/* Get the base address of the ports */
@ -271,7 +286,7 @@ void pic32mx_dumpgpio(uint32_t pinset, const char *msg)
/* Verify that the port number is within range */
if (port < GPIO_NPORTS)
if (port < CHIP_NPORTS)
{
/* Get the base address of the ports */

7
nuttx/arch/mips/src/pic32mx/pic32mx-head.S
View File

@ -597,12 +597,19 @@ halt:
.type devconfig, object
devconfig:
devconfig3:
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
.long CONFIG_PIC32MX_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MX_PMDL1WAY << 28 | CONFIG_PIC32MX_IOL1WAY << 29 | \
CONFIG_PIC32MX_USBIDO << 30 | CONFIG_PIC32MX_VBUSIO << 31 | \
DEVCFG3_UNUSED
#else
.long CONFIG_PIC32MX_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MX_SRSSEL << DEVCFG3_FSRSSEL_SHIFT | \
CONFIG_PIC32MX_FMIIEN << 24 | CONFIG_PIC32MX_FETHIO << 25 | \
CONFIG_PIC32MX_FCANIO << 26 | CONFIG_PIC32MX_FSCM1IO << 29 | \
CONFIG_PIC32MX_USBIDO << 30 | CONFIG_PIC32MX_VBUSIO << 31 | \
DEVCFG3_UNUSED
#endif
devconfig2:
.long CONFIG_PIC32MX_PLLIDIV | CONFIG_PIC32MX_PLLMULT | \

2
nuttx/arch/mips/src/pic32mx/pic32mx-int.h
View File

@ -457,7 +457,7 @@
# define INT_CMP1 (1 << 0) /* Vector: 27, Comparator 1 Interrupt */
# define INT_CMP2 (1 << 1) /* Vector: 28, Comparator 2 Interrupt */
# define INT_CMP2 (1 << 2) /* Vector: 29, Comparator 3 Interrupt */
# define INT_CMP3 (1 << 2) /* Vector: 29, Comparator 3 Interrupt */
# define INT_USB (1 << 3) /* Vector: 30, USB */
# define INT_SPI1E (1 << 4) /* Vector: 31, SPI1 */
# define INT_SPI1TX (1 << 5) /* Vector: 31, " " */

9
nuttx/arch/mips/src/pic32mx/pic32mx-lowinit.c
View File

@ -46,6 +46,7 @@
#include "up_internal.h"
#include "up_arch.h"
#include "chip.h"
#include "pic32mx-internal.h"
#include "pic32mx-bmx.h"
#include "pic32mx-che.h"
@ -109,13 +110,16 @@
static inline void pic32mx_waitstates(void)
{
#ifdef CHIP_CHE
unsigned int nwaits;
unsigned int residual;
#endif
/* Disable DRM wait states */
putreg32(BMX_CON_BMXWSDRM, PIC32MX_BMX_CONCLR);
#ifdef CHIP_CHE
/* Configure pre-fetch cache FLASH wait states */
residual = BOARD_CPU_CLOCK;
@ -131,6 +135,7 @@ static inline void pic32mx_waitstates(void)
/* Set the FLASH wait states -- clearing all other bits! */
putreg32(nwaits, PIC32MX_CHE_CON);
#endif
}
/****************************************************************************
@ -148,11 +153,13 @@ static inline void pic32mx_cache(void)
{
register uint32_t regval;
/* Enable caching on all regions */
/* Enable prefetch on all regions */
#ifdef CHIP_CHE
regval = getreg32(PIC32MX_CHE_CON);
regval |= CHE_CON_PREFEN_ALL;
putreg32(regval, PIC32MX_CHE_CON);
#endif
/* Enable cache on KSEG 0 in the CP0 CONFIG register*/

275
nuttx/arch/mips/src/pic32mx/pic32mx-pps.h Normal file
View File

@ -0,0 +1,275 @@
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx-pps.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PPS_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PPS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx-memorymap.h"
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
/* Peripheral pin select input registers */
#define PIC32MX_PPS_INT1R_OFFSET 0x0004
#define PIC32MX_PPS_INT2R_OFFSET 0x0008
#define PIC32MX_PPS_INT3R_OFFSET 0x000c
#define PIC32MX_PPS_INT4R_OFFSET 0x0010
#define PIC32MX_PPS_T2CKR_OFFSET 0x0018
#define PIC32MX_PPS_T3CKR_OFFSET 0x001c
#define PIC32MX_PPS_T4CKR_OFFSET 0x0020
#define PIC32MX_PPS_T5CKR_OFFSET 0x0024
#define PIC32MX_PPS_IC1R_OFFSET 0x0028
#define PIC32MX_PPS_IC2R_OFFSET 0x002c
#define PIC32MX_PPS_IC3R_OFFSET 0x0030
#define PIC32MX_PPS_IC4R_OFFSET 0x0034
#define PIC32MX_PPS_IC5R_OFFSET 0x0038
#define PIC32MX_PPS_OCFAR_OFFSET 0x0048
#define PIC32MX_PPS_OCFBR_OFFSET 0x004c
#define PIC32MX_PPS_U1RXR_OFFSET 0x0050
#define PIC32MX_PPS_U1CTSR_OFFSET 0x0054
#define PIC32MX_PPS_U2RXR_OFFSET 0x0058
#define PIC32MX_PPS_U2CTSR_OFFSET 0x005c
#define PIC32MX_PPS_SDI1R_OFFSET 0x0084
#define PIC32MX_PPS_SS1R_OFFSET 0x0088
#define PIC32MX_PPS_SDI2R_OFFSET 0x0090
#define PIC32MX_PPS_SS2R_OFFSET 0x0094
#define PIC32MX_PPS_REFCLKIR_OFFSET 0x00b8
/* Peripheral pin select output registers */
#define PIC32MX_PPS_RPA0R_OFFSET 0x0000
#define PIC32MX_PPS_RPA1R_OFFSET 0x0004
#define PIC32MX_PPS_RPA2R_OFFSET 0x0008
#define PIC32MX_PPS_RPA3R_OFFSET 0x000c
#define PIC32MX_PPS_RPA4R_OFFSET 0x0010
#define PIC32MX_PPS_RPA8R_OFFSET 0x0020
#define PIC32MX_PPS_RPA9R_OFFSET 0x0024
#define PIC32MX_PPS_RPB0R_OFFSET 0x002c
#define PIC32MX_PPS_RPB1R_OFFSET 0x0030
#define PIC32MX_PPS_RPB2R_OFFSET 0x0034
#define PIC32MX_PPS_RPB3R_OFFSET 0x0038
#define PIC32MX_PPS_RPB4R_OFFSET 0x003c
#define PIC32MX_PPS_RPB5R_OFFSET 0x0040
#define PIC32MX_PPS_RPB6R_OFFSET 0x0044
#define PIC32MX_PPS_RPB7R_OFFSET 0x0048
#define PIC32MX_PPS_RPB8R_OFFSET 0x004c
#define PIC32MX_PPS_RPB9R_OFFSET 0x0050
#define PIC32MX_PPS_RPB10R_OFFSET 0x0054
#define PIC32MX_PPS_RPB11R_OFFSET 0x0058
#define PIC32MX_PPS_RPB13R_OFFSET 0x0060
#define PIC32MX_PPS_RPB14R_OFFSET 0x0064
#define PIC32MX_PPS_RPB15R_OFFSET 0x0068
#define PIC32MX_PPS_RPC0R_OFFSET 0x006c
#define PIC32MX_PPS_RPC1R_OFFSET 0x0070
#define PIC32MX_PPS_RPC2R_OFFSET 0x0074
#define PIC32MX_PPS_RPC3R_OFFSET 0x0078
#define PIC32MX_PPS_RPC4R_OFFSET 0x007c
#define PIC32MX_PPS_RPC5R_OFFSET 0x0080
#define PIC32MX_PPS_RPC6R_OFFSET 0x0084
#define PIC32MX_PPS_RPC7R_OFFSET 0x0088
#define PIC32MX_PPS_RPC8R_OFFSET 0x008c
#define PIC32MX_PPS_RPC9R_OFFSET 0x0090
/* Register Addresses *******************************************************/
/* Peripheral pin select input registers */
#define PIC32MX_PPS_INT1R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_INT1R_OFFSET)
#define PIC32MX_PPS_INT2R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_INT2R_OFFSET)
#define PIC32MX_PPS_INT3R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_INT3R_OFFSET)
#define PIC32MX_PPS_INT4R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_INT4R_OFFSET)
#define PIC32MX_PPS_T2CKR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_T2CKR_OFFSET)
#define PIC32MX_PPS_T3CKR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_T3CKR_OFFSET)
#define PIC32MX_PPS_T4CKR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_T4CKR_OFFSET)
#define PIC32MX_PPS_T5CKR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_T5CKR_OFFSET)
#define PIC32MX_PPS_IC1R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC1R_OFFSET)
#define PIC32MX_PPS_IC2R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC2R_OFFSET)
#define PIC32MX_PPS_IC3R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC3R_OFFSET)
#define PIC32MX_PPS_IC4R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC4R_OFFSET)
#define PIC32MX_PPS_IC5R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC5R_OFFSET)
#define PIC32MX_PPS_OCFAR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_OCFAR_OFFSET)
#define PIC32MX_PPS_OCFBR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_OCFBR_OFFSET)
#define PIC32MX_PPS_U1RXR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_U1RXR_OFFSET)
#define PIC32MX_PPS_U1CTSR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_U1CTSR_OFFSET)
#define PIC32MX_PPS_U2RXR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_U2RXR_OFFSET)
#define PIC32MX_PPS_U2CTSR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_U2CTSR_OFFSET)
#define PIC32MX_PPS_SDI1R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_SDI1R_OFFSET)
#define PIC32MX_PPS_SS1R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_SS1R_OFFSET)
#define PIC32MX_PPS_SDI2R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_SDI2R_OFFSET)
#define PIC32MX_PPS_SS2R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_SS2R_OFFSET)
#define PIC32MX_PPS_REFCLKIR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_REFCLKIR_OFFSET)
/* Peripheral pin select output registers */
#define PIC32MX_PPS_RPA0R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA0R_OFFSET)
#define PIC32MX_PPS_RPA1R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA1R_OFFSET)
#define PIC32MX_PPS_RPA2R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA2R_OFFSET)
#define PIC32MX_PPS_RPA3R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA3R_OFFSET)
#define PIC32MX_PPS_RPA4R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA4R_OFFSET)
#define PIC32MX_PPS_RPA8R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA8R_OFFSET)
#define PIC32MX_PPS_RPA9R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA9R_OFFSET)
#define PIC32MX_PPS_RPB0R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB0R_OFFSET)
#define PIC32MX_PPS_RPB1R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB1R_OFFSET)
#define PIC32MX_PPS_RPB2R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB2R_OFFSET)
#define PIC32MX_PPS_RPB3R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB3R_OFFSET)
#define PIC32MX_PPS_RPB4R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB4R_OFFSET)
#define PIC32MX_PPS_RPB5R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB5R_OFFSET)
#define PIC32MX_PPS_RPB6R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB6R_OFFSET)
#define PIC32MX_PPS_RPB7R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB7R_OFFSET)
#define PIC32MX_PPS_RPB8R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB8R_OFFSET)
#define PIC32MX_PPS_RPB9R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB9R_OFFSET)
#define PIC32MX_PPS_RPB10R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB10R_OFFSET)
#define PIC32MX_PPS_RPB11R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB11R_OFFSET)
#define PIC32MX_PPS_RPB13R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB13R_OFFSET)
#define PIC32MX_PPS_RPB14R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB14R_OFFSET)
#define PIC32MX_PPS_RPB15R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB15R_OFFSET)
#define PIC32MX_PPS_RPC0R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC0R_OFFSET)
#define PIC32MX_PPS_RPC1R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC1R_OFFSET)
#define PIC32MX_PPS_RPC2R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC2R_OFFSET)
#define PIC32MX_PPS_RPC3R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC3R_OFFSET)
#define PIC32MX_PPS_RPC4R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC4R_OFFSET)
#define PIC32MX_PPS_RPC5R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC5R_OFFSET)
#define PIC32MX_PPS_RPC6R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC6R_OFFSET)
#define PIC32MX_PPS_RPC7R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC7R_OFFSET)
#define PIC32MX_PPS_RPC8R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC8R_OFFSET)
#define PIC32MX_PPS_RPC9R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC9R_OFFSET)
/* Register Bit-Field Definitions *******************************************/
/* Peripheral pin select input registers */
#define PPS_INSEL_MASK 0x0000000f
#define PPS_INSEL_RPA0 0
#define PPS_INSEL_RPB3 1
#define PPS_INSEL_RPB4 2
#define PPS_INSEL_RPB15 3
#define PPS_INSEL_RPB7 4
#define PPS_INSEL_RPC7 5
#define PPS_INSEL_RPC0 6
#define PPS_INSEL_RPC5 7
#define PPS_INSEL_RPA1 0
#define PPS_INSEL_RPB5 1
#define PPS_INSEL_RPB1 2
#define PPS_INSEL_RPB11 3
#define PPS_INSEL_RPB8 4
#define PPS_INSEL_RPA8 5
#define PPS_INSEL_RPC8 6
#define PPS_INSEL_RPA9 7
#define PPS_INSEL_RPA2 0
#define PPS_INSEL_RPB6 1
#define PPS_INSEL_RPA4 2
#define PPS_INSEL_RPB13 3
#define PPS_INSEL_RPB2 4
#define PPS_INSEL_RPC6 5
#define PPS_INSEL_RPC1 6
#define PPS_INSEL_RPC3 7
#define PPS_INSEL_RPA3 0
#define PPS_INSEL_RPB14 1
#define PPS_INSEL_RPB0 2
#define PPS_INSEL_RPB10 3
#define PPS_INSEL_RPB9 4
#define PPS_INSEL_RPC9 5
#define PPS_INSEL_RPC2 6
#define PPS_INSEL_RPC4 7
/* Peripheral pin select output registers */
#define PPS_OUTSEL_MASK 0x0000000f
#define PPS_OUTSEL_NOCONNECT 0
#define PPS_OUTSEL_U1TX 1
#define PPS_OUTSEL_U2RTS 2
#define PPS_OUTSEL_SS1 3
#define PPS_OUTSEL_OC1 5
#define PPS_OUTSEL_C2OUT 7
#define PPS_OUTSEL_SDO1 3
#define PPS_OUTSEL_SDO2 4
#define PPS_OUTSEL_OC2 5
//#define PPS_OUTSEL_SDO1 3
//#define PPS_OUTSEL_SDO2 4
#define PPS_OUTSEL_OC4 5
#define PPS_OUTSEL_OC5 6
#define PPS_OUTSEL_REFCLKO 7
#define PPS_OUTSEL_U1RTS 1
#define PPS_OUTSEL_U2TX 2
#define PPS_OUTSEL_SS2 4
#define PPS_OUTSEL_OC3 5
#define PPS_OUTSEL_C1OUT 7
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CHIP_PIC32MX1 || CHIP_PIC32MX2 */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PPS_H */

40
nuttx/configs/mirtoo/README.txt
View File

@ -1,4 +1,4 @@
configs/pic32mx README
configs/mirtoo README
=====================
This README file discusses the port of NuttX to the DTX1-4000L "Mirtoo" module.
@ -11,6 +11,7 @@ Contents
PIC32MX250F128D Pin Out
Toolchains
Loading NuttX with ICD3
LED Usage
PIC32MX Configuration Options
Configurations
@ -53,15 +54,15 @@ PIN PIC32 SIGNAL(s) BOARD SIGNAL/USAGE
--- ------------------------------------------------ ---------------------------------- ----------------------------------
7 VCAP VCAP Not available off module
--- ------------------------------------------------ ---------------------------------- ----------------------------------
8 PGED2/RPB10/D+/CTED11/RB10 FUNC0 FUNC0, to FT230XS RXD
PGED2 Debug Channel 2 data Not available
8 PGED2/RPB10/D+/CTED11/RB10 FUNC0 FUNC0, to FT230XS RXD and debug port
PGED2 Debug Channel 2 data Used at boot time for ICD3
RPB10 Peripheral Selection, PORTB, Pin 10 Used for UART RXD
D+ USB D+ Not available
CTED11 CTMU External Edge Input 11 Not available
RB10 PORTB, Pin 10 Not available
--- ------------------------------------------------ ---------------------------------- ----------------------------------
9 PGEC2/RPB11/D-/RB11 FUNC1 FUNC1, to FT230XS TXD
PGEC2 Debug Channel 2 clock Not available
PGEC2 Debug Channel 2 clock Used at boot time for ICD3
RPB11 Peripheral Selection, PORTB, Pin 11 Used for UART TXD
D- USB D- Not available
RB11 PORTB, Pin 11 Not available
@ -412,6 +413,35 @@ Loading NuttX with ICD3
# to the top-level build directory. It is the only
# required input to mkpichex.
LED Usage
=========
The Mirtoo module has 2 user LEDs labeled LED0 and LED1 in the schematics:
--- ----- --------------------------------------------------------------
PIN Board Notes
--- ----- --------------------------------------------------------------
RC8 LED0 Grounded, high value illuminates
RC9 LED1 Grounded, high value illuminates
The Dimitech DTX1-4000L EV-kit1 supports 3 more LEDs, but there are not
controllable from software.
If CONFIG_ARCH_LEDS is defined, then NuttX will control these LEDs as
follows:
ON OFF
------------------------- ---- ---- ---- ----
LED0 LED1 LED0 LED1
------------------------- ---- ---- ---- ----
LED_STARTED 0 OFF OFF --- ---
LED_HEAPALLOCATE 1 ON OFF --- ---
LED_IRQSENABLED 2 OFF ON --- ---
LED_STACKCREATED 3 ON ON --- ---
LED_INIRQ 4 ON N/C OFF N/C
LED_SIGNAL 4 ON N/C OFF N/C
LED_ASSERTION 4 ON N/C OFF N/C
LED_PANIC 4 ON N/C OFF N/C
PIC32MX Configuration Options
=============================
@ -522,11 +552,13 @@ PIC32MX Configuration Options
CONFIG_PIC32MX_PMP - Parallel Master Port
CONFIG_PIC32MX_CM1 - Comparator 1
CONFIG_PIC32MX_CM2 - Comparator 2
CONFIG_PIC32MX_CM3 - Comparator 3
CONFIG_PIC32MX_RTCC - Real-Time Clock and Calendar
CONFIG_PIC32MX_DMA - DMA
CONFIG_PIC32MX_FLASH - FLASH
CONFIG_PIC32MX_USBDEV - USB device
CONFIG_PIC32MX_USBHOST - USB host
CONFIG_PIC32MX_CTMU - CTMU
PIC32MX Configuration Settings
DEVCFG0:

63
nuttx/configs/mirtoo/include/board.h
View File

@ -42,6 +42,9 @@
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/****************************************************************************
* Pre-Processor Definitions
@ -85,15 +88,53 @@
#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */
/* LED definitions **********************************************************/
/* The Mirtoo module has 2 user LEDs labeled LED0 and LED1 in the schematics:
*
* --- ----- --------------------------------------------------------------
* PIN Board Notes
* --- ----- --------------------------------------------------------------
* RC8 LED0 Grounded, high value illuminates
* RC9 LED1 Grounded, high value illuminates
*
* The Dimitech DTX1-4000L EV-kit1 supports 3 more LEDs, but there are not
* controllable from software.
*/
/* LED index values for use with pic32mx_setled() */
#define PIC32MX_MIRTOO_LED0 0
#define PIC32MX_MIRTOO_LED1 1
#define PIC32MX_MIRTOO_NLEDS 2
/* LED bits for use with pic32mx_setleds() */
#define PIC32MX_MIRTOO_LED0_BIT (1 << PIC32MX_MIRTOO_LED0)
#define PIC32MX_MIRTOO_LED1_BIT (1 << PIC32MX_MIRTOO_LED1)
/* If CONFIG_ARCH_LEDS is defined, then NuttX will control these LEDs as
* follows:
* ON OFF
* ------------------------- ---- ---- ---- ----
* LED0 LED1 LED0 LED1
* ------------------------- ---- ---- ---- ----
* LED_STARTED 0 OFF OFF --- ---
* LED_HEAPALLOCATE 1 ON OFF --- ---
* LED_IRQSENABLED 2 OFF ON --- ---
* LED_STACKCREATED 3 ON ON --- ---
* LED_INIRQ 4 ON N/C OFF N/C
* LED_SIGNAL 4 ON N/C OFF N/C
* LED_ASSERTION 4 ON N/C OFF N/C
* LED_PANIC 4 ON N/C OFF N/C
*/
#define LED_STARTED 0
#define LED_HEAPALLOCATE 1
#define LED_IRQSENABLED 2
#define LED_STACKCREATED 3
#define LED_INIRQ 4
#define LED_SIGNAL 5
#define LED_ASSERTION 6
#define LED_PANIC 7
#define LED_SIGNAL 4
#define LED_ASSERTION 4
#define LED_PANIC 4
/****************************************************************************
* Public Types
@ -116,6 +157,22 @@ extern "C" {
#define EXTERN extern
#endif
/****************************************************************************
* Name: pic32mx_ledinit, pic32mx_setled, and pic32mx_setleds
*
* Description:
* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
* LEDs. If CONFIG_ARCH_LEDS is not defined, then the following interfaces
* are available to control the LEDs from user applicaitons.
*
****************************************************************************/
#ifndef CONFIG_ARCH_LEDS
EXTERN void pic32mx_ledinit(void);
EXTERN void pic32mx_setled(int led, bool ledon);
EXTERN void pic32mx_setleds(uint8_t ledset);
#endif
#undef EXTERN
#ifdef __cplusplus
}

18
nuttx/configs/mirtoo/ostest/defconfig
View File

@ -123,8 +123,6 @@ CONFIG_PIC32MX_MICROCHIPL_LITE=n
#
CONFIG_PIC32MX_WDT=n
CONFIG_PIC32MX_RTCC=n
CONFIG_PIC32MX_TIMER1=n
CONFIG_PIC32MX_TIMER2=n
CONFIG_PIC32MX_TIMER3=n
CONFIG_PIC32MX_TIMER4=n
@ -143,13 +141,15 @@ CONFIG_PIC32MX_I2C1=n
CONFIG_PIC32MX_I2C2=n
CONFIG_PIC32MX_SPI1=n
CONFIG_PIC32MX_SPI2=n
CONFIG_PIC32MX_UART1=y
CONFIG_PIC32MX_UART2=n
CONFIG_PIC32MX_PMP=n
CONFIG_PIC32MX_UART1=n
CONFIG_PIC32MX_UART2=y
CONFIG_PIC32MX_ADC=n
CONFIG_PIC32MX_PMP=n
CONFIG_PIC32MX_CVR=n
CONFIG_PIC32MX_CM1=n
CONFIG_PIC32MX_CM2=n
CONFIG_PIC32MX_CM3=n
CONFIG_PIC32MX_RTCC=n
CONFIG_PIC32MX_OSC=y
CONFIG_PIC32MX_DDP=n
CONFIG_PIC32MX_FLASH=n
@ -161,10 +161,6 @@ CONFIG_PIC32MX_USBHOST=n
CONFIG_PIC32MX_IOPORTA=y
CONFIG_PIC32MX_IOPORTB=y
CONFIG_PIC32MX_IOPORTC=y
CONFIG_PIC32MX_IOPORTD=y
CONFIG_PIC32MX_IOPORTE=y
CONFIG_PIC32MX_IOPORTF=y
CONFIG_PIC32MX_IOPORTG=y
#
# PIC32MX Configuration Settings
@ -204,8 +200,8 @@ CONFIG_PIC32MX_ICESEL=1
# CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
# CONFIG_UARTn_2STOP - Two stop bits
#
CONFIG_UART1_SERIAL_CONSOLE=y
CONFIG_UART2_SERIAL_CONSOLE=n
CONFIG_UART1_SERIAL_CONSOLE=n
CONFIG_UART2_SERIAL_CONSOLE=y
CONFIG_UART1_TXBUFSIZE=256
CONFIG_UART2_TXBUFSIZE=256

6
nuttx/configs/mirtoo/src/Makefile
View File

@ -38,10 +38,10 @@
CFLAGS += -I$(TOPDIR)/sched
ASRCS =
CSRCS = up_boot.c
CSRCS = up_boot.c up_leds.c
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += up_leds.c
ifeq ($(CONFIG_PIC32MX_SPI2),y)
CSRCS += up_spi2.c
endif
AOBJS = $(ASRCS:.S=$(OBJEXT))

8
nuttx/configs/mirtoo/src/mirtoo-internal.h
View File

@ -69,15 +69,15 @@ extern "C" {
#endif
/************************************************************************************
* Name: pic32mx_spiinitialize
* Name: pic32mx_spi2initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the PCB Logic board.
* Called to configure SPI2 chip select GPIO pins for the Mirtoo module.
*
************************************************************************************/
#if defined(CONFIG_PIC32MX_SPI1) || defined(CONFIG_PIC32MX_SPI2)
EXTERN void weak_function pic32mx_spiinitialize(void);
#ifdef CONFIG_PIC32MX_SPI2
EXTERN void weak_function pic32mx_spi2initialize(void);
#endif
/************************************************************************************

48
nuttx/configs/mirtoo/src/up_boot.c
View File

@ -48,16 +48,52 @@
#include "up_internal.h"
#include "pic32mx-internal.h"
#include "pic32mx-pps.h"
#include "mirtoo-internal.h"
/************************************************************************************
* Definitions
************************************************************************************/
#define GPIO_U2TX (GPIO_OUTPUT|GPIO_PORTB|GPIO_PIN10)
#define GPIO_U2RX (GPIO_INPUT|GPIO_PORTB|GPIO_PIN11)
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: pic32mx_uartinitialize
*
* Description:
* When mounted on the DTX1-4000L EV-kit1 board, serial output is avaiable through
* an FT230X device via the FUNC0 and FUNC1 module outputs
*
* ---------- ------ ----- ------ -------------------------
* BOARD OUTPUT PIN SIGNAL NOTES
* ---------- ------ ----- ------ -------------------------
* FT230X RXD FUNC0 RPB11 U2RX UART2 RX (Also PGEC2)
* FT230X TXD FUNC1 RPB10 U2TX UART2 TX (Also PGED2)
*
************************************************************************************/
static inline void pic32mx_uartinitialize(void)
{
#ifdef CONFIG_PIC32MX_UART2
/* Make sure that TRIS pins are set correctly. Configure the UART pins as digital
* inputs and outputs first.
*/
pic32mx_configgpio(GPIO_U2TX);
pic32mx_configgpio(GPIO_U2RX);
/* Configure UART TX and RX pins to RPB10 and 11, respectively */
putreg32(PPS_INSEL_RPB11, PIC32MX_PPS_U2RXR);
putreg32(PPS_OUTSEL_U2TX, PIC32MX_PPS_RPB10R);
#endif
}
/************************************************************************************
* Public Functions
************************************************************************************/
@ -74,14 +110,18 @@
void pic32mx_boardinitialize(void)
{
/* Configure the console UART */
pic32mx_uartinitialize();
/* Configure SPI chip selects if 1) at least one SPI is enabled, and 2) the weak
* function pic32mx_spiinitialize() has been brought into the link.
* function pic32mx_spi2initialize() has been brought into the link.
*/
#if defined(CONFIG_PIC32MX_SPI1) || defined(CONFIG_PIC32MX_SPI2)
if (pic32mx_spiinitialize)
#ifdef CONFIG_PIC32MX_SPI2
if (pic32mx_spi2initialize)
{
pic32mx_spiinitialize();
pic32mx_spi2initialize();
}
#endif

258
nuttx/configs/mirtoo/src/up_leds.c Normal file
View File

@ -0,0 +1,258 @@
/****************************************************************************
* configs/mirtoo/src/up_leds.c
* arch/arm/src/board/up_leds.c
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <arch/board/board.h>
#include "pic32mx-internal.h"
#include "mirtoo-internal.h"
/****************************************************************************
* Definitions
****************************************************************************/
/* LED Configuration ********************************************************/
/* The Mirtoo module has 2 user LEDs labeled LED0 and LED1 in the schematics:
*
* --- ----- --------------------------------------------------------------
* PIN Board Notes
* --- ----- --------------------------------------------------------------
* RC8 LED0 Grounded, high value illuminates
* RC9 LED1 Grounded, high value illuminates
*
* The Dimitech DTX1-4000L EV-kit1 supports 3 more LEDs, but there are not
* controllable from software.
*
* If CONFIG_ARCH_LEDS is defined, then NuttX will control these LEDs as
* follows:
* ON OFF
* ------------------------- ---- ---- ---- ----
* LED0 LED1 LED0 LED1
* ------------------------- ---- ---- ---- ----
* LED_STARTED 0 OFF OFF --- ---
* LED_HEAPALLOCATE 1 ON OFF --- ---
* LED_IRQSENABLED 2 OFF ON --- ---
* LED_STACKCREATED 3 ON ON --- ---
* LED_INIRQ 4 ON N/C OFF N/C
* LED_SIGNAL 4 ON N/C OFF N/C
* LED_ASSERTION 4 ON N/C OFF N/C
* LED_PANIC 4 ON N/C OFF N/C
*/
#define GPIO_LED_0 (GPIO_OUTPUT|GPIO_VALUE_ZERO|GPIO_PORTC|GPIO_PIN8)
#define GPIO_LED_1 (GPIO_OUTPUT|GPIO_VALUE_ZERO|GPIO_PORTC|GPIO_PIN9)
/* LED Management Definitions ***********************************************/
#ifdef CONFIG_ARCH_LEDS
# define LED_OFF 0
# define LED_ON 1
# define LED_NC 2
#endif
/* Debug ********************************************************************/
#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_LEDS)
# define leddbg lldbg
# ifdef CONFIG_DEBUG_VERBOSE
# define ledvdbg lldbg
# else
# define ledvdbg(x...)
# endif
#else
# undef CONFIG_DEBUG_LEDS
# undef CONFIG_DEBUG_VERBOSE
# define leddbg(x...)
# define ledvdbg(x...)
#endif
/****************************************************************************
* Private types
****************************************************************************/
#ifdef CONFIG_ARCH_LEDS
struct led_setting_s
{
uint8_t led0 : 2;
uint8_t led1 : 2;
uint8_t unused : 4;
};
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* If CONFIG_ARCH_LEDS is defined then NuttX will control the LEDs. The
* following structures identified the LED settings for each NuttX LED state.
*/
#ifdef CONFIG_ARCH_LEDS
static const struct led_setting_s g_ledonvalues[LED_NVALUES] =
{
{LED_OFF, LED_OFF, 0},
{LED_ON, LED_OFF, 0},
{LED_OFF, LED_ON, 0},
{LED_ON, LED_ON, 0},
{LED_ON, LED_NC, 0},
};
static const struct led_setting_s g_ledoffvalues[LED_NVALUES] =
{
{LED_NC, LED_NC, 0},
{LED_NC, LED_NC, 0},
{LED_NC, LED_NC, 0},
{LED_NC, LED_NC, 0},
{LED_OFF, LED_NC, 0},
};
/* If CONFIG_ARCH_LEDS is not defined, the the user can control the LEDs in
* any way. The following array simply maps the PIC32MX_MIRTOO_LEDn
* index values to the correct LED pin configuration.
*/
#else
static const uint16_t g_ledpincfg[PIC32MX_MIRTOO_NLEDS] =
{
GPIO_LED_0, GPIO_LED_1
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_setleds
****************************************************************************/
#ifdef CONFIG_ARCH_LEDS
void up_setleds(FAR const struct led_setting_s *setting)
{
/* LEDs are pulled up so writing a low value (false) illuminates them */
if (setting->led0 != LED_NC)
{
pic32mx_gpiowrite(GPIO_LED_0, setting->led0 == LED_ON);
}
if (setting->led1 != LED_NC)
{
pic32mx_gpiowrite(GPIO_LED_1, setting->led1 == LED_ON);
}
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: pic32mx_ledinit
****************************************************************************/
void pic32mx_ledinit(void)
{
/* Configure output pins */
pic32mx_configgpio(GPIO_LED_0);
pic32mx_configgpio(GPIO_LED_1);
}
/****************************************************************************
* Name: pic32mx_setled
****************************************************************************/
#ifndef CONFIG_ARCH_LEDS
void pic32mx_setled(int led, bool ledon)
{
/* LEDs are pulled up so writing a low value (false) illuminates them */
if ((unsigned)led < PIC32MX_MIRTOO_NLEDS)
{
pic32mx_gpiowrite(g_ledpincfg[led], ledon);
}
}
#endif
/****************************************************************************
* Name: pic32mx_setleds
****************************************************************************/
#ifndef CONFIG_ARCH_LEDS
void pic32mx_setleds(uint8_t ledset)
{
/* Call pic32mx_setled() with ledon == true to illuminated the LED */
pic32mx_setled(PIC32MX_MIRTOO_LED0, (ledset & PIC32MX_MIRTOO_LED0_BIT) != 0);
pic32mx_setled(PIC32MX_MIRTOO_LED1, (ledset & PIC32MX_MIRTOO_LED1_BIT) != 0);
}
#endif
/****************************************************************************
* Name: up_ledon
****************************************************************************/
#ifdef CONFIG_ARCH_LEDS
void up_ledon(int led)
{
if ((unsigned)led < LED_NVALUES)
{
up_setleds(&g_ledonvalues[led]);
}
}
#endif
/****************************************************************************
* Name: up_ledoff
****************************************************************************/
#ifdef CONFIG_ARCH_LEDS
void up_ledoff(int led)
{
if ((unsigned)led < LED_NVALUES)
{
up_setleds(&g_ledoffvalues[led]);
}
}
#endif

200
nuttx/configs/mirtoo/src/up_spi2.c Normal file
View File

@ -0,0 +1,200 @@
/************************************************************************************
* configs/mirtoo/src/up_spi2.c
* arch/arm/src/board/up_spi2.c
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <nuttx/spi.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "chip.h"
#include "pic32mx-internal.h"
#include "pic32mx-pps.h"
#include "mirtoo_internal.h"
#ifdef CONFIG_PIC32MX_SPI2
/************************************************************************************
* Definitions
************************************************************************************/
/* The Mirtoo module as two on-board SPI devices:
*
* SST25VF032B - 32-Mbit SPI Serial FLASH
*
* PGA117 - Zero drift programmable gain amplifier with MUX. The PGA117 offers 10
* analog inputs, a four-pin SPI interface with daisy-chain capability, and hardware
* and software shutdown in a TSSOP-20 package. Only 8 of the analog inputs (PORT0-7)
* are used on the Mirtoo module.
*
* Chip selects:
*
* ------ -------- ------------------------- --------------------------------
* PIN SIGNAL BOARD CONNECTION NOTES
* ------ -------- ------------------------- --------------------------------
* RPA1 SI PGA117 and SST25VF032B SPI2 data OUT (SDO2)
* RPA2 SO PGA117 and SST25VF032B SPI2 data IN (SDI2)
* SCK2 SCK PGA117 and SST25VF032B SPI2 clock
*
* RB7 ~CSAI PGA117 PGA117 chip select (active low)
* RB13 ~CSM SST25VF032B SST25VF032B chip select (active low)
*/
#define GPIO_SI (GPIO_OUTPUT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_SO (GPIO_INPUT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_SCK (GPIO_OUTPUT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_PGA117_CS (GPIO_OUTPUT|GPIO_VALUE_ONE|GPIO_PORTB|GPIO_PIN7)
#define GPIO_SST25VF032B_CS (GPIO_OUTPUT|GPIO_VALUE_ONE|GPIO_PORTB|GPIO_PIN13)
/* The following enable debug output from this file (needs CONFIG_DEBUG too).
*
* CONFIG_DEBUG_SPI - Define to enable basic SPI debug
*/
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# define spivdbg llvdbg
#else
# define spidbg(x...)
# define spivdbg(x...)
#endif
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: pic32mx_spi2initialize
*
* Description:
* Called to configure SPI2 chip select GPIO pins for the Mirtoo module.
*
************************************************************************************/
void weak_function pic32mx_spi2initialize(void)
{
uint32_t regval;
/* Make sure that TRIS pins are set correctly. Configure the SPI pins as digital
* inputs and outputs first.
*/
pic32mx_configgpio(GPIO_SI);
pic32mx_configgpio(GPIO_SO);
pic32mx_configgpio(GPIO_SCK);
/* Configure SPI2 data in and data out to use RPA2 and 1, respectively */
putreg32(PPS_INSEL_RPA2, PIC32MX_PPS_SDI2R);
putreg32(PPS_OUTSEL_SDO2, PIC32MX_PPS_RPA1R);
/* Configure the SPI chip select GPIOs */
pic32mx_configgpio(GPIO_PGA117_CS);
pic32mx_configgpio(GPIO_SST25VF032B_CS);
}
/************************************************************************************
* Name: pic32mx_spi2select, pic32mx_spi2status, and pic32mx_spi2cmddata
*
* Description:
* These external functions must be provided by board-specific logic. They are
* implementations of the select, status, and cmddata methods of the SPI interface
* defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods
* including up_spiinitialize()) are provided by common PIC32MX logic. To use
* this common SPI logic on your board:
*
* 1. Provide logic in pic32mx_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide pic32mx_spiNselect() and pic32mx_spiNstatus() functions
* in your board-specific logic. These functions will perform chip selection
* and status operations using GPIOs in the way your board is configured.
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
* pic32mx_spiNcmddata() functions in your board-specific logic. These
* functions will perform cmd/data selection operations using GPIOs in the way
* your board is configured.
* 3. Add a call to up_spiinitialize() in your low level application
* initialization logic
* 4. The handle returned by up_spiinitialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
************************************************************************************/
struct spi_dev_s;
enum spi_dev_e;
void pic31mx_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
if (devid == SPIDEV_FLASH)
{
pic32mx_gpiowrite(GPIO_SST25VF032B_CS, !selected);
}
else if (devid == SPIDEV_MUX)
{
pic32mx_gpiowrite(GPIO_PGA117_CS, !selected);
}
}
uint8_t pic31mx_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#ifdef CONFIG_SPI_CMDDATA
int pic31mx_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return 0;
}
#endif
#endif /* CONFIG_PIC32MX_SPI2 */

4
nuttx/configs/pic32mx7mmb/include/board.h
View File

@ -134,8 +134,8 @@
/* LED bits for use with pic32mx_setleds() */
#define PIC32MX_PIC32MX7MMB_LED0_BIT (1 << PIC32MX_PIC32MX7MMB_LED0)
#define PIC32MX_PIC32MX7MMB_LED1_BIT (1 << PIC32MX_PIC32MX7MMB_LED2)
#define PIC32MX_PIC32MX7MMB_LED2_BIT (1 << PIC32MX_PIC32MX7MMB_LED3)
#define PIC32MX_PIC32MX7MMB_LED1_BIT (1 << PIC32MX_PIC32MX7MMB_LED1)
#define PIC32MX_PIC32MX7MMB_LED2_BIT (1 << PIC32MX_PIC32MX7MMB_LED2)
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 3 LEDs
* on board the Mikroelektronika PIC32MX7 MMB. The following definitions

4
nuttx/include/nuttx/spi.h
View File

@ -355,7 +355,9 @@ enum spi_dev_e
SPIDEV_ETHERNET, /* Select SPI ethernet device */
SPIDEV_DISPLAY, /* Select SPI LCD/OLED display device */
SPIDEV_WIRELESS, /* Select SPI Wireless device */
SPIDEV_TOUCHSCREEN /* Select SPI touchscreen device */
SPIDEV_TOUCHSCREEN, /* Select SPI touchscreen device */
SPIDEV_EXPANDER, /* Select SPI I/O expander device */
SPIDEV_MUX /* Select SPI multiplexer device */
};
/* Certain SPI devices may required differnt clocking modes */