forked from Archive/PX4-Autopilot
LPC43 Need to use fractional dividers to get the low-level UART BAUD correct
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4931 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
e78472258f
commit
a4426d194e
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@ -545,134 +545,6 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_setbaud
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*
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* Description:
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* Configure the U[S]ART divisors to accomplish the desired BAUD given the
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* U[S]ART base frequency.
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*
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* This computationally intensive algorithm is based on the same logic
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* used in the NXP sample code.
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*
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****************************************************************************/
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void up_setbaud(struct up_dev_s *priv)
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{
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uint32_t lcr; /* Line control register value */
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uint32_t dl; /* Best DLM/DLL full value */
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uint32_t mul; /* Best FDR MULVALL value */
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uint32_t divadd; /* Best FDR DIVADDVAL value */
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uint32_t best; /* Error value associated with best {dl, mul, divadd} */
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uint32_t cdl; /* Candidate DLM/DLL full value */
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uint32_t cmul; /* Candidate FDR MULVALL value */
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uint32_t cdivadd; /* Candidate FDR DIVADDVAL value */
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uint32_t errval; /* Error value associated with the candidate */
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/* The U[S]ART buad is given by:
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*
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* Fbaud = Fbase * mul / (mul + divadd) / (16 * dl)
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* dl = Fbase * mul / (mul + divadd) / Fbaud / 16
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* = Fbase * mul / ((mul + divadd) * Fbaud * 16)
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* = ((Fbase * mul) >> 4) / ((mul + divadd) * Fbaud)
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*
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* Where the value of MULVAL and DIVADDVAL comply with:
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*
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* 0 < mul < 16
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* 0 <= divadd < mul
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*/
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best = UINT32_MAX;
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divadd = 0;
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mul = 0;
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dl = 0;
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/* Try each mulitplier value in the valid range */
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for (cmul = 1 ; cmul < 16; cmul++)
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{
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/* Try each divider value in the valid range */
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for (cdivadd = 0 ; cdivadd < cmul ; cdivadd++)
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{
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/* Candidate:
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* dl = ((Fbase * mul) >> 4) / ((mul + cdivadd) * Fbaud)
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* (dl << 32) = (Fbase << 28) * cmul / ((mul + cdivadd) * Fbaud)
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*/
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uint64_t dl64 = ((uint64_t)priv->basefreq << 28) * cmul /
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((cmul + cdivadd) * priv->baud);
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/* The lower 32-bits of this value is the error */
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errval = (uint32_t)(dl64 & 0x00000000ffffffffull);
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/* The upper 32-bits is the candidate DL value */
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cdl = (uint32_t)(dl64 >> 32);
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/* Round up */
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if (errval > (1 << 31))
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{
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errval = -errval;
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cdl++;
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}
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/* Check if the resulting candidate DL value is within range */
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if (cdl < 1 || cdl > 65536)
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{
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/* No... try a different divadd value */
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continue;
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}
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/* Is this the best combination that we have seen so far? */
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if (errval < best)
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{
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/* Yes.. then the candidate is out best guess so far */
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best = errval;
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dl = cdl;
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divadd = cdivadd;
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mul = cmul;
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/* If the new best guess is exact (within our precision), then
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* we are finished.
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*/
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if (best == 0)
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{
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break;
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}
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}
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}
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}
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DEBUGASSERT(dl > 0);
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/* Enter DLAB=1 */
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lcr = up_serialin(priv, LPC43_UART_LCR_OFFSET);
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up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr | UART_LCR_DLAB);
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/* Save then divider values */
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up_serialout(priv, LPC43_UART_DLM_OFFSET, dl >> 8);
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up_serialout(priv, LPC43_UART_DLL_OFFSET, dl & 0xff);
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/* Clear DLAB */
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up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr & ~UART_LCR_DLAB);
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/* Then save the fractional divider values */
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up_serialout(priv, LPC43_UART_FDR_OFFSET,
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(mul << UART_FDR_MULVAL_SHIFT) | (divadd << UART_FDR_DIVADDVAL_SHIFT));
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}
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/****************************************************************************
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* Name: up_setup
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*
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@ -733,7 +605,7 @@ static int up_setup(struct uart_dev_s *dev)
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/* Set the BAUD divisor */
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up_setbaud(priv);
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lpc43_setbaud(priv->uartbase, priv->basefreq, priv->baud);
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/* Configure the FIFOs */
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@ -70,21 +70,21 @@
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# define CONSOLE_2STOP CONFIG_USART0_2STOP
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC43_UART1_BASE
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# define CONSOLE_BASEFREQ BOARD_USART0_BASEFREQ
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# define CONSOLE_BASEFREQ BOARD_UART1_BASEFREQ
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# define CONSOLE_BAUD CONFIG_UART1_BAUD
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# define CONSOLE_BITS CONFIG_UART1_BITS
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# define CONSOLE_PARITY CONFIG_UART1_PARITY
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# define CONSOLE_2STOP CONFIG_UART1_2STOP
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#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC43_USART2_BASE
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# define CONSOLE_BASEFREQ BOARD_USART0_BASEFREQ
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# define CONSOLE_BASEFREQ BOARD_USART2_BASEFREQ
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# define CONSOLE_BAUD CONFIG_USART2_BAUD
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# define CONSOLE_BITS CONFIG_USART2_BITS
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# define CONSOLE_PARITY CONFIG_USART2_PARITY
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# define CONSOLE_2STOP CONFIG_USART2_2STOP
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#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC43_USART3_BASE
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# define CONSOLE_BASEFREQ BOARD_USART0_BASEFREQ
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# define CONSOLE_BASEFREQ BOARD_USART3_BASEFREQ
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# define CONSOLE_BAUD CONFIG_USART3_BAUD
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# define CONSOLE_BITS CONFIG_USART3_BITS
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# define CONSOLE_PARITY CONFIG_USART3_PARITY
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@ -133,100 +133,11 @@
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/* LCR and FCR values for the console */
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#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
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#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | \
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CONSOLE_LCR_STOP)
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#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
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UART_FCR_RXRST | UART_FCR_FIFOEN)
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/* We cannot allow the DLM/DLL divisor to become to small or will will lose too
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* much accuracy. This following is a "fudge factor" that represents the minimum
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* value of the divisor that we will permit.
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*/
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#define UART_MINDL 32
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/* Select a CCLK divider to produce the UART BASEFREQ. The strategy is to select the
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* smallest divisor that results in an solution within range of the 16-bit
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* DLM and DLL divisor:
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*
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* BAUD = BASEFREQ / (16 * DL), or
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* DL = BASEFREQ / BAUD / 16
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*
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* Where:
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*
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* BASEFREQ = CCLK / divisor
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*
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* Ignoring the fractional divider for now (the console UART will be reconfigured
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* later in the boot sequencye, then the fractional dividers will be set properly).
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*
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* Check divisor == 1. This works if the upper limit is met
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*
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* DL < 0xffff, or
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* BASEFREQ / BAUD / 16 < 0xffff, or
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* CCLK / BAUD / 16 < 0xffff, or
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* CCLK < BAUD * 0xffff * 16
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* BAUD > CCLK / 0xffff / 16
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*
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* And the lower limit is met (we can't allow DL to get very close to one).
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*
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* DL >= MinDL
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* CCLK / BAUD / 16 >= MinDL, or
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* BAUD <= CCLK / 16 / MinDL
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*/
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#if CONSOLE_BAUD < (LPC43_CCLK / 16 / UART_MINDL)
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# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK
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# define CONSOLE_NUMERATOR (LPC43_CCLK)
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/* Check divisor == 2. This works if:
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*
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* 2 * CCLK / BAUD / 16 < 0xffff, or
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* BAUD > CCLK / 0xffff / 8
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*
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* And
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*
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* 2 * CCLK / BAUD / 16 >= MinDL, or
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* BAUD <= CCLK / 8 / MinDL
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*/
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#elif CONSOLE_BAUD < (LPC43_CCLK / 8 / UART_MINDL)
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# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK2
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# define CONSOLE_NUMERATOR (LPC43_CCLK / 2)
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/* Check divisor == 4. This works if:
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*
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* 4 * CCLK / BAUD / 16 < 0xffff, or
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* BAUD > CCLK / 0xffff / 4
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*
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* And
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*
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* 4 * CCLK / BAUD / 16 >= MinDL, or
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* BAUD <= CCLK / 4 / MinDL
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*/
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#elif CONSOLE_BAUD < (LPC43_CCLK / 4 / UART_MINDL)
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# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK4
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# define CONSOLE_NUMERATOR (LPC43_CCLK / 4)
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/* Check divisor == 8. This works if:
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*
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* 8 * CCLK / BAUD / 16 < 0xffff, or
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* BAUD > CCLK / 0xffff / 2
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*
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* And
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*
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* 8 * CCLK / BAUD / 16 >= MinDL, or
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* BAUD <= CCLK / 2 / MinDL
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*/
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#else /* if CONSOLE_BAUD < (LPC43_CCLK / 2 / UART_MINDL) */
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# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK8
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# define CONSOLE_NUMERATOR (LPC43_CCLK / 8)
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#endif
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/* Then this is the value to use for the DLM and DLL registers */
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#define CONSOLE_DL (CONSOLE_NUMERATOR / (CONSOLE_BAUD << 4))
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/**************************************************************************
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* Private Types
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**************************************************************************/
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@ -331,18 +242,13 @@ void lpc43_lowsetup(void)
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putreg32(UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8, CONSOLE_BASE+LPC43_UART_FCR_OFFSET);
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/* Set up the LCR and set DLAB=1 */
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/* Set up the LCR */
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putreg32(CONSOLE_LCR_VALUE|UART_LCR_DLAB, CONSOLE_BASE+LPC43_UART_LCR_OFFSET);
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putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+LPC43_UART_LCR_OFFSET);
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/* Set the BAUD divisor */
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putreg32(CONSOLE_DL >> 8, CONSOLE_BASE+LPC43_UART_DLM_OFFSET);
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putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE+LPC43_UART_DLL_OFFSET);
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/* Clear DLAB */
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putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+LPC43_UART_LCR_OFFSET);
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lpc43_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD);
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/* Configure the FIFOs */
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@ -528,3 +434,132 @@ void lpc43_usart3_setup(void)
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irqrestore(flags);
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};
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#endif
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/****************************************************************************
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* Name: lpc43_setbaud
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*
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* Description:
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* Configure the U[S]ART divisors to accomplish the desired BAUD given the
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* U[S]ART base frequency.
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*
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* This computationally intensive algorithm is based on the same logic
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* used in the NXP sample code.
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*
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****************************************************************************/
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void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
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{
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uint32_t lcr; /* Line control register value */
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uint32_t dl; /* Best DLM/DLL full value */
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uint32_t mul; /* Best FDR MULVALL value */
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uint32_t divadd; /* Best FDR DIVADDVAL value */
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uint32_t best; /* Error value associated with best {dl, mul, divadd} */
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uint32_t cdl; /* Candidate DLM/DLL full value */
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uint32_t cmul; /* Candidate FDR MULVALL value */
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uint32_t cdivadd; /* Candidate FDR DIVADDVAL value */
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uint32_t errval; /* Error value associated with the candidate */
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/* The U[S]ART buad is given by:
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*
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* Fbaud = Fbase * mul / (mul + divadd) / (16 * dl)
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* dl = Fbase * mul / (mul + divadd) / Fbaud / 16
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* = Fbase * mul / ((mul + divadd) * Fbaud * 16)
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* = ((Fbase * mul) >> 4) / ((mul + divadd) * Fbaud)
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*
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* Where the value of MULVAL and DIVADDVAL comply with:
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*
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* 0 < mul < 16
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* 0 <= divadd < mul
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*/
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best = UINT32_MAX;
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divadd = 0;
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mul = 0;
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dl = 0;
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/* Try each mulitplier value in the valid range */
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for (cmul = 1 ; cmul < 16; cmul++)
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{
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/* Try each divider value in the valid range */
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for (cdivadd = 0 ; cdivadd < cmul ; cdivadd++)
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{
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/* Candidate:
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* dl = ((Fbase * mul) >> 4) / ((mul + cdivadd) * Fbaud)
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* (dl << 32) = (Fbase << 28) * cmul / ((mul + cdivadd) * Fbaud)
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*/
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uint64_t dl64 = ((uint64_t)basefreq << 28) * cmul /
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((cmul + cdivadd) * baud);
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/* The lower 32-bits of this value is the error */
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errval = (uint32_t)(dl64 & 0x00000000ffffffffull);
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/* The upper 32-bits is the candidate DL value */
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cdl = (uint32_t)(dl64 >> 32);
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/* Round up */
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if (errval > (1 << 31))
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{
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errval = -errval;
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cdl++;
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}
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/* Check if the resulting candidate DL value is within range */
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if (cdl < 1 || cdl > 65536)
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{
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/* No... try a different divadd value */
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continue;
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}
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/* Is this the best combination that we have seen so far? */
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if (errval < best)
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{
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/* Yes.. then the candidate is out best guess so far */
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best = errval;
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dl = cdl;
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divadd = cdivadd;
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mul = cmul;
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/* If the new best guess is exact (within our precision), then
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* we are finished.
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*/
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if (best == 0)
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{
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break;
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}
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}
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}
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}
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DEBUGASSERT(dl > 0);
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/* Enter DLAB=1 */
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lcr = getreg32(uartbase + LPC43_UART_LCR_OFFSET);
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putreg32(lcr | UART_LCR_DLAB, uartbase + LPC43_UART_LCR_OFFSET);
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/* Save then divider values */
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putreg32(dl >> 8, uartbase + LPC43_UART_DLM_OFFSET);
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putreg32(dl & 0xff, uartbase + LPC43_UART_DLL_OFFSET);
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/* Clear DLAB */
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putreg32(lcr & ~UART_LCR_DLAB, uartbase + LPC43_UART_LCR_OFFSET);
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/* Then save the fractional divider values */
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putreg32((mul << UART_FDR_MULVAL_SHIFT) | (divadd << UART_FDR_DIVADDVAL_SHIFT),
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uartbase + LPC43_UART_FDR_OFFSET);
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}
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@ -133,6 +133,20 @@ EXTERN void lpc43_usart2_setup(void);
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EXTERN void lpc43_usart3_setup(void);
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#endif
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/****************************************************************************
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* Name: lpc43_setbaud
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*
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* Description:
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* Configure the U[S]ART divisors to accomplish the desired BAUD given the
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* U[S]ART base frequency.
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*
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* This computationally intensive algorithm is based on the same logic
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* used in the NXP sample code.
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*
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****************************************************************************/
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EXTERN void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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@ -806,11 +806,12 @@ Where <subdir> is one of the following:
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ostest:
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------
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This configuration directory, performs a simple OS test using
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This configuration of this directory performs a simple OS test using
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examples/ostest. By default, this project assumes that you are
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using the DFU bootloader.
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executing directly from SRAM.
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CONFIG_LPC43_CODESOURCERYW=y : CodeSourcery under Windows
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CONFIG_BOOT_SRAM=y : Executing in SRAM
|
||||
CONFIG_LPC32_CODEREDW=y : Code Red under Windows
|
||||
|
||||
This configuration directory, performs a simple test of the USB host
|
||||
HID keyboard class driver using the test logic in examples/hidkbd.
|
||||
|
|
@ -843,3 +844,11 @@ Where <subdir> is one of the following:
|
|||
|
||||
+CONFIG_EXAMPLES_OSTEST_FPUSIZE=(4*33)
|
||||
|
||||
nsh:
|
||||
----
|
||||
This configuration is the NuttShell (NSH) example at examples/nsh/
|
||||
examples/ostest. By default, this project assumes that you are
|
||||
executing directly from SRAM.
|
||||
|
||||
CONFIG_BOOT_SRAM=y : Executing in SRAM
|
||||
CONFIG_LPC32_CODEREDW=y : Code Red under Windows
|
||||
|
|
|
|||
Loading…
Reference in New Issue