From a00441ecf43c207a581b247e9e21c1cbda0a6592 Mon Sep 17 00:00:00 2001 From: Simone Guscetti Date: Fri, 19 May 2017 11:50:39 +0200 Subject: [PATCH] fmu-v5 timer_config: timer io channels for FMU_CH7/8 --- .../boards/px4fmu-v5/px4fmu_timer_config.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/drivers/boards/px4fmu-v5/px4fmu_timer_config.c b/src/drivers/boards/px4fmu-v5/px4fmu_timer_config.c index 9841a5885f..0899f758f0 100644 --- a/src/drivers/boards/px4fmu-v5/px4fmu_timer_config.c +++ b/src/drivers/boards/px4fmu-v5/px4fmu_timer_config.c @@ -154,6 +154,22 @@ __EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = { .timer_channel = 3, .ccr_offset = STM32_GTIM_CCR3_OFFSET, .masks = GTIM_SR_CC3IF | GTIM_SR_CC3OF + }, + { + .gpio_out = GPIO_TIM12_CH1OUT, + .gpio_in = GPIO_TIM12_CH1IN, + .timer_index = 2, + .timer_channel = 1, + .ccr_offset = STM32_GTIM_CCR1_OFFSET, // TODO: need revision + .masks = GTIM_SR_CC1IF | GTIM_SR_CC1OF // TODO: need revision + }, + { + .gpio_out = GPIO_TIM12_CH2OUT, + .gpio_in = GPIO_TIM12_CH2IN, + .timer_index = 2, + .timer_channel = 2, + .ccr_offset = STM32_GTIM_CCR2_OFFSET, // TODO: need revision + .masks = GTIM_SR_CC2IF | GTIM_SR_CC2OF // TODO: need revision } };