forked from Archive/PX4-Autopilot
STM32 Kconfig looks good. STM32 external ram configuration changed.
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@5100 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
parent
2cdd7e7425
commit
97da506c0c
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@ -3263,4 +3263,8 @@
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* Kconfig: Refactor serial settings (moved from chip to drivers/serial).
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AVR "teensy" now builds with Kconfig (contributed by Richard Cochran).
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* Kconfig: Add configuration settings for the LPC17xx
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* Kconfig: Add configuratino settings for the LM3S (from Richard Cochran).
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* Kconfig: Add configuration settings for the LM3S (from Richard Cochran).
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* Kconfig: Verify configuration settings for the STM32. This include
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changes in the way that the external SRAM is configured: Define
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CONFIG_HEAP2_SIZE (decimal) instead of CONFIG_HEAP2_END (hex).
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@ -58,11 +58,13 @@ config ARCH_X86
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config ARCH_Z16
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bool "ZNEO"
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select ARCH_HAVE_HEAP2
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---help---
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ZiLOG ZNEO 16-bit architectures (z16f).
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config ARCH_Z80
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bool "z80"
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select ARCH_HAVE_HEAP2
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---help---
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ZiLOG 8-bit architectures (z80, ez80, z8).
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@ -17,6 +17,7 @@ config ARCH_CHIP_C5471
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config ARCH_CHIP_CALYPSO
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bool "Calypso"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_HEAP2
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---help---
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TI Calypso-based cell phones (ARM7TDMI)
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@ -29,6 +30,7 @@ config ARCH_CHIP_DM320
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config ARCH_CHIP_IMX
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bool "Freescale iMX"
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select ARCH_ARM920T
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select ARCH_HAVE_HEAP2
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---help---
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Freescale iMX architectures (ARM920T)
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@ -37,6 +37,10 @@
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/mm.h>
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@ -52,6 +56,14 @@
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#include "up_arch.h"
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#include "up_internal.h"
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/****************************************************************************
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* Preprocessor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_addregion
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*
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@ -84,7 +96,7 @@ void up_addregion(void)
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/* Configure the RHEA bridge with some sane default values */
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calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0);
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mm_addregion((FAR void*)CONFIG_HEAP2_START, CONFIG_HEAP2_END-CONFIG_HEAP2_START);
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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}
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#endif
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@ -111,8 +111,8 @@ void up_addregion(void)
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/* Check for any additional memory regions */
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#if defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_END)
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_END - CONFIG_HEAP2_BASE);
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#if defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_SIZE)
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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#endif
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}
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#endif
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@ -84,7 +84,42 @@ config STM32_STM32F20XX
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config STM32_STM32F40XX
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bool
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default y if ARCH_CHIP_STM32F405RG || ARCH_CHIP_STM32F405VG || ARCH_CHIP_STM32F405ZG || ARCH_CHIP_STM32F407VE || ARCH_CHIP_STM32F407VG || ARCH_CHIP_STM32F407ZE || ARCH_CHIP_STM32F407ZG || ARCH_CHIP_STM32F407IE || ARCH_CHIP_STM32F407IE
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default y if ARCH_CHIP_STM32F405RG || ARCH_CHIP_STM32F405VG || ARCH_CHIP_STM32F405ZG || ARCH_CHIP_STM32F407VE || ARCH_CHIP_STM32F407VG || ARCH_CHIP_STM32F407ZE || ARCH_CHIP_STM32F407ZG || ARCH_CHIP_STM32F407IE || ARCH_CHIP_STM32F407IG
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choice
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prompt "Toolchain Selection"
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default STM32_CODESOURCERYW
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depends on ARCH_CHIP_STM32
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config STM32_CODESOURCERYW
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bool "CodeSourcery for Windows"
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config STM32_CODESOURCERYL
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bool "CodeSourcery for Linux"
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config STM32_ATOLLIC_LITE
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bool "Atollic Lite for Windows"
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config STM32_ATOLLIC_PRO
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bool "Atollic Pro for Windows"
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config STM32_DEVKITARM
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bool "DevkitARM (Windows)"
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config STM32_RAISONANCE
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bool "STMicro Raisonance for Windows"
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config STM32_BUILDROOT
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bool "NuttX buildroot (Cygwin or Linux)"
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endchoice
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config STM32_DFU
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bool "DFU bootloader"
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default n
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---help---
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Configure and position code for use with the STMicro DFU bootloader. Do
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not select this option if you will load code using JTAG/SWM.
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menu "STM32 Peripheral Support"
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@ -228,7 +263,7 @@ config STM32_SPI4
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config STM32_SYSCFG
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bool "SYSCFG"
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default n
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default y
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depends on STM32_STM32F20XX || STM32_STM32F40XX
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config STM32_TIM1
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@ -517,24 +552,11 @@ config STM32_CCMEXCLUDE
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config STM32_FSMC_SRAM
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bool "External SRAM on FSMC"
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default n
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depends on FSMC
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depends on STM32_FSMC
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select ARCH_HAVE_HEAP2
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---help---
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In addition to internal SRAM, SRAM may also be available through the FSMC.
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config HEAP2_BASE
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hex "FSMC SRAM base address"
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default 0x00000000
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depends on STM32_FSMC_SRAM
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---help---
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The base address of the SRAM in the FSMC address space.
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config HEAP2_END
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hex "FSMC SRAM end+1 address"
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default 0x00000000
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depends on STM32_FSMC_SRAM
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---help---
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The end (+1) of the SRAM in the FSMC address space
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config STM32_TIM1_PWM
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bool "TIM1 PWM"
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default n
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@ -1536,6 +1558,7 @@ config STM32_PHYADDR
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config STM32_MII
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bool "Use MII interface"
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default n
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depends on STM32_ETHMAC
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---help---
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Support Ethernet MII interface.
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@ -1549,13 +1572,14 @@ config STM32_MII_MCO2
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config STM32_AUTONEG
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bool "Use autonegtiation"
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default y
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depends on STM32_ETHMAC
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---help---
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Use PHY autonegotion to determine speed and mode
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config STM32_ETHFD
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bool "Full duplex"
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default n
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depends on !STM32_AUTONEG
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depends on STM32_ETHMAC && !STM32_AUTONEG
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---help---
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If STM32_AUTONEG is not defined, then this may be defined to select full duplex
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mode. Default: half-duplex
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@ -1563,7 +1587,7 @@ config STM32_ETHFD
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config STM32_ETH100MBPS
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bool "100 Mbps"
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default n
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depends on !STM32_AUTONEG
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depends on STM32_ETHMAC && !STM32_AUTONEG
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---help---
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If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps
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speed. Default: 10 Mbps
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@ -1607,6 +1631,7 @@ config STM32_PHYSR_FULLDUPLEX
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config STM32_ETH_PTP
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bool "Precision Time Protocol (PTP)"
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default n
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depends on STM32_ETHMAC
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---help---
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Precision Time Protocol (PTP). Not supported but some hooks are indicated
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with this condition.
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@ -1616,6 +1641,7 @@ endmenu
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config STM32_RMII
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bool
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default y if !STM32_MII
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depends on STM32_ETHMAC
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config STM32_MII_MCO1
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bool
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@ -73,13 +73,14 @@
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*
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* CONFIG_STM32_FSMC=y : Enables the FSMC
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* CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the
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* FSMC (as opposed to an LCD or FLASH).
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* FSMC (as opposed to an LCD or FLASH).
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* CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
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* address space
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* CONFIG_HEAP2_END : The end (+1) of the SRAM in the FSMC
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* address space
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* address space
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* CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
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* address space
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* CONFIG_MM_REGIONS : Must be set to a large enough value to
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* include the FSMC SRAM (as determined by the rules provided below)
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* include the FSMC SRAM (as determined by
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* the rules provided below)
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*/
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#ifndef CONFIG_STM32_FSMC
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/* If FSMC SRAM is going to be used as heap, then verify that the starting
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* address and size of the external SRAM region has been provided in the
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* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_END).
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* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
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*/
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#ifdef CONFIG_STM32_FSMC_SRAM
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# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_END)
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# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_END must be provided"
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# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
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# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
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# undef CONFIG_STM32_FSMC_SRAM
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# endif
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#endif
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/* Add the external FSMC SRAM heap region. */
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#ifdef CONFIG_STM32_FSMC_SRAM
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_END - CONFIG_HEAP2_BASE);
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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#endif
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}
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#endif
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@ -107,6 +107,6 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
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#if CONFIG_MM_REGIONS > 1
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void up_addregion(void)
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{
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_END - CONFIG_HEAP2_BASE);
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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}
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#endif
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@ -109,6 +109,6 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
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#if CONFIG_MM_REGIONS > 1
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void up_addregion(void)
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{
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_END - CONFIG_HEAP2_BASE);
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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}
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#endif
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@ -45,8 +45,8 @@ CONFIG_ARCH_BOARD_COMPALE99=y
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CONFIG_BOARD_LOOPSPERMSEC=1250
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CONFIG_ROM_VECTORS=n
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CONFIG_MM_REGIONS=2
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CONFIG_HEAP2_START=0x01000000
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CONFIG_HEAP2_END=0x01200000
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CONFIG_HEAP2_BASE=0x01000000
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CONFIG_HEAP2_SIZE=2097152
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CONFIG_ARCH_LEDS=n
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CONFIG_ARCH_INTERRUPTSTACK=1024
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CONFIG_ARCH_STACKDUMP=y
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@ -45,8 +45,8 @@ CONFIG_ARCH_BOARD_COMPALE99=y
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CONFIG_BOARD_LOOPSPERMSEC=1250
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CONFIG_ROM_VECTORS=n
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CONFIG_MM_REGIONS=2
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CONFIG_HEAP2_START=0x01000000
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CONFIG_HEAP2_END=0x01200000
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CONFIG_HEAP2_BASE=0x01000000
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CONFIG_HEAP2_SIZE=2097152
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CONFIG_ARCH_LEDS=n
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CONFIG_ARCH_INTERRUPTSTACK=1024
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CONFIG_ARCH_STACKDUMP=y
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@ -155,14 +155,6 @@ CONFIG_USART3_2STOP=0
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CONFIG_UART4_2STOP=0
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CONFIG_UART5_2STOP=0
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#
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# STM32F103Z specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=y
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# General build options
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#
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@ -153,14 +153,6 @@ CONFIG_USART3_2STOP=0
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CONFIG_UART4_2STOP=0
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CONFIG_UART5_2STOP=0
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#
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# STM32F103V specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=n
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# General build options
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#
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@ -158,14 +158,6 @@ CONFIG_USART3_2STOP=0
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CONFIG_UART4_2STOP=0
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CONFIG_UART5_2STOP=0
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#
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# STM32F103Z specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=n
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# General build options
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#
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@ -153,14 +153,6 @@ CONFIG_USART3_2STOP=0
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CONFIG_UART4_2STOP=0
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CONFIG_UART5_2STOP=0
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#
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# STM32F103V specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=n
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# General build options
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#
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@ -157,14 +157,6 @@ CONFIG_USART3_2STOP=0
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CONFIG_UART4_2STOP=0
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CONFIG_UART5_2STOP=0
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#
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# STM32F103V specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=n
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# General build options
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#
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@ -155,14 +155,6 @@ CONFIG_USART3_2STOP=0
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CONFIG_UART4_2STOP=0
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CONFIG_UART5_2STOP=0
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#
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# STM32F103V specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=n
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# General build options
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#
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|
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@ -154,14 +154,6 @@ CONFIG_USART3_2STOP=0
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CONFIG_UART4_2STOP=0
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CONFIG_UART5_2STOP=0
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#
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# STM32F103V specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=n
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# General build options
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#
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@ -165,14 +165,6 @@ CONFIG_UART3_PARITY=0
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CONFIG_UART4_PARITY=0
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CONFIG_UART5_PARITY=0
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#
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# K40X256VLQ100 specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=n
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# General build options
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#
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|
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@ -183,14 +183,6 @@ CONFIG_USART3_2STOP=0
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CONFIG_UART4_2STOP=0
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CONFIG_UART5_2STOP=0
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#
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# STM32F103Z specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=n
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# STM3210E-EVAL specific LCD settings
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#
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|
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@ -185,14 +185,6 @@ CONFIG_USART3_2STOP=0
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CONFIG_UART4_2STOP=0
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CONFIG_UART5_2STOP=0
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#
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# STM32F103Z specific SSI device driver settings
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#
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CONFIG_SSI0_DISABLE=y
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CONFIG_SSI1_DISABLE=y
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CONFIG_SSI_POLLWAIT=y
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#CONFIG_SSI_TXLIMIT=4
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#
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# STM3210E-EVAL specific LCD settings
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#
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@ -362,7 +362,7 @@ The on-board SRAM can be configured by setting
|
|||
CONFIG_STM32_FSMC=y : Enables the FSMC
|
||||
CONFIG_STM32_FSMC_SRAM=y : Enable external SRAM support
|
||||
CONFIG_HEAP2_BASE=0x68000000 : SRAM will be located at 0x680000000
|
||||
CONFIG_HEAP2_END=(0x68000000+(1*1024*1024)) : The size of the SRAM is 1Mbyte
|
||||
CONFIG_HEAP2_SIZE=1048576 : The size of the SRAM is 1Mbyte
|
||||
CONFIG_MM_REGIONS=2 : There will be two memory regions
|
||||
: in the heap
|
||||
|
||||
|
|
|
@ -151,14 +151,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -162,14 +162,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=y
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -160,14 +160,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -160,14 +160,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -181,14 +181,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -160,14 +160,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -160,14 +160,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -160,14 +160,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -160,14 +160,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -161,14 +161,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -191,14 +191,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -161,14 +161,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -160,14 +160,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM3210E-EVAL specific LCD settings
|
||||
#
|
||||
|
|
|
@ -352,7 +352,7 @@ The on-board SRAM can be configured by setting
|
|||
CONFIG_STM32_FSMC=y
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=(0x64000000+(2*1024*1024))
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
CONFIG_MM_REGIONS=2
|
||||
|
||||
Configuration Options
|
||||
|
@ -368,7 +368,7 @@ NuttX configuration file:
|
|||
FSMC (as opposed to an LCD or FLASH).
|
||||
CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
|
||||
address space
|
||||
CONFIG_HEAP2_END : The end (+1) of the SRAM in the FSMC
|
||||
CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
|
||||
address space
|
||||
CONFIG_MM_REGIONS : Must be set to a large enough value to
|
||||
include the FSMC SRAM
|
||||
|
@ -475,9 +475,9 @@ STM3220G-EVAL-specific Configuration Options
|
|||
CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the
|
||||
FSMC (as opposed to an LCD or FLASH).
|
||||
|
||||
CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space
|
||||
CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
|
||||
|
||||
CONFIG_HEAP2_END - The end (+1) of the SRAM in the FSMC address space
|
||||
CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC address space (decimal)
|
||||
|
||||
CONFIG_ARCH_IRQPRIO - The STM3220xxx supports interrupt prioritization
|
||||
|
||||
|
|
|
@ -78,7 +78,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -183,14 +183,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F20xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F20xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -78,7 +78,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -183,14 +183,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F20xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F20xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -78,7 +78,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -183,14 +183,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F20xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F20xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -78,7 +78,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -183,14 +183,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F20xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F20xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -78,7 +78,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=n
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -183,14 +183,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F20xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F20xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -78,7 +78,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -183,14 +183,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F20xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F20xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -78,7 +78,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -183,14 +183,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F20xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F20xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -451,7 +451,7 @@ The on-board SRAM can be configured by setting
|
|||
CONFIG_STM32_FSMC=y
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=(0x64000000+(2*1024*1024))
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
CONFIG_MM_REGIONS=2 (or =3, see below)
|
||||
|
||||
Configuration Options
|
||||
|
@ -472,7 +472,7 @@ present in the NuttX configuration file:
|
|||
FSMC (as opposed to an LCD or FLASH).
|
||||
CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
|
||||
address space
|
||||
CONFIG_HEAP2_END : The end (+1) of the SRAM in the FSMC
|
||||
CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
|
||||
address space
|
||||
CONFIG_MM_REGIONS : Must be set to a large enough value to
|
||||
include the FSMC SRAM
|
||||
|
@ -591,9 +591,9 @@ STM3240G-EVAL-specific Configuration Options
|
|||
CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the
|
||||
FSMC (as opposed to an LCD or FLASH).
|
||||
|
||||
CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space
|
||||
CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
|
||||
|
||||
CONFIG_HEAP2_END - The end (+1) of the SRAM in the FSMC address space
|
||||
CONFIG_HEAP2_END - The size of the SRAM in the FSMC address space (decimal)
|
||||
|
||||
CONFIG_ARCH_IRQPRIO - The STM3240xxx supports interrupt prioritization
|
||||
|
||||
|
|
|
@ -83,7 +83,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -189,14 +189,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -83,7 +83,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -189,14 +189,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -83,7 +83,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -189,14 +189,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -84,7 +84,7 @@ CONFIG_STM32_CCMEXCLUDE=y
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -190,14 +190,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -83,7 +83,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -189,14 +189,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -83,7 +83,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=n
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -189,14 +189,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -83,7 +83,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -189,14 +189,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -83,7 +83,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -189,14 +189,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -83,7 +83,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=n
|
|||
#
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_HEAP2_BASE=0x64000000
|
||||
CONFIG_HEAP2_END=0x64200000
|
||||
CONFIG_HEAP2_SIZE=2097152
|
||||
|
||||
#
|
||||
# Individual subsystems can be enabled:
|
||||
|
@ -189,14 +189,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -445,13 +445,13 @@ present in the NuttX configuration file:
|
|||
|
||||
CONFIG_STM32_FSMC=y : Enables the FSMC
|
||||
CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the
|
||||
FSMC (as opposed to an LCD or FLASH).
|
||||
FSMC (as opposed to an LCD or FLASH).
|
||||
CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
|
||||
address space
|
||||
CONFIG_HEAP2_END : The end (+1) of the SRAM in the FSMC
|
||||
address space
|
||||
address space
|
||||
CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
|
||||
address space
|
||||
CONFIG_MM_REGIONS : Must be set to a large enough value to
|
||||
include the FSMC SRAM
|
||||
include the FSMC SRAM
|
||||
|
||||
SRAM Configurations
|
||||
-------------------
|
||||
|
@ -704,9 +704,9 @@ STM32F4Discovery-specific Configuration Options
|
|||
CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the
|
||||
FSMC (as opposed to an LCD or FLASH).
|
||||
|
||||
CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space
|
||||
CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
|
||||
|
||||
CONFIG_HEAP2_END - The end (+1) of the SRAM in the FSMC address space
|
||||
CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC address space (decimal)
|
||||
|
||||
CONFIG_ARCH_IRQPRIO - The STM32F4Discovery supports interrupt prioritization
|
||||
|
||||
|
|
|
@ -178,14 +178,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx specific CAN device driver settings
|
||||
#
|
||||
|
|
|
@ -164,14 +164,6 @@ CONFIG_UART3_PARITY=0
|
|||
CONFIG_UART4_PARITY=0
|
||||
CONFIG_UART5_PARITY=0
|
||||
|
||||
#
|
||||
# K40X256VLQ100 specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
|
|
@ -164,14 +164,6 @@ CONFIG_UART3_PARITY=0
|
|||
CONFIG_UART4_PARITY=0
|
||||
CONFIG_UART5_PARITY=0
|
||||
|
||||
#
|
||||
# K40X256VLQ100 specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=n
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
#
|
||||
# Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
|
||||
# Copyright (c) 2011 Uros Platise. All rights reserved.
|
||||
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
# Uros Platise <uros.platise@isotel.eu>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
|
@ -181,14 +181,6 @@ CONFIG_USART3_2STOP=0
|
|||
CONFIG_UART4_2STOP=0
|
||||
CONFIG_UART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
#
|
||||
CONFIG_SSI0_DISABLE=y
|
||||
CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# OS support for I2C
|
||||
#
|
||||
|
|
|
@ -3,15 +3,6 @@
|
|||
# see misc/tools/kconfig-language.txt.
|
||||
#
|
||||
|
||||
config MM_REGIONS
|
||||
int "Number of memory regions"
|
||||
default 1
|
||||
---help---
|
||||
If the architecture includes multiple, non-contiguous regions of
|
||||
memory to allocate from, this specifies the number of memory regions
|
||||
that the memory manager must handle and enables the API
|
||||
mm_addregion(start, end);
|
||||
|
||||
config MM_SMALL
|
||||
bool "Small memory model"
|
||||
default n
|
||||
|
@ -24,3 +15,30 @@ config MM_SMALL
|
|||
have internal SRAM of size less than or equal to 64Kb. In this case,
|
||||
CONFIG_MM_SMALL can be defined so that those MCUs will also benefit
|
||||
from the smaller, 16-bit-based allocation overhead.
|
||||
|
||||
config MM_REGIONS
|
||||
int "Number of memory regions"
|
||||
default 1
|
||||
---help---
|
||||
If the architecture includes multiple, non-contiguous regions of
|
||||
memory to allocate from, this specifies the number of memory regions
|
||||
that the memory manager must handle and enables the API
|
||||
mm_addregion(start, end);
|
||||
|
||||
config ARCH_HAVE_HEAP2
|
||||
bool
|
||||
|
||||
config HEAP2_BASE
|
||||
hex "Start address of second heap region"
|
||||
default 0x00000000
|
||||
depends on ARCH_HAVE_HEAP2
|
||||
---help---
|
||||
The base address of the second heap region.
|
||||
|
||||
config HEAP2_SIZE
|
||||
int "Size of the second heap region"
|
||||
default 0
|
||||
depends on ARCH_HAVE_HEAP2
|
||||
---help---
|
||||
The size of the second heap region.
|
||||
|
||||
|
|
Loading…
Reference in New Issue