forked from Archive/PX4-Autopilot
Fix LPC43xx clocking bugs; LPC43xx now runs at 204MHz
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4946 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
6cffd422b8
commit
919354a96a
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@ -2996,3 +2996,16 @@
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* fs/: More stylistic file clean-up.
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* mm/: More stylistic file clean-up.
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* drivers/ and drivers/serial/: More stylistic file clean-up.
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* arch/arm/src/lpc43xx/lpc43_clockconfig.c: Fix PLL1 bit manipulation logic.
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Critical bugfix! This would often cause the LPC43xx to fail to boot.
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* arch/arm/src/lpc43xx/lpc43_rgu.c: The soft reset logic called from the
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beginning of __start seems cause problems. A magic delay seems to improve
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the logic some. But I suspect that real fix is to get rid of all of the
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soft reset logic. This would also be a critical bugfix if I believed
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that it really fixed all of the issues.
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* arch/arm/src/lpc43xx/chip/lpc43_cgu.h: Fix a bit mask in the PLL1
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control register. Critical bugfix.
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* arch/arm/src/lpc43xx/lpc43_clockconfig.c and configs/lpc4330-xplorer/include/board.h:
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Implement PLL1 ramp-up logic; Now the LPC43xx is running at 204MHz.
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* configs/lpc4330-xplorer/*/defconfig: Re-calibrated delay loops using
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the 204MHz clock. The LPC43xx ripping rips!
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@ -309,8 +309,8 @@
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# define PLL1_CTRL_NSEL_DIV3 (2 << PLL1_CTRL_NSEL_SHIFT)
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# define PLL1_CTRL_NSEL_DIV4 (3 << PLL1_CTRL_NSEL_SHIFT)
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/* Bits 14-15: Reserved */
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#define PLL1_CTRL_MSEL_SHIFT (16) /* Bits 16-17: Feedback-divider division ratio M */
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#define PLL1_CTRL_MSEL_MASK (3 << PLL1_CTRL_MSEL_SHIFT)
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#define PLL1_CTRL_MSEL_SHIFT (16) /* Bits 16-23: Feedback-divider division ratio M */
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#define PLL1_CTRL_MSEL_MASK (0xff << PLL1_CTRL_MSEL_SHIFT)
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# define PLL1_CTRL_MSEL(n) (((n)-1) << PLL1_CTRL_MSEL_SHIFT) /* n=1..256 */
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#define PLL1_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
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#define PLL1_CTRL_CLKSEL_MASK (31 << PLL1_CTRL_CLKSEL_SHIFT)
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@ -54,7 +54,8 @@
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#define LOW_XTAL_FREQUENCY 15000000
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#define MAX_XTAL_FREQUENCY 25000000
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#define MAX_FCLKOUT_FREQUENCY 156000000
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#define MAX_FCLKOUT_FREQUENCY 204000000
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#define MAX_FCLKOUT_DIRECT 156000000
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#define MAX_FCCO_FRQUENCY 320000000
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/* Configuration ************************************************************/
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@ -74,7 +75,7 @@
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# error "BOARD_XTAL_FREQUENCY exceeds the maximum value"
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#endif
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#if !defined(BOARD_PLL1_DIRECT) && (BOARD_FCLKOUT_FREQUENCY > MAX_FCLKOUT_FREQUENCY)
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#if BOARD_FCLKOUT_FREQUENCY > MAX_FCLKOUT_FREQUENCY
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# error "BOARD_FCLKOUT_FREQUENCY exceed the maximum"
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#endif
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@ -84,16 +85,136 @@
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/* Convert the user-friendly definitions in board.h to register bit settings */
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#if BOARD_PLL_PSEL == 1
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
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#elif BOARD_PLL_PSEL == 2
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
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#elif BOARD_PLL_PSEL == 4
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
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#elif BOARD_PLL_PSEL == 8
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
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/* Check if we are using a RAMP */
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#undef PLL_RAMP
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#ifdef BOARD_PLL_RAMP_MSEL
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# define PLL_RAMP 1
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/* Get initial PLL values */
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# define INIT_MSEL_VALUE PLL1_CTRL_MSEL(1)
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# define INIT_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
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/* Pick the initial PSEL value (integer mode) */
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# ifndef BOARD_XTAL_FREQUENCY
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# error "BOARD_XTAL_FREQUENCY is not defined in board.h"
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# endif
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# if BOARD_XTAL_FREQUENCY >= MAX_FCLKOUT_DIRECT
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# error "BOARD_XTAL_FREQUENCY value is not supported"
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# endif
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# if (2 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
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# error "Impossible value for BOARD_XTAL_FREQUENCY"
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# elif (2 * 2 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
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# define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
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# elif (2 * 4 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
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# define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
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# elif (2 * 8 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
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# define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
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# else
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# define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
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# endif
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/* Select initial integer mode controls */
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# define INIT_PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | INIT_PSEL_VALUE | INIT_NSEL_VALUE | INIT_MSEL_VALUE)
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/* Select a value close to a 10 millisecond delay */
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# define XTAL_DELAY \
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(10 * BOARD_XTAL_FREQUENCY + (LPC43_CCLK - 1)) / LPC43_CCLK
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/* Check the ramp-up MSEL value */
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# if (BOARD_PLL_RAMP_MSEL > 0) && (BOARD_PLL_RAMP_MSEL < 256)
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# define RAMP_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_RAMP_MSEL)
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# else
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# error "Unsupported value of BOARD_PLL_RAMP_NSEL"
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# endif
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/* Check the ramp-up NSEL value */
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# ifndef BOARD_PLL_RAMP_NSEL
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# error "BOARD_PLL_RAMP_NSEL is not defined in board.h"
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# endif
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# if BOARD_PLL_RAMP_NSEL == 1
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# define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
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# elif BOARD_PLL_RAMP_NSEL == 2
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# define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV2
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# elif BOARD_PLL_RAMP_NSEL == 3
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# define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV3
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# elif BOARD_PLL_RAMP_NSEL == 4
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# define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV4
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# else
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# error "Unsupported value of BOARD_PLL_RAMP_NSEL"
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# endif
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/* Check for direct mode */
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# ifndef BOARD_RAMP_FCLKOUT
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# error "BOARD_RAMP_FCLKOUT is not defined in board.h"
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# endif
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# if BOARD_RAMP_FCLKOUT >= MAX_FCLKOUT_DIRECT
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/* Select direct mode controls */
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# define RAMP_PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | RAMP_NSEL_VALUE | RAMP_MSEL_VALUE)
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# else
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/* Check the ramp-up PSEL value */
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# ifndef BOARD_PLL_RAMP_PSEL
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# error "BOARD_PLL_RAMP_PSEL is not defined in board.h"
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# endif
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# if BOARD_PLL_RAMP_PSEL == 1
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# define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
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# elif BOARD_PLL_RAMP_PSEL == 2
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# define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
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# elif BOARD_PLL_RAMP_PSEL == 4
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# define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
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# elif BOARD_PLL_RAMP_PSEL == 8
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# define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
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# else
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# error "Unsupported value of BOARD_PLL_RAMP_PSEL"
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# endif
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# endif
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/* Select integer mode controls */
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# define RAMP_PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | RAMP_PSEL_VALUE | RAMP_NSEL_VALUE | RAMP_MSEL_VALUE)
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/* Select a value close to a 10 millisecond delay */
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#endif
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/* Check the Final MSEL value */
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#ifndef BOARD_PLL_MSEL
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# error "BOARD_PLL_MSEL is not defined in board.h"
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#endif
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#if (BOARD_PLL_MSEL > 0) && (BOARD_PLL_MSEL < 256)
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# define CTRL_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_MSEL)
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#else
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# error "Unsupported value of BOARD_PLL_PSEL"
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# error "Unsupported value of BOARD_PLL_MSEL"
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#endif
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/* Check the Final NSEL value */
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#ifndef BOARD_PLL_NSEL
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# error "BOARD_PLL_NSEL is not defined in board.h"
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#endif
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#if BOARD_PLL_NSEL == 1
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@ -108,10 +229,44 @@
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# error "Unsupported value of BOARD_PLL_NSEL"
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#endif
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#if (BOARD_PLL_MSEL > 0) && (BOARD_PLL_MSEL < 256)
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# define CTRL_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_MSEL)
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#else
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# error "Unsupported value of BOARD_PLL_NSEL"
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/* Check for direct mode */
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#ifndef BOARD_FCLKOUT_FREQUENCY
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# error "BOARD_FCLKOUT_FREQUENCY is not defined in board.h"
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#endif
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#if BOARD_FCLKOUT_FREQUENCY >= MAX_FCLKOUT_DIRECT
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/* Select direct mode controls */
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# define PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | CTRL_NSEL_VALUE | CTRL_MSEL_VALUE)
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# else
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/* Check the Final PSEL value */
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# ifndef BOARD_PLL_PSEL
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# error "BOARD_PLL_PSEL is not defined in board.h"
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# endif
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# if BOARD_PLL_PSEL == 1
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
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# elif BOARD_PLL_PSEL == 2
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
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# elif BOARD_PLL_PSEL == 4
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
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# elif BOARD_PLL_PSEL == 8
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
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# else
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# error "Unsupported value of BOARD_PLL_PSEL"
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# endif
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/* Select integer mode controls */
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# define PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | CTRL_PSEL_VALUE | CTRL_NSEL_VALUE | CTRL_MSEL_VALUE)
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#endif
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/****************************************************************************
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@ -162,7 +317,7 @@ static inline void lpc43_xtalconfig(void)
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/* Select the crystal oscillator as the input to PLL1 */
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regval = getreg32(LPC43_PLL1_CTRL);
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regval = getreg32(LPC43_PLL1_CTRL);
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regval &= ~PLL1_CTRL_CLKSEL_MASK;
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regval |= PLL1_CLKSEL_XTAL | PLL1_CTRL_AUTOBLOCK;
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putreg32(regval, LPC43_PLL1_CTRL);
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@ -177,7 +332,7 @@ static inline void lpc43_xtalconfig(void)
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*
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****************************************************************************/
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static inline void lpc43_pll1config(void)
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static inline void lpc43_pll1config(uint32_t ctrlvalue)
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{
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uint32_t regval;
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@ -195,7 +350,6 @@ static inline void lpc43_pll1config(void)
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regval &= ~(PLL1_CTRL_BYPASS | PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT |
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PLL1_CTRL_PSEL_MASK | PLL1_CTRL_NSEL_MASK |
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PLL1_CTRL_MSEL_MASK);
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putreg32(regval, LPC43_PLL1_CTRL);
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/* Set selected PLL1 controls:
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*
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@ -206,13 +360,7 @@ static inline void lpc43_pll1config(void)
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* - PLL1_CTRL_MSEL: Set to the value from board.h
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*/
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#ifdef BOARD_PLL1_DIRECT
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regval |= (PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | CTRL_PSEL_VALUE |
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CTRL_NSEL_VALUE | CTRL_MSEL_VALUE);
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#else
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regval |= (PLL1_CTRL_FBSEL | CTRL_PSEL_VALUE | CTRL_NSEL_VALUE |
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CTRL_MSEL_VALUE);
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#endif
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regval |= ctrlvalue;
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putreg32(regval, LPC43_PLL1_CTRL);
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}
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@ -255,13 +403,13 @@ static inline void lpc43_pll1enable(void)
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*
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****************************************************************************/
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static inline void lpc43_m4clkselect(void)
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static inline void lpc43_m4clkselect(uint32_t clksel)
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{
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uint32_t regval;
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regval = getreg32(LPC43_BASE_M4_CLK);
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regval &= ~BASE_M4_CLK_CLKSEL_MASK;
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regval |= BASE_M4_CLKSEL_PLL1;
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regval |= clksel;
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putreg32(regval, LPC43_BASE_M4_CLK);
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}
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@ -285,15 +433,50 @@ void lpc43_clockconfig(void)
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lpc43_xtalconfig();
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#ifndef PLL_RAMP
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/* Configure PLL1 */
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lpc43_pll1config();
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lpc43_pll1config(PLL_CONTROLS);
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/* Enable PLL1 */
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lpc43_pll1enable();
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/* Set up PLL1 output as the M4 clock */
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lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
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#else
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/* Drive the M4 clock from the XTAL until the PLL is configured */
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lpc43_m4clkselect(BASE_M4_CLKSEL_XTAL);
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/* Select the initial PLL1 configured (BOARD_XTAL_FREQUENCY x 1) */
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lpc43_pll1config(INIT_PLL_CONTROLS);
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/* Enable PLL1 */
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lpc43_pll1enable();
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/* Delay around 10 milliseconds */
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up_mdelay(XTAL_DELAY);
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/* Configure the intermediate, ramp-up configuration for PLL1 */
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lpc43_pll1config(RAMP_PLL_CONTROLS);
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/* Set up PLL1 output as the M4 clock */
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lpc43_m4clkselect();
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lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
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/* Delay around 10 milliseconds */
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up_mdelay(XTAL_DELAY);
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/* Go to the final, full-speed PLL1 configuration */
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lpc43_pll1config(PLL_CONTROLS);
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#endif
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}
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@ -41,6 +41,7 @@
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <nuttx/arch.h>
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#include "nvic.h"
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#include "up_arch.h"
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@ -112,6 +113,10 @@ void lpc43_softreset(void)
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RGU_CTRL1_CAN0_RST | RGU_CTRL1_M0APP_RST),
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LPC43_RGU_CTRL1);
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/* A delay seems to be necessary somewhere around here */
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up_mdelay(20);
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/* Clear all pending interupts */
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putreg32(0xffffffff, NVIC_IRQ0_31_CLRPEND);
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@ -69,10 +69,6 @@
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#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency (Y1) */
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#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */
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/* TODO: The LPC43xx is capable of running at much higher frequencies, but requires
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* a ramp-up in several stages.
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*/
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/* Integer and direct modes are supported:
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*
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* In integer mode (Fclkout < 156000000):
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@ -85,12 +81,66 @@
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* Fcco = Fclkout
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*/
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#undef BOARD_PLL1_DIRECT /* Integer mode */
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#define BOARD_PLL_MSEL (6) /* Msel = 6 */
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#define BOARD_PLL_NSEL (1) /* Nsel = 1 */
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#define BOARD_PLL_PSEL (2) /* Psel = 2 */
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#define BOARD_FCLKOUT_FREQUENCY (72000000) /* 6 * 12,000,000 / 1 */
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#define BOARD_FCCO_FREQUENCY (244000000) /* 2 * 2 * 72,000,000 */
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#ifdef CONFIG_LPC43_72MHz
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/* NOTE: At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was
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* determined to be:
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*
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* CONFIG_BOARD_LOOPSPERMSEC=7191
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*
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* executing from SRAM.
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*/
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/* Final clocking (Integer mode with no ramp-up)
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*
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* Fclkout = 6 * 12MHz / 1 = 72MHz
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* Fcco = 2 * 2 * 72MHz = 216MHz
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*/
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# define BOARD_PLL_MSEL (6) /* Msel = 6 */
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# define BOARD_PLL_NSEL (1) /* Nsel = 1 */
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# define BOARD_PLL_PSEL (2) /* Psel = 2 */
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# define BOARD_FCLKOUT_FREQUENCY (72000000) /* 6 * 12,000,000 / 1 */
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# define BOARD_FCCO_FREQUENCY (244000000) /* 2 * 2 * Fclkout */
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#else
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/* NOTE: At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was
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* determined to be:
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*
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* CONFIG_BOARD_LOOPSPERMSEC=18535
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*
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* executing from SRAM.
|
||||
*/
|
||||
|
||||
/* Intermediate ramp-up clocking (Integer mode). If BOARD_PLL_RAMP_MSEL
|
||||
* is not defined, there will be no ramp-up.
|
||||
*
|
||||
* Fclkout = 9 * 12MHz / 1 = 108MHz
|
||||
* Fcco = 2 * 1 * 108MHz = 216MHz
|
||||
*/
|
||||
|
||||
# define BOARD_PLL_RAMP_MSEL (9) /* Msel = 9 */
|
||||
# define BOARD_PLL_RAMP_NSEL (1) /* Nsel = 1 */
|
||||
# define BOARD_PLL_RAMP_PSEL (1) /* Psel = 1 */
|
||||
|
||||
# define BOARD_RAMP_FCLKOUT (108000000) /* 9 * 12,000,000 / 1 */
|
||||
# define BOARD_RAMP_FCCO (216000000) /* 2 * 1 * Fclkout */
|
||||
|
||||
/* Final clocking (Direct mode).
|
||||
*
|
||||
* Fclkout = 17 * 12MHz / 1 = 204MHz
|
||||
* Fcco = Fclockout = 204MHz
|
||||
*/
|
||||
|
||||
# define BOARD_PLL_MSEL (17) /* Msel = 17 */
|
||||
# define BOARD_PLL_NSEL (1) /* Nsel = 1 */
|
||||
|
||||
# define BOARD_FCLKOUT_FREQUENCY (204000000) /* 17 * 12,000,000 / 1 */
|
||||
# define BOARD_FCCO_FREQUENCY (204000000) /* Fclockout */
|
||||
|
||||
#endif
|
||||
|
||||
/* This is the clock setup we configure for:
|
||||
*
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ CONFIG_ARCH_CHIP=lpc43xx
|
|||
CONFIG_ARCH_CHIP_LPC4330FET100=y
|
||||
CONFIG_ARCH_BOARD=lpc4330-xplorer
|
||||
CONFIG_ARCH_BOARD_LPC4330_XPLORER=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=7191
|
||||
CONFIG_BOARD_LOOPSPERMSEC=18535
|
||||
CONFIG_DRAM_SIZE=(72*1024)
|
||||
CONFIG_DRAM_START=0x10080000
|
||||
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ CONFIG_ARCH_CHIP=lpc43xx
|
|||
CONFIG_ARCH_CHIP_LPC4330FET100=y
|
||||
CONFIG_ARCH_BOARD=lpc4330-xplorer
|
||||
CONFIG_ARCH_BOARD_LPC4330_XPLORER=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=7191
|
||||
CONFIG_BOARD_LOOPSPERMSEC=18535
|
||||
CONFIG_DRAM_SIZE=(72*1024)
|
||||
CONFIG_DRAM_START=0x10080000
|
||||
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
|
||||
|
|
|
|||
Loading…
Reference in New Issue