From 8fbc664c2831ac700a0063fd2bf7752259701844 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 22 Dec 2011 22:50:41 +0000 Subject: [PATCH] PIC32, need to clear SW interrupt bit in CAUSE register git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4218 7fd9a85b-ad96-42d3-883c-3090e2eb8679 --- nuttx/arch/mips/src/mips32/up_swint0.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/nuttx/arch/mips/src/mips32/up_swint0.c b/nuttx/arch/mips/src/mips32/up_swint0.c index 443f81cfc2..6929d0b12c 100644 --- a/nuttx/arch/mips/src/mips32/up_swint0.c +++ b/nuttx/arch/mips/src/mips32/up_swint0.c @@ -45,9 +45,11 @@ #include #include -#include #include +#include +#include + #include "up_internal.h" /**************************************************************************** @@ -268,6 +270,7 @@ static inline void dispatch_syscall(uint32_t *regs) int up_swint0(int irq, FAR void *context) { uint32_t *regs = (uint32_t*)context; + uint32_t cause; DEBUGASSERT(regs && regs == current_regs); @@ -359,9 +362,15 @@ int up_swint0(int irq, FAR void *context) } #endif - /* Clear the pending software interrupt 0 */ + /* Clear the pending software interrupt 0 in the PIC32 interrupt block */ up_clrpend_irq(PIC32MX_IRQSRC_CS0); - + + /* And reset the software interrupt bit in the MIPS CAUSE register */ + + cause = cp0_getcause(); + cause &= ~CP0_CAUSE_IP0; + cp0_putcause(cause); + return OK; }