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PIC32, need to clear SW interrupt bit in CAUSE register 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4218 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2011-12-22 22:50:41 +00:00
parent 8953e3a370
commit 8fbc664c28
1 changed files with 12 additions and 3 deletions
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15
nuttx/arch/mips/src/mips32/up_swint0.c
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@ -45,9 +45,11 @@
#include <assert.h>
#include <debug.h>
#include <arch/irq.h>
#include <nuttx/sched.h>
#include <arch/irq.h>
#include <arch/mips32/cp0.h>
#include "up_internal.h"
/****************************************************************************
@ -268,6 +270,7 @@ static inline void dispatch_syscall(uint32_t *regs)
int up_swint0(int irq, FAR void *context)
{
uint32_t *regs = (uint32_t*)context;
uint32_t cause;
DEBUGASSERT(regs && regs == current_regs);
@ -359,9 +362,15 @@ int up_swint0(int irq, FAR void *context)
}
#endif
/* Clear the pending software interrupt 0 */
/* Clear the pending software interrupt 0 in the PIC32 interrupt block */
up_clrpend_irq(PIC32MX_IRQSRC_CS0);
/* And reset the software interrupt bit in the MIPS CAUSE register */
cause = cp0_getcause();
cause &= ~CP0_CAUSE_IP0;
cp0_putcause(cause);
return OK;
}