forked from Archive/PX4-Autopilot
Shenzhou schematic is wrong: LCD WR signal is on PB14, not PD14
git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5195 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -3415,4 +3415,6 @@
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configuration.
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* configs/shenzhou: Oops. The Shenzhou LCD is and SSD1289,
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not an ILI93xx.
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* configs/shenzhou/src/up_ssd1289.c: The LCD is basically functional
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on the Shenzhou board.
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@ -238,6 +238,8 @@ config DEBUG_ENABLE
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---help---
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Support an interface to dynamically enable or disable debug output.
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comment "Subsystem Debug Options"
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config DEBUG_SCHED
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bool "Enable Scheduler Debug Output"
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default n
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@ -288,6 +290,8 @@ config DEBUG_GRAPHICS
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---help---
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Enable NX graphics debug output (disabled by default)
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comment "Driver Debug Options"
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config DEBUG_LCD
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bool "Enable Low-level LCD Debug Output"
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default n
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@ -94,7 +94,7 @@ PN NAME SIGNAL NOTES
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MII_TXD0 Ethernet PHY
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52 PB13 I2S_CK Audio DAC
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MII_TXD1 Ethernet PHY
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53 PB14 SD_CD
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53 PB14 SD_CD There is confusion here. Schematic is wrong LCD_WR is PB14.
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54 PB15 I2S_DIN Audio DAC
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-- ---- -------------- -------------------------------------------------------------------
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@ -139,7 +139,7 @@ PN NAME SIGNAL NOTES
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58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
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59 PD12 WIRELESS_CS To the NRF24L01 2.4G wireless module
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60 PD13 LCD_RS To TFT LCD (CN13)
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61 PD14 LCD_WR To TFT LCD (CN13)
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61 PD14 LCD_WR To TFT LCD (CN13). Schematic is wrong LCD_WR is PB14.
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62 PD15 LCD_RD To TFT LCD (CN13)
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-- ---- -------------- -------------------------------------------------------------------
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@ -164,7 +164,7 @@
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* 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27)
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* 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
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* 60 PD13 LCD_RS To TFT LCD (CN13, pin 20)
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* 61 PD14 LCD_WR To TFT LCD (CN13, pin 21)
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* 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). Schematic is wrong LCD_WR is PB14.
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* 62 PD15 LCD_RD To TFT LCD (CN13, pin 22)
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* 97 PE0 DB00 To TFT LCD (CN13, pin 3)
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* 98 PE1 DB01 To TFT LCD (CN13, pin 4)
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@ -281,7 +281,7 @@
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#define GPIO_LCD_RD (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN15)
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#define GPIO_LCD_WR (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN14)
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GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN14)
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#define GPIO_LCD_LE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN2)
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@ -307,9 +307,9 @@
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#define LCD_RD_CLEAR LCD_BIT_CLEAR(STM32_GPIOD_OFFSET, 15) /* GPIO_PORTD|GPIO_PIN15 */
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#define LCD_RD_SET LCD_BIT_SET(STM32_GPIOD_OFFSET, 15)
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#define LCD_RD_READ LCD_BIT_READ(STM32_GPIOD_OFFSET, 15)
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#define LCD_WR_CLEAR LCD_BIT_CLEAR(STM32_GPIOD_OFFSET, 14) /* GPIO_PORTD|GPIO_PIN14 */
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#define LCD_WR_SET LCD_BIT_SET(STM32_GPIOD_OFFSET, 14)
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#define LCD_WR_READ LCD_BIT_READ(STM32_GPIOD_OFFSET, 14)
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#define LCD_WR_CLEAR LCD_BIT_CLEAR(STM32_GPIOB_OFFSET, 14) /* GPIO_PORTB|GPIO_PIN14 */
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#define LCD_WR_SET LCD_BIT_SET(STM32_GPIOB_OFFSET, 14)
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#define LCD_WR_READ LCD_BIT_READ(STM32_GPIOB_OFFSET, 14)
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#define LCD_LE_CLEAR LCD_BIT_CLEAR(STM32_GPIOB_OFFSET, 2) /* GPIO_PORTB|GPIO_PIN2 */
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#define LCD_LE_SET LCD_BIT_SET(STM32_GPIOB_OFFSET, 2)
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#define LCD_LE_READ LCD_BIT_READ(STM32_GPIOB_OFFSET, 2)
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@ -383,7 +383,7 @@
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 53 PB14 SD_CD Active low: Pulled high
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* 53 PB14 SD_CD Active low: Pulled high. Schematic is wrong LCD_WR is PB14.
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* 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
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*/
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@ -49,7 +49,7 @@
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* 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27)
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* 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
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* 60 PD13 LCD_RS To TFT LCD (CN13, pin 20)
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* 61 PD14 LCD_WR To TFT LCD (CN13, pin 21)
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* 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). Schematic is wrong LCD_WR is PB14.
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* 62 PD15 LCD_RD To TFT LCD (CN13, pin 22)
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* 97 PE0 DB00 To TFT LCD (CN13, pin 3)
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* 98 PE1 DB01 To TFT LCD (CN13, pin 4)
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@ -160,7 +160,7 @@ static void stm32_lcdoutput(FAR struct stm32_lower_s *priv);
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* 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27)
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* 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
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* 60 PD13 LCD_RS To TFT LCD (CN13, pin 20)
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* 61 PD14 LCD_WR To TFT LCD (CN13, pin 21)
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* 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). Schematic is wrong LCD_WR is PB14.
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* 62 PD15 LCD_RD To TFT LCD (CN13, pin 22)
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* 97 PE0 DB00 To TFT LCD (CN13, pin 3)
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* 98 PE1 DB01 To TFT LCD (CN13, pin 4)
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@ -312,6 +312,9 @@ static void stm32_wrdata(FAR struct stm32_lower_s *priv, uint16_t data)
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putreg32(1, LCD_WR_CLEAR);
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putreg32((uint32_t)data, LCD_ODR);
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/* Total WR pulse with should be 50ns wide. */
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putreg32(1, LCD_WR_SET);
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}
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@ -326,6 +329,8 @@ static void stm32_wrdata(FAR struct stm32_lower_s *priv, uint16_t data)
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#ifndef CONFIG_SSD1289_WRONLY
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static inline uint16_t stm32_rddata(FAR struct stm32_lower_s *priv)
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{
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uint16_t regval;
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/* Make sure D0-D15 are configured as inputs */
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stm32_lcdinput(priv);
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@ -333,8 +338,13 @@ static inline uint16_t stm32_rddata(FAR struct stm32_lower_s *priv)
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/* Toggle the RD line to latch the 16-bit LCD data */
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putreg32(1, LCD_RD_CLEAR);
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/* Data should appear 250ns after RD. Total RD pulse width should be 500nS */
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__asm__ __volatile__(" nop\n nop\n nop\n nop\n");
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regval = (uint16_t)getreg32(LCD_IDR);
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putreg32(1, LCD_RD_SET);
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return (uint16_t)getreg32(LCD_IDR);
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return regval;
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}
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#endif
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