forked from Archive/PX4-Autopilot
Update to the STM3240G-EVAL LCD driver
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4652 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
cf9b822df7
commit
823d7a394a
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@ -34,21 +34,10 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************************/
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/* This driver supports the following LCDs:
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/* This driver supports the following LCDs on the STM324xG_EVAL board:
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*
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* 1. Ampire AM-240320LTNQW00H
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* 2. Orise Tech SPFD5408B
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* 3. RenesasSP R61580
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*
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* The driver dynamically selects the LCD based on the reported LCD ID value. However,
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* code size can be reduced by suppressing support for individual LCDs using:
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*
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* CONFIG_STM32_AM240320_DISABLE
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* CONFIG_STM32_SPFD5408B_DISABLE
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* CONFIG_STM32_R61580_DISABLE
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*
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* Omitting the above (or setting them to "n") enables support for the LCD. Setting
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* any of the above to "y" will disable support for the corresponding LCD.
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* AM-240320L8TNQW00H (LCD_ILI9320) and
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* AM-240320D5TOQW01H (LCD_ILI9325)
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*/
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/**************************************************************************************
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@ -79,6 +68,12 @@
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* Pre-processor Definitions
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**************************************************************************************/
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/* Configuration **********************************************************************/
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/* CONFIG_STM32_ILI9320_DISABLE may be defined to disabled the AM-240320L8TNQW00H
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* (LCD_ILI9320)
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* CONFIG_STM32_ILI9325_DISABLE may be defined to disabled the AM-240320D5TOQW01H
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* (LCD_ILI9325)
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*/
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/* Check contrast selection */
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#if !defined(CONFIG_LCD_MAXCONTRAST)
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@ -143,17 +138,6 @@
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# define CONFIG_LCD_LANDSCAPE 1
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#endif
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/* When reading 16-bit gram data, there may some shifts in the returned data
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* and/or there may be some colors in the incorrect posisions:
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*
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* - SPFD5408B: There appears to be a 5-bit shift in the returned data.
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* Red and green appear to be swapped on read-back as well
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* - R61580: There is a 16-bit (1 pixel) shift in the returned data.
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* - AM240320: Unknown -- assume colors are correct for now.
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*/
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#define SPFD5408B_RDSHIFT 5
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/* Define CONFIG_DEBUG_LCD to enable detailed LCD debug output. Verbose debug must
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* also be enabled.
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*/
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@ -303,15 +287,17 @@
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/* LCD IDs */
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#define SPFD5408B_ID 0x5408
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#define R61580_ID 0x1580
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#define ILI9320_ID 0x9320
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#define ILI9325_ID 0x9325
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/* Debug ******************************************************************************/
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#ifdef CONFIG_DEBUG_LCD
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# define lcddbg(format, arg...) vdbg(format, ##arg)
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# define lcddbg dbg
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# define lcdvdbg vdbg
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#else
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# define lcddbg(x...)
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# define lcddbg(x...)
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# define lcdvdbg(x...)
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#endif
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/**************************************************************************************
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@ -323,9 +309,8 @@
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enum lcd_type_e
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{
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LCD_TYPE_UNKNOWN = 0,
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LCD_TYPE_SPFD5408B,
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LCD_TYPE_R61580,
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LCD_TYPE_AM240320
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LCD_TYPE_ILI9320,
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LCD_TYPE_ILI9325
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};
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/* This structure describes the LCD registers */
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@ -364,9 +349,7 @@ static uint16_t stm3240g_readreg(uint8_t regaddr);
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static inline void stm3240g_gramselect(void);
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static inline void stm3240g_writegram(uint16_t rgbval);
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static void stm3240g_readsetup(FAR uint16_t *accum);
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#ifndef CONFIG_STM32_AM240320_DISABLE
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static void stm3240g_readnosetup(FAR uint16_t *accum);
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#endif
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static uint16_t stm3240g_readshift(FAR uint16_t *accum);
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static uint16_t stm3240g_readnoshift(FAR uint16_t *accum);
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static void stm3240g_setcursor(uint16_t col, uint16_t row);
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@ -538,113 +521,33 @@ static inline void stm3240g_writegram(uint16_t rgbval)
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}
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/**************************************************************************************
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* Name: stm3240g_readsetup / stm3240g_readnosetup
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* Name: stm3240g_readnosetup
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*
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* Description:
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* Prime the operation by reading one pixel from the GRAM memory if necessary for
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* this LCD type. When reading 16-bit gram data, there may be some shifts in the
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* returned data:
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*
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* - SPFD5408B: There appears to be a 5-bit shift in the returned data.
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* - R61580: There is a 16-bit (1 pixel) shift in the returned data.
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* - AM240320: Unknown -- assuming no shift in the return data
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* - ILI932x: Unknown -- assuming no shift in the return data
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*
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**************************************************************************************/
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/* Used for SPFD5408B and R61580 */
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#if !defined(CONFIG_STM32_SPFD5408B_DISABLE) || !defined(CONFIG_STM32_R61580_DISABLE)
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static void stm3240g_readsetup(FAR uint16_t *accum)
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{
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/* Read-ahead one pixel */
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*accum = LCD->value;
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}
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#endif
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/* Used only for AM240320 */
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#ifndef CONFIG_STM32_AM240320_DISABLE
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static void stm3240g_readnosetup(FAR uint16_t *accum)
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{
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}
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#endif
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/**************************************************************************************
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* Name: stm3240g_readshift / stm3240g_readnoshift
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* Name: stm3240g_readnoshift
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*
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* Description:
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* Read one correctly aligned pixel from the GRAM memory. Possibly shifting the
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* data and possibly swapping red and green components.
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*
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* - SPFD5408B: There appears to be a 5-bit shift in the returned data.
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* Red and green appear to be swapped on read-back as well
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* - R61580: There is a 16-bit (1 pixel) shift in the returned data.
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* All colors in the normal order
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* - AM240320: Unknown -- assuming colors are in the color order
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* - ILI932x: Unknown -- assuming colors are in the color order
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*
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**************************************************************************************/
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/* This version is used only for the SPFD5408B. It shifts the data by 5-bits and swaps
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* red and green
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*/
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#ifndef CONFIG_STM32_SPFD5408B_DISABLE
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static uint16_t stm3240g_readshift(FAR uint16_t *accum)
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{
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uint16_t red;
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uint16_t green;
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uint16_t blue;
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/* Read the value (GRAM register already selected) */
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uint16_t next = LCD->value;
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/* Return previous bits 0-10 as bits 6-15 and next data bits 11-15 as bits 0-5
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*
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* xxxx xPPP PPPP PPPP
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* NNNN Nxxx xxxx xxxx
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*
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* Assuming that SPFD5408B_RDSHIFT == 5
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*/
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uint16_t value = *accum << SPFD5408B_RDSHIFT | next >> (16-SPFD5408B_RDSHIFT);
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/* Save the value for the next time we are called */
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*accum = next;
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/* Tear the RGB655 apart. Swap read and green */
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red = (value << (11-5)) & 0xf800; /* Move bits 5-9 to 11-15 */
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green = (value >> (10-5)) & 0x07e0; /* Move bits 10-15 to bits 5-10 */
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blue = value & 0x001f; /* Blue is in the right place */
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/* And put the RGB565 back together */
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value = red | green | blue;
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/* This is wierd... If blue is zero, then red+green values are off by 0x20.
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* Except that both 0x0000 and 0x0020 can map to 0x0000. Need to revisit
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* this!!!!!!!!!!! I might be misinterpreting some of the data that I have.
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*/
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#if 0 /* REVISIT */
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if (value != 0 && blue == 0)
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{
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value += 0x20;
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}
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#endif
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return value;
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}
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#endif
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/* This version is used for the R61580 and for the AM240320. It neither shifts nor
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* swaps colors.
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*/
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#if !defined(CONFIG_STM32_R61580_DISABLE) || !defined(CONFIG_STM32_AM240320_DISABLE)
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#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE)
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static uint16_t stm3240g_readnoshift(FAR uint16_t *accum)
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{
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/* Read the value (GRAM register already selected) */
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@ -720,7 +623,7 @@ static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu
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/* Buffer must be provided and aligned to a 16-bit address boundary */
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lcddbg("row: %d col: %d npixels: %d\n", row, col, npixels);
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lcdvdbg("row: %d col: %d npixels: %d\n", row, col, npixels);
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DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0);
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/* Write the run to GRAM. */
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@ -813,34 +716,25 @@ static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer,
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/* Buffer must be provided and aligned to a 16-bit address boundary */
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lcddbg("row: %d col: %d npixels: %d\n", row, col, npixels);
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lcdvdbg("row: %d col: %d npixels: %d\n", row, col, npixels);
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DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0);
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/* Configure according to the LCD type */
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switch (g_lcddev.type)
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{
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#ifndef CONFIG_STM32_SPFD5408B_DISABLE
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case LCD_TYPE_SPFD5408B:
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readsetup = stm3240g_readsetup;
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readgram = stm3240g_readshift;
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break;
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#endif
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#ifndef CONFIG_STM32_R61580_DISABLE
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case LCD_TYPE_R61580:
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readsetup = stm3240g_readsetup;
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readgram = stm3240g_readnoshift;
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break;
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#endif
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#ifndef CONFIG_STM32_AM240320_DISABLE
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case LCD_TYPE_AM240320:
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#if !defined(CONFIG_STM32_ILI9320_DISABLE)
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case LCD_TYPE_ILI9320:
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readsetup = stm3240g_readnosetup;
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readgram = stm3240g_readnoshift;
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break;
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#endif
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#if !defined(CONFIG_STM32_ILI9325_DISABLE)
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case LCD_TYPE_ILI9325:
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readsetup = stm3240g_readnosetup;
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readgram = stm3240g_readnoshift;
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break;
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#endif
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default: /* Shouldn't happen */
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return -ENOSYS;
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}
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@ -927,11 +821,11 @@ static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer,
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**************************************************************************************/
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static int stm3240g_getvideoinfo(FAR struct lcd_dev_s *dev,
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FAR struct fb_videoinfo_s *vinfo)
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FAR struct fb_videoinfo_s *vinfo)
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{
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DEBUGASSERT(dev && vinfo);
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gvdbg("fmt: %d xres: %d yres: %d nplanes: %d\n",
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g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, g_videoinfo.nplanes);
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lcdvdbg("fmt: %d xres: %d yres: %d nplanes: %d\n",
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g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, g_videoinfo.nplanes);
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memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s));
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return OK;
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}
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@ -948,7 +842,7 @@ static int stm3240g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno
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FAR struct lcd_planeinfo_s *pinfo)
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{
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DEBUGASSERT(dev && pinfo && planeno == 0);
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gvdbg("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp);
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lcdvdbg("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp);
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memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s));
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return OK;
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}
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@ -964,7 +858,7 @@ static int stm3240g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno
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static int stm3240g_getpower(struct lcd_dev_s *dev)
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{
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gvdbg("power: %d\n", 0);
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lcdvdbg("power: %d\n", 0);
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return g_lcddev.power;
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}
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@ -1016,7 +910,7 @@ static int stm3240g_poweroff(void)
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static int stm3240g_setpower(struct lcd_dev_s *dev, int power)
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{
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gvdbg("power: %d\n", power);
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lcdvdbg("power: %d\n", power);
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DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER);
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/* Set new power level */
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@ -1062,14 +956,8 @@ static int stm3240g_setpower(struct lcd_dev_s *dev, int power)
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#endif
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/* Then turn the display on */
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#ifndef CONFIG_STM32_AM240320_DISABLE
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# if !defined (CONFIG_STM32_SPFD5408B_DISABLE) || !defined(CONFIG_STM32_R61580_DISABLE)
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stm3240g_writereg(LCD_REG_7, g_lcddev.type == LCD_TYPE_AM240320 ? 0x0173 : 0x0112);
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# else
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#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE)
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stm3240g_writereg(LCD_REG_7, 0x0173);
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# endif
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#else
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stm3240g_writereg(LCD_REG_7, 0x0112);
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#endif
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g_lcddev.power = power;
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}
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@ -1093,7 +981,7 @@ static int stm3240g_setpower(struct lcd_dev_s *dev, int power)
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static int stm3240g_getcontrast(struct lcd_dev_s *dev)
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{
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gvdbg("Not implemented\n");
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lcdvdbg("Not implemented\n");
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return -ENOSYS;
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}
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@ -1107,7 +995,7 @@ static int stm3240g_getcontrast(struct lcd_dev_s *dev)
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static int stm3240g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast)
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{
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gvdbg("contrast: %d\n", contrast);
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lcdvdbg("contrast: %d\n", contrast);
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return -ENOSYS;
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}
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@ -1123,194 +1011,17 @@ static inline void stm3240g_lcdinitialize(void)
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{
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uint16_t id;
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/* Check if the LCD is Orise Tech SPFD5408B Controller (or the compatible RenesasSP
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* R61580).
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*/
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/* Check if the LCD is xxx Controller (or the compatible) */
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id = stm3240g_readreg(LCD_REG_0);
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lcddbg("LCD ID: %04x\n", id);
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/* Check if the ID is for the SPFD5408B */
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/* Check if the ID is for the STM32_ILI9320 & STM32_ILI9325 */
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#if !defined(CONFIG_STM32_SPFD5408B_DISABLE)
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if (id == SPFD5408B_ID)
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#if !defined(CONFIG_STM32_ILI9320_DISABLE)
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if (id == 0x9320)
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{
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/* Set the LCD type for the SPFD5408B */
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g_lcddev.type = LCD_TYPE_SPFD5408B;
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lcddbg("LCD type: %d\n", g_lcddev.type);
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/* Start Initial Sequence */
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stm3240g_writereg(LCD_REG_1, 0x0100); /* Set SS bit */
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stm3240g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */
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stm3240g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */
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stm3240g_writereg(LCD_REG_4, 0x0000); /* Resize register */
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stm3240g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */
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stm3240g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */
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stm3240g_writereg(LCD_REG_10, 0x0000); /* FMARK function */
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stm3240g_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */
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stm3240g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */
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stm3240g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */
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/* Power On sequence */
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stm3240g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
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stm3240g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
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stm3240g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
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stm3240g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
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up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */
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stm3240g_writereg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
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up_mdelay(50);
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stm3240g_writereg(LCD_REG_16, 0x12B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
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up_mdelay(50);
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stm3240g_writereg(LCD_REG_18, 0x01bd); /* External reference voltage= Vci */
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up_mdelay(50);
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|
||||
stm3240g_writereg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */
|
||||
stm3240g_writereg(LCD_REG_41, 0x000e); /* VCM[4:0] for VCOMH */
|
||||
up_mdelay(50);
|
||||
|
||||
stm3240g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
|
||||
stm3240g_writereg(LCD_REG_33, 0x013f); /* GRAM Vertical Address */
|
||||
|
||||
/* Adjust the Gamma Curve (SPFD5408B)*/
|
||||
|
||||
stm3240g_writereg(LCD_REG_48, 0x0b0d);
|
||||
stm3240g_writereg(LCD_REG_49, 0x1923);
|
||||
stm3240g_writereg(LCD_REG_50, 0x1c26);
|
||||
stm3240g_writereg(LCD_REG_51, 0x261c);
|
||||
stm3240g_writereg(LCD_REG_52, 0x2419);
|
||||
stm3240g_writereg(LCD_REG_53, 0x0d0b);
|
||||
stm3240g_writereg(LCD_REG_54, 0x1006);
|
||||
stm3240g_writereg(LCD_REG_55, 0x0610);
|
||||
stm3240g_writereg(LCD_REG_56, 0x0706);
|
||||
stm3240g_writereg(LCD_REG_57, 0x0304);
|
||||
stm3240g_writereg(LCD_REG_58, 0x0e05);
|
||||
stm3240g_writereg(LCD_REG_59, 0x0e01);
|
||||
stm3240g_writereg(LCD_REG_60, 0x010e);
|
||||
stm3240g_writereg(LCD_REG_61, 0x050e);
|
||||
stm3240g_writereg(LCD_REG_62, 0x0403);
|
||||
stm3240g_writereg(LCD_REG_63, 0x0607);
|
||||
|
||||
/* Set GRAM area */
|
||||
|
||||
stm3240g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
|
||||
stm3240g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */
|
||||
stm3240g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
|
||||
stm3240g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */
|
||||
stm3240g_writereg(LCD_REG_96, 0xa700); /* Gate Scan Line */
|
||||
stm3240g_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */
|
||||
stm3240g_writereg(LCD_REG_106, 0x0000); /* set scrolling line */
|
||||
|
||||
/* Partial Display Control */
|
||||
|
||||
stm3240g_writereg(LCD_REG_128, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_129, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_130, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_131, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_132, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_133, 0x0000);
|
||||
|
||||
/* Panel Control */
|
||||
|
||||
stm3240g_writereg(LCD_REG_144, 0x0010);
|
||||
stm3240g_writereg(LCD_REG_146, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_147, 0x0003);
|
||||
stm3240g_writereg(LCD_REG_149, 0x0110);
|
||||
stm3240g_writereg(LCD_REG_151, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_152, 0x0000);
|
||||
|
||||
/* Set GRAM write direction and BGR=1
|
||||
* I/D=01 (Horizontal : increment, Vertical : decrement)
|
||||
* AM=1 (address is updated in vertical writing direction)
|
||||
*/
|
||||
|
||||
stm3240g_writereg(LCD_REG_3, 0x1018);
|
||||
stm3240g_writereg(LCD_REG_7, 0); /* Display OFF */
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
/* Check if the ID is for the almost compatible R61580 */
|
||||
|
||||
#if !defined(CONFIG_STM32_R61580_DISABLE)
|
||||
if (id == R61580_ID)
|
||||
{
|
||||
/* Set the LCD type for the R61580 */
|
||||
|
||||
g_lcddev.type = LCD_TYPE_R61580;
|
||||
lcddbg("LCD type: %d\n", g_lcddev.type);
|
||||
|
||||
/* Start Initial Sequence */
|
||||
|
||||
stm3240g_writereg(LCD_REG_0, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_0, 0x0000);
|
||||
up_mdelay(100);
|
||||
stm3240g_writereg(LCD_REG_0, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_0, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_0, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_0, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_164, 0x0001);
|
||||
up_mdelay(100);
|
||||
stm3240g_writereg(LCD_REG_96, 0xa700);
|
||||
stm3240g_writereg(LCD_REG_8, 0x0808);
|
||||
|
||||
/* Gamma Setting */
|
||||
|
||||
stm3240g_writereg(LCD_REG_48, 0x0203);
|
||||
stm3240g_writereg(LCD_REG_49, 0x080f);
|
||||
stm3240g_writereg(LCD_REG_50, 0x0401);
|
||||
stm3240g_writereg(LCD_REG_51, 0x050b);
|
||||
stm3240g_writereg(LCD_REG_52, 0x3330);
|
||||
stm3240g_writereg(LCD_REG_53, 0x0b05);
|
||||
stm3240g_writereg(LCD_REG_54, 0x0005);
|
||||
stm3240g_writereg(LCD_REG_55, 0x0f08);
|
||||
stm3240g_writereg(LCD_REG_56, 0x0302);
|
||||
stm3240g_writereg(LCD_REG_57, 0x3033);
|
||||
|
||||
/* Power Setting */
|
||||
|
||||
stm3240g_writereg(LCD_REG_144, 0x0018); /* 80Hz */
|
||||
stm3240g_writereg(LCD_REG_16, 0x0530); /* BT, AP */
|
||||
stm3240g_writereg(LCD_REG_17, 0x0237); /* DC1,DC0,VC */
|
||||
stm3240g_writereg(LCD_REG_18, 0x01bf);
|
||||
stm3240g_writereg(LCD_REG_19, 0x1000); /* VCOM */
|
||||
up_mdelay(200);
|
||||
|
||||
stm3240g_writereg(LCD_REG_1, 0x0100); /* Set SS bit */
|
||||
stm3240g_writereg(LCD_REG_2, 0x0200);
|
||||
stm3240g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */
|
||||
stm3240g_writereg(LCD_REG_9, 0x0001);
|
||||
stm3240g_writereg(LCD_REG_10, 0x0008);
|
||||
stm3240g_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */
|
||||
stm3240g_writereg(LCD_REG_13, 0xd000);
|
||||
stm3240g_writereg(LCD_REG_14, 0x0030);
|
||||
stm3240g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */
|
||||
stm3240g_writereg(LCD_REG_32, 0x0000); /* H Start */
|
||||
stm3240g_writereg(LCD_REG_33, 0x0000); /* V Start */
|
||||
stm3240g_writereg(LCD_REG_41, 0x002e);
|
||||
stm3240g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
|
||||
stm3240g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */
|
||||
stm3240g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
|
||||
stm3240g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */
|
||||
stm3240g_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */
|
||||
stm3240g_writereg(LCD_REG_106, 0x0000); /* set scrolling line */
|
||||
stm3240g_writereg(LCD_REG_128, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_129, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_130, 0x005f);
|
||||
stm3240g_writereg(LCD_REG_147, 0x0701);
|
||||
|
||||
stm3240g_writereg(LCD_REG_7, 0x0000); /* Display OFF */
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
#ifndef CONFIG_STM32_AM240320_DISABLE
|
||||
g_lcddev.type = LCD_TYPE_AM240320;
|
||||
g_lcddev.type = LCD_TYPE_ILI9320;
|
||||
lcddbg("LCD type: %d\n", g_lcddev.type);
|
||||
|
||||
/* Start Initial Sequence */
|
||||
|
|
@ -1399,10 +1110,100 @@ static inline void stm3240g_lcdinitialize(void)
|
|||
|
||||
stm3240g_writereg(LCD_REG_3, 0x1018);
|
||||
stm3240g_writereg(LCD_REG_7, 0); /* Display off */
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#if !defined(CONFIG_STM32_ILI9325_DISABLE)
|
||||
if (id == 0x9325)
|
||||
{
|
||||
g_lcddev.type = LCD_TYPE_ILI9325;
|
||||
lcddbg("LCD type: %d\n", g_lcddev.type);
|
||||
|
||||
/* Start Initial Sequence */
|
||||
|
||||
stm3240g_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */
|
||||
stm3240g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */
|
||||
stm3240g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */
|
||||
stm3240g_writereg(LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1. */
|
||||
stm3240g_writereg(LCD_REG_4, 0x0000); /* Resize register */
|
||||
stm3240g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */
|
||||
stm3240g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */
|
||||
stm3240g_writereg(LCD_REG_10, 0x0000); /* FMARK function */
|
||||
stm3240g_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */
|
||||
stm3240g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */
|
||||
stm3240g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */
|
||||
|
||||
/* Power On sequence */
|
||||
|
||||
stm3240g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
|
||||
stm3240g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
|
||||
stm3240g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
|
||||
stm3240g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
|
||||
up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */
|
||||
stm3240g_writereg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
|
||||
stm3240g_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
|
||||
up_mdelay(50); /* Delay 50 ms */
|
||||
stm3240g_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
|
||||
up_mdelay(50); /* Delay 50 ms */
|
||||
stm3240g_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
|
||||
stm3240g_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
|
||||
up_mdelay(50); /* Delay 50 ms */
|
||||
stm3240g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
|
||||
stm3240g_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
|
||||
|
||||
/* Adjust the Gamma Curve (ILI9325) */
|
||||
|
||||
stm3240g_writereg(LCD_REG_48, 0x0007);
|
||||
stm3240g_writereg(LCD_REG_49, 0x0302);
|
||||
stm3240g_writereg(LCD_REG_50, 0x0105);
|
||||
stm3240g_writereg(LCD_REG_53, 0x0206);
|
||||
stm3240g_writereg(LCD_REG_54, 0x0808);
|
||||
stm3240g_writereg(LCD_REG_55, 0x0206);
|
||||
stm3240g_writereg(LCD_REG_56, 0x0504);
|
||||
stm3240g_writereg(LCD_REG_57, 0x0007);
|
||||
stm3240g_writereg(LCD_REG_60, 0x0105);
|
||||
stm3240g_writereg(LCD_REG_61, 0x0808);
|
||||
|
||||
/* Set GRAM area */
|
||||
|
||||
stm3240g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
|
||||
stm3240g_writereg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
|
||||
stm3240g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
|
||||
stm3240g_writereg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
|
||||
|
||||
stm3240g_writereg(LCD_REG_96, 0xA700); /* Gate Scan Line(GS=1, scan direction is G320~G1) */
|
||||
stm3240g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */
|
||||
stm3240g_writereg(LCD_REG_106, 0x0000); /* set scrolling line */
|
||||
|
||||
/* Partial Display Control */
|
||||
|
||||
stm3240g_writereg(LCD_REG_128, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_129, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_130, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_131, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_132, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_133, 0x0000);
|
||||
|
||||
/* Panel Control */
|
||||
|
||||
stm3240g_writereg(LCD_REG_144, 0x0010);
|
||||
stm3240g_writereg(LCD_REG_146, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_147, 0x0003);
|
||||
stm3240g_writereg(LCD_REG_149, 0x0110);
|
||||
stm3240g_writereg(LCD_REG_151, 0x0000);
|
||||
stm3240g_writereg(LCD_REG_152, 0x0000);
|
||||
|
||||
/* set GRAM write direction and BGR = 1 */
|
||||
/* I/D=00 (Horizontal : increment, Vertical : decrement) */
|
||||
/* AM=1 (address is updated in vertical writing direction) */
|
||||
|
||||
stm3240g_writereg(LCD_REG_3, 0x1018);
|
||||
|
||||
stm3240g_writereg(LCD_REG_7, 0x0); /* display off*/
|
||||
|
||||
#else
|
||||
lcddbg("Unsupported LCD type\n");
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/**************************************************************************************
|
||||
|
|
@ -1587,7 +1388,7 @@ static void stm3240g_backlight(void)
|
|||
|
||||
int up_lcdinitialize(void)
|
||||
{
|
||||
gvdbg("Initializing\n");
|
||||
lcdvdbg("Initializing\n");
|
||||
|
||||
/* Configure GPIO pins and configure the FSMC to support the LCD */
|
||||
|
||||
|
|
@ -1659,4 +1460,3 @@ void stm3240g_lcdclear(uint16_t color)
|
|||
LCD->value = color;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -138,20 +138,32 @@ void stm32_selectlcd(void)
|
|||
|
||||
stm32_enablefsmc();
|
||||
|
||||
/* Bank4 NOR/SRAM control register configuration */
|
||||
/* Color LCD configuration (LCD configured as follow):
|
||||
*
|
||||
* - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it.
|
||||
* - Memory Type = SRAM "FSMC_BCR_SRAM"
|
||||
* - Data Width = 16bit "FSMC_BCR_MWID16"
|
||||
* - Write Operation = Enable "FSMC_BCR_WREN"
|
||||
* - Extended Mode = Enable "FSMC_BCR_EXTMOD"
|
||||
* - Asynchronous Wait = Disable
|
||||
*/
|
||||
|
||||
putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4);
|
||||
/* Bank3 NOR/SRAM control register configuration */
|
||||
|
||||
/* Bank4 NOR/SRAM timing register configuration */
|
||||
putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN | FSMC_BCR_EXTMOD,
|
||||
STM32_FSMC_BCR3);
|
||||
|
||||
putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTRUN(0)|
|
||||
FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR4);
|
||||
/* Bank3 NOR/SRAM timing register configuration */
|
||||
|
||||
putreg32(0xffffffff, STM32_FSMC_BWTR4);
|
||||
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTRUN(0) |
|
||||
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
|
||||
|
||||
putreg32(0xffffffff, STM32_FSMC_BWTR3);
|
||||
|
||||
/* Enable the bank by setting the MBKEN bit */
|
||||
|
||||
putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4);
|
||||
putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN | FSMC_BCR_EXTMOD,
|
||||
STM32_FSMC_BCR3);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_FSMC */
|
||||
|
|
|
|||
Loading…
Reference in New Issue