forked from Archive/PX4-Autopilot
ADC driver update
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4203 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
b7edb56d6f
commit
7dd484954b
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@ -50,6 +50,7 @@
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#include <errno.h>
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#include <assert.h>
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#include <debug.h>
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#include <unistd.h>
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#include <arch/board/board.h>
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#include <nuttx/arch.h>
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@ -98,14 +99,17 @@ struct stm32_dev_s
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uint8_t nchannels; /* Number of channels */
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uint8_t intf; /* ADC interface number */
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uint8_t current; /* Current ADC channel being converted */
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#ifdef ADC_HAVE_TIMER
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uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, 3=CC4, 4=TRGO */
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#endif
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xcpt_t isr; /* Interrupt handler for this ADC block */
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uint32_t base; /* Base address of registers unique to this ADC block */
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#ifdef ADC_HAVE_TIMER
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uint32_t tbase; /* Base address of timer used by this ADC block */
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uint32_t extsel; /* EXTSEL value used by this ADC block */
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uint32_t presc; /* Timer prescaler value */
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uint32_t pclck; /* The PCLK frequency that drives this timer */
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uint32_t freq; /* The desired frequency of conversions */
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#endif
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uint8_t chanlist[ADC_MAX_SAMPLES];
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};
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@ -117,6 +121,10 @@ struct stm32_dev_s
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static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset);
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static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value);
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#ifdef ADC_HAVE_TIMER
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static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset);'
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static void tim_putreg(struct stm32_dev_s *priv, int offset, uint16_t value);
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#endif
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static void adc_rccreset(struct stm32_dev_s *priv, bool reset);
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/* ADC Interrupt Handler */
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@ -142,6 +150,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg);
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static void adc_enable(FAR struct stm32_dev_s *priv, bool enable);
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#ifdef ADC_HAVE_TIMER
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static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable);
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static int adc_timinit(FAR struct stm32_dev_s *priv);
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#endif
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static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable);
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@ -176,9 +185,11 @@ static struct stm32_dev_s g_adcpriv1 =
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.intf = 1,
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.base = STM32_ADC1_BASE,
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#ifdef ADC1_HAVE_TIMER
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.trigger = CONFIG_STM32_ADC1_TIMTRIG;
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.tbase = ADC1_TIMER_BASE,
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.extsel = ADC1_EXTSEL_VALUE,
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.presc = ADC1_TIMER_PCLK_FREQUENCY / CONFIG_STM32_ADC1_SAMPLE_FREQUENCY,
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.pclck = ADC1_TIMER_PCLK_FREQUENCY,
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.freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY,
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#endif
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};
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@ -204,9 +215,11 @@ static struct stm32_dev_s g_adcpriv2 =
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.intf = 2;
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.base = STM32_ADC2_BASE,
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#ifdef ADC2_HAVE_TIMER
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.trigger = CONFIG_STM32_ADC2_TIMTRIG;
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.tbase = ADC2_TIMER_BASE,
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.extsel = ADC2_EXTSEL_VALUE,
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.presc = ADC2_TIMER_PCLK_FREQUENCY / CONFIG_STM32_ADC2_SAMPLE_FREQUENCY,
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.pclck = ADC2_TIMER_PCLK_FREQUENCY,
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.freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY,
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#endif
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};
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@ -232,9 +245,11 @@ static struct stm32_dev_s g_adcpriv3 =
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.intf = 3;
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.base = STM32_ADC3_BASE,
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#ifdef ADC3_HAVE_TIMER
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.trigger = CONFIG_STM32_ADC3_TIMTRIG;
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.tbase = ADC3_TIMER_BASE,
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.extsel = ADC3_EXTSEL_VALUE,
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.presc = ADC3_TIMER_PCLK_FREQUENCY / CONFIG_STM32_ADC3_SAMPLE_FREQUENCY,
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.pclck = ADC3_TIMER_PCLK_FREQUENCY,
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.freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY,
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#endif
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};
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@ -303,9 +318,9 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value)
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static uint32_t tim_getreg(struct stm32_dev_s *priv, int offset)
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static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset)
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{
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return getreg32(priv->tbase + offset);
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return getreg16(priv->tbase + offset);
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}
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#endif
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@ -325,9 +340,48 @@ static uint32_t tim_getreg(struct stm32_dev_s *priv, int offset)
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static void tim_putreg(struct stm32_dev_s *priv, int offset, uint32_t value)
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static void tim_putreg(struct stm32_dev_s *priv, int offset, uint16_t value)
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{
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putreg32(value, priv->tbase + offset);
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putreg16(value, priv->tbase + offset);
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}
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#endif
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/****************************************************************************
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* Name: adc_timstart
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*
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* Description:
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* Start (or stop) the timer counter
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*
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* Input Parameters:
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* priv - A reference to the ADC block status
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* enable - True: Start conversion
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*
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* Returned Value:
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*
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static void adc_timstart(struct stm32_dev_s *priv, bool enable)
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{
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uint16_t regval;
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avdbg("enable: %d\n", enable);
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regval = tim_getreg(priv, STM32_BTIM_CR1_OFFSET);
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if (enable)
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{
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/* Start the counter */
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regval |= ATIM_CR1_CEN;
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}
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else
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{
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/* Disable the counter */
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regval &= ~ATIM_CR1_CEN;
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}
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tim_putreg(priv, STM32_BTIM_CR1_OFFSET, regval);
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}
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#endif
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@ -349,7 +403,13 @@ static void tim_putreg(struct stm32_dev_s *priv, int offset, uint32_t value)
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#ifdef ADC_HAVE_TIMER
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static int adc_timinit(FAR struct stm32_dev_s *priv)
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{
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uint32_t prescaler;
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uint32_t reload;
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uint32_t regval;
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uint16_t cr1;
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uint16_t cr2;
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uint16_t ccmr1;
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uint16_t ccmr2;
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/* If the timer base address is zero, then this ADC was not configured to
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* use a timer.
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@ -357,16 +417,20 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
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if (!priv->tbase)
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{
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#warning "Does anything need to be configured if there is no timer for this ADC?"
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/* Configure the ADC to use the selected timer and timer channel as the trigger
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* EXTTRIG: External Trigger Conversion mode for regular channels DISABLE
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*/
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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regval &= ~ADC_CR2_EXTTRIG;
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adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
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return OK;
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}
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/* Configure the ADC to use the selected timer and timer channel as the trigger */
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/* EXTTRIG: External Trigger Conversion mode for regular channels */
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET)
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else
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{
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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regval |= ADC_CR2_EXTTRIG;
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}
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/* EXTSEL selection: These bits select the external event used to trigger
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* the start of conversion of a regular group. NOTE:
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@ -382,35 +446,153 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
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adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
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/* Configure the timer channel to drive the ADC */
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#warning "LOTS of missing timer setup logic"
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regval = priv->presc;
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/* Caculate optimal values for the timer prescaler and for the timer reload
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* register. If freq is the desired frequency, then
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*
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* reload = timclk / freq
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* reload = (pclck / prescaler) / freq
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*
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* There are many solutions to do this, but the best solution will be the
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* one that has the largest reload value and the smallest prescaler value.
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* That is the solution that should give us the most accuracy in the timer
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* control. Subject to:
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*
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* 0 <= prescaler <= 65536
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* 1 <= reload <= 65535
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*
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* So ( prescaler = pclck / 65535 / freq ) would be optimal.
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*/
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prescaler = (priv->pclck / priv->freq + 65534) / 65535;
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/* We need to decrement the prescaler value by one, but only, the value does
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* not underflow.
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*/
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if (regval > 0)
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if (prescaler > 0)
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{
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regval--;
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prescaler--;
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}
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/* Check for overflow */
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if (regval > 0xffff)
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else if (prescaler > 0xffff)
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{
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regval = 0xffff;
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adbg("WARNING: Prescaler overflowed.\n");
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prescaler = 0xffff;
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}
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/* Save the timer prescaler value */
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reload = (priv->pclck / prescaler) / priv->freq;
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tim_putreg(priv, STM32_BTIM_PSC_OFFSET, regval);
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if (reload < 1)
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{
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adbg("WARNING: Reload value underflowed.\n");
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reload = 1;
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}
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else if (reload > 65535)
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{
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adbg("WARNING: Reload value overflowed.\n");
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reload = 65535;
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}
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avdbg("TIM%d PCLCK: %d frequency: %d TIMCLK: %d prescaler: %d reload: %d\n",
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priv->intf, priv->pclck, priv->freq, (priv->pclck / (prescaler+1)), prescaler, reload);
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/* Set up the timer CR1 register */
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cr1 = tim_getreg(priv, STM32_GTIM_CR1_OFFSET);
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/* Disable the timer until we get it configured */
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adc_timstart(priv, false);
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/* Select the Counter Mode == count up:
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*
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* ATIM_CR1_EDGE: The counter counts up or down depending on the
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* direction bit(DIR).
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* ATIM_CR1_DIR: 0: count up, 1: count down
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*/
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cr1 &= ~(ATIM_CR1_DIR | ATIM_CR1_CMS_MASK);
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cr1 |= ATIM_CR1_EDGE;
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/* Set the clock division to zero for all */
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cr1 &= ~GTIM_CR1_CKD_MASK;
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tim_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
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/* Save the timer prescaler value and autoreload value*/
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tim_putreg(priv, STM32_BTIM_PSC_OFFSET, prescaler);
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tim_putreg(priv, STM32_BTIM_ARR_OFFSET, reload);
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/* Clear the advanced timers repitition counter in TIM1 */
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#if defined(CONFIG_STM32_TIM1_ADC3) || defined(CONFIG_STM32_TIM8_ADC3)
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if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
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{
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tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0);
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}
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#endif
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/* TIMx event generation: Bit 0 UG: Update generation */
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tim_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG);
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/* CCMR Configurations */
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ccmr1 = 0;
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ccmr2 = 0;
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switch (priv->trigger)
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{
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case 0: /* Timer x CC1 event */
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{
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ccmr1 = (ATIM_CCMR_CCS_CCIN1 << ATIM_CCMR1_CC1S_SHIFT) |
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(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) |
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0x01; /* CC1 channel is configured as input, IC1 is mapped on TI1 */
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#warning "* I will fix this numeric values with the definitions *"
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ccmr2 = 0x68;
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}
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break;
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case 1: /* Timer x CC2 event */
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{
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#warning "missing logic, I want the Timer-x-CC1-event working first"
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}
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break;
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case 2: /* Timer x CC3 event */
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{
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#warning "missing logic, I want the Timer-x-CC1-event working first"
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}
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break;
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case 3: /* Timer x CC4 event */
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{
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#warning "missing logic, I want the Timer-x-CC1-event working first"
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}
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break;
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case 4: /* Timer x TRGO event */
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{
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#warning "missing logic, I want the Timer-x-CC1-event working first"
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}
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break;
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default:
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return -EINVAL;
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}
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/* Enable the timer counter */
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/* All but the CEN bit with the default config in CR1 */
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regval = stm32_tim_getreg(priv, STM32_BTIM_CR1_OFFSET);
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regval |= ATIM_CR1_CEN;
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tim_putreg(priv, STM32_BTIM_CR1_OFFSET, val);
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adc_timstart(priv, true);
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return OK;
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}
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#endif
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@ -447,7 +629,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable)
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regval &= ~ADC_CR2_SWSTART;
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}
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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adc_putreg(priv, STM32_ADC_CR2_OFFSET,regval);
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}
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/****************************************************************************
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@ -573,6 +755,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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irqstate_t flags;
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uint32_t regval;
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int offset;
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int ret;
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int i;
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avdbg("intf: %d\n", priv->intf);
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@ -625,14 +808,21 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, 0x00b6db6d);
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#ifdef ADC_HAVE_TIMER
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adc_timinit(priv);
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ret = adc_timinit(priv);
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if (ret!=OK)
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{
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adbg("Error initializing the timers\n");
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}
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#endif
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/* ADC CR1 Configuration */
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regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET);
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/* Clear DUALMODE and SCAN bits */
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regval &= ~ADC_CR1_DUALMOD_MASK;
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regval &= ~ADC_CR1_SCAN; /* Clear DUALMODE and SCAN bits */
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regval &= ~ADC_CR1_SCAN;
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adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval);
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/* Initialize the ADC_Mode (ADC_Mode_Independent) */
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@ -703,14 +893,16 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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priv->current = 0;
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usleep(10);
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/* Set ADON to wake up the ADC from Power Down state. */
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usleep(10);
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adc_enable(priv, true);
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/* Set ADON (Again) to start the conversion. */
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adc_enable(priv, true);
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irqrestore(flags);
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avdbg("SR: %08x CR1: 0x%08x CR2: 0x%08x\n",
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@ -752,9 +944,11 @@ static int adc_setup(FAR struct adc_dev_s *dev)
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{
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/* Enable the ADC interrupt */
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avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq);
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up_enable_irq(priv->irq);
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}
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avdbg("Returning %d\n",ret);
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return ret;
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}
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@ -863,7 +1057,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
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adcsr = adc_getreg(priv, STM32_ADC_SR_OFFSET);
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if ((adcsr & ADC_SR_AWD) != 0)
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{
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adbg(" Analog Watchdog, Value converted out of range!\n");
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adbg("WARNING: Analog Watchdog, Value converted out of range!\n");
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}
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/* EOC: End of conversion */
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@ -886,6 +1080,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
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* 3) The third is the converted data for the channel.
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*/
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avdbg("Calling adc_receive(dev, priv->chanlist[%d], value=%d)", priv->current, value);
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adc_receive(dev, priv->chanlist[priv->current], value);
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/* Set the channel number of the next channel that will complete conversion */
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@ -1106,7 +1301,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
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#ifdef CONFIG_STM32_ADC1
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if (intf == 1)
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{
|
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adbg("ADC1 Selected\n");
|
||||
avdbg("ADC1 Selected\n");
|
||||
dev = &g_adcdev1;
|
||||
}
|
||||
else
|
||||
|
|
@ -1114,7 +1309,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
|
|||
#ifdef CONFIG_STM32_ADC2
|
||||
if (intf == 2)
|
||||
{
|
||||
adbg("ADC2 Selected\n");
|
||||
avdbg("ADC2 Selected\n");
|
||||
dev = &g_adcdev2;
|
||||
}
|
||||
else
|
||||
|
|
@ -1122,7 +1317,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
|
|||
#ifdef CONFIG_STM32_ADC3
|
||||
if (intf == 3)
|
||||
{
|
||||
adbg("ADC3 Selected\n");
|
||||
avdbg("ADC3 Selected\n");
|
||||
dev = &g_adcdev3;
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -47,6 +47,8 @@
|
|||
|
||||
#include "chip.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "stm32_pwm.h"
|
||||
#include "stm3210e-internal.h"
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
|
|
@ -74,7 +76,7 @@
|
|||
|
||||
/* The number of ADC channels in the conversion list */
|
||||
|
||||
#define ADC_NCHANNELS 3
|
||||
#define ADC_NCHANNELS 2
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
|
|
@ -82,11 +84,11 @@
|
|||
|
||||
/* Identifying number of each ADC channel: Variable Resistor , BNC_CN5 and BNC_CN3 */
|
||||
|
||||
static const uint8_t g_chanlist[ADC_NCHANNELS] = {14, 10, 12};
|
||||
static const uint8_t g_chanlist[ADC_NCHANNELS] = {14, 10};
|
||||
|
||||
/* Configurations of pins used byte each ADC channels */
|
||||
|
||||
static const uint32_t g_pinlist[ADC_NCHANNELS] = {GPIO_ADC1_IN14 , GPIO_ADC1_IN10, GPIO_ADC1_IN13};
|
||||
static const uint32_t g_pinlist[ADC_NCHANNELS] = {GPIO_ADC1_IN14 , GPIO_ADC1_IN10};
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
|
|
@ -118,7 +120,7 @@ int adc_devinit(void)
|
|||
|
||||
for(i = 0; i < ADC_NCHANNELS; i++)
|
||||
{
|
||||
stm32_configgpio(chanlist[i]);
|
||||
stm32_configgpio(g_chanlist[i]);
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
|
|
|||
|
|
@ -47,6 +47,8 @@
|
|||
|
||||
#include "chip.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "stm32_pwm.h"
|
||||
#include "stm3240g-internal.h"
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
|
|
|
|||
Loading…
Reference in New Issue