forked from Archive/PX4-Autopilot
Cosmetic updates to the ENC28J60 driver
git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5161 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
a2256f3fd9
commit
7d318ee113
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@ -68,3 +68,4 @@ distclean: clean
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@for dir in $(INSTALLED_DIRS) ; do \
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$(MAKE) -C $$dir distclean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)"; \
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done
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@ -466,7 +466,7 @@ Build Targets and Options
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This is the build "verbosity flag." If you specify V=1 on the make command
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line, you will see the exact commands used in the build. This can be very
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useful when adding new boards or tracking down compile time errors and
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warnings.
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warnings (Contributed by Richard Cochran).
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CYGWIN BUILD PROBLEMS
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^^^^^^^^^^^^^^^^^^^^^
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@ -925,7 +925,7 @@ static inline void enc_wrbuffer(FAR struct enc_driver_s *priv,
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*/
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enc_deselect(priv);
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enc_bmdump(ENC_WBM, buffer, buflen);
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enc_bmdump(ENC_WBM, buffer, buflen+1);
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}
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/****************************************************************************
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@ -949,20 +949,38 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
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{
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uint16_t data = 0;
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/* Set the PHY address (and start the PHY read operation) */
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/* "To read from a PHY register:
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*
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* 1. Write the address of the PHY register to read from into the MIREGADR
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* register.
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*/
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enc_wrbreg(priv, ENC_MIREGADR, phyaddr);
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/* 2. Set the MICMD.MIIRD bit. The read operation begins and the
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* MISTAT.BUSY bit is set.
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*/
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enc_wrbreg(priv, ENC_MICMD, MICMD_MIIRD);
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/* Wait until the PHY read completes */
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/* 3. Wait 10.24 µs. Poll the MISTAT.BUSY bit to be certain that the
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* operation is complete. While busy, the host controller should not
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* start any MIISCAN operations or write to the MIWRH register.
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*
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* When the MAC has obtained the register contents, the BUSY bit will
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* clear itself.
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*/
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up_udelay(12);
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if (enc_waitbreg(priv, ENC_MISTAT, MISTAT_BUSY, 0x00) == OK);
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{
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/* Terminate reading */
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/* 4. Clear the MICMD.MIIRD bit. */
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enc_wrbreg(priv, ENC_MICMD, 0x00);
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/* Get the PHY data */
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/* 5. Read the desired data from the MIRDL and MIRDH registers. The
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* order that these bytes are accessed is unimportant."
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*/
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data = (uint16_t)enc_rdbreg(priv, ENC_MIRDL);
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data |= (uint16_t)enc_rdbreg(priv, ENC_MIRDH) << 8;
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@ -992,17 +1010,35 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
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static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
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uint16_t phydata)
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{
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/* Set the PHY register address */
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/* "To write to a PHY register:
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*
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* 1. Write the address of the PHY register to write to into the
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* MIREGADR register.
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*/
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enc_wrbreg(priv, ENC_MIREGADR, phyaddr);
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/* Write the PHY data */
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/* 2. Write the lower 8 bits of data to write into the MIWRL register. */
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enc_wrbreg(priv, ENC_MIWRL, phydata);
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/* 3. Write the upper 8 bits of data to write into the MIWRH register.
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* Writing to this register automatically begins the MIIM transaction,
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* so it must be written to after MIWRL. The MISTAT.BUSY bit becomes
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* set.
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*/
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enc_wrbreg(priv, ENC_MIWRH, phydata >> 8);
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/* Wait until the PHY write completes */
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/* The PHY register will be written after the MIIM operation completes,
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* which takes 10.24 µs. When the write operation has completed, the BUSY
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* bit will clear itself.
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*
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* The host controller should not start any MIISCAN or MIIRD operations
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* while busy."
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*/
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up_udelay(12);
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enc_waitbreg(priv, ENC_MISTAT, MISTAT_BUSY, 0x00);
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}
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@ -1063,7 +1099,10 @@ static int enc_transmit(FAR struct enc_driver_s *priv)
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enc_wrbreg(priv, ENC_EWRPTL, PKTMEM_TX_START & 0xff);
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enc_wrbreg(priv, ENC_EWRPTH, PKTMEM_TX_START >> 8);
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/* Set the TX End pointer based on the size of the packet to send */
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/* Set the TX End pointer based on the size of the packet to send. Note
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* that the offset accounts for the control byte at the beginning the
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* buffer plus the size of the packet data.
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*/
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txend = PKTMEM_TX_START + priv->dev.d_len;
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enc_wrbreg(priv, ENC_ETXNDL, txend & 0xff);
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@ -360,8 +360,8 @@
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/* PHY Control Register 1 Register Bit Definitions */
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#define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Power-Down */
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#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power Save */
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#define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Duplex Mode */
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#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power-Down */
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#define PHCON1_PLOOPBK (1 << 14) /* Bit 14: PHY Loopback */
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#define PHCON1_PRST (1 << 15) /* Bit 15: PHY Software Reset */
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@ -399,7 +399,6 @@
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#define PHIR_PLNKIF (1 << 4) /* Bit 4: PHY Link Change Interrupt */
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/* PHLCON Regiser Bit Definitions */
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/* Bit 0: Reserved */
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#define PHLCON_STRCH (1 << 1) /* Bit 1: LED Pulse Stretching Enable */
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#define PHLCON_LFRQ0 (1 << 2) /* Bit 2: LED Pulse Stretch Time Configuration */
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