dark0707
/
px4-firmware
forked from Archive/PX4-Autopilot
1
0
Fork 0
Code Pull Requests Activity

Fixed typo and added support for H7 temperature sense on ADC3

This commit is contained in:
dino 2021-03-15 16:38:54 +01:00 committed by David Sidrane
parent 6d04a67b02
commit 7c8b7fa44d
4 changed files with 15 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
platforms/nuttx/src/px4/stm/stm32f1/include/px4_arch/micro_hal.h
View File

@ -46,6 +46,6 @@ __BEGIN_DECLS
# define PX4_BBSRAM_GETDESC_IOCTL STM32_BBSRAM_GETDESC_IOCTL
#endif
#define PX4_NUMBER_I2C_BUSES STM32_NI2C
#define APX4_ADC_INTERNAL_TEMP_SENSOR_CHANNEL 16
#define PX4_ADC_INTERNAL_TEMP_SENSOR_CHANNEL 16
__END_DECLS

2
platforms/nuttx/src/px4/stm/stm32f3/include/px4_arch/micro_hal.h
View File

@ -46,7 +46,7 @@ __BEGIN_DECLS
# define PX4_BBSRAM_GETDESC_IOCTL STM32_BBSRAM_GETDESC_IOCTL
#endif
#define PX4_NUMBER_I2C_BUSES STM32_NI2C
#define APX4_ADC_INTERNAL_TEMP_SENSOR_CHANNEL 16
#define PX4_ADC_INTERNAL_TEMP_SENSOR_CHANNEL 16
__END_DECLS

14
platforms/nuttx/src/px4/stm/stm32h7/adc/adc.cpp
View File

@ -54,7 +54,7 @@
#define rPCSEL(base) REG((base), STM32_ADC_PCSEL_OFFSET)
#define rCFG(base) REG((base), STM32_ADC_CFGR_OFFSET)
#define rCFG2(base) REG((base), STM32_ADC_CFGR2_OFFSET)
#define rCCR(base) REG((base), STM32_ADC_CCR_OFFSET)
#define rCCR() REG((STM32_ADC1_BASE), (STM32_ADC_CCR_OFFSET))
#define rSQR1(base) REG((base), STM32_ADC_SQR1_OFFSET)
#define rSQR2(base) REG((base), STM32_ADC_SQR2_OFFSET)
#define rSQR3(base) REG((base), STM32_ADC_SQR3_OFFSET)
@ -159,8 +159,8 @@ int px4_arch_adc_init(uint32_t base_address)
/* enable the temperature sensor, VREFINT channel and VBAT */
rCCR(base_address) = (ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN |
ADC_CCR_CKMODE_ASYCH | ADC_CCR_PRESC_DIV);
rCCR() = (ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN |
ADC_CCR_CKMODE_ASYCH | ADC_CCR_PRESC_DIV);
/* Enable ADC calibration. ADCALDIF == 0 so this is only for
* single-ended conversions, not for differential ones.
@ -276,6 +276,12 @@ uint32_t px4_arch_adc_sample(uint32_t base_address, unsigned channel)
{
irqstate_t flags = px4_enter_critical_section();
if (channel > PX4_ADC_ADC3_CHANNEL_OFFSET) {
channel = channel - PX4_ADC_ADC3_CHANNEL_OFFSET;
base_address = STM32_ADC3_BASE;
}
/* clear any previous EOC */
if (rISR(base_address) & ADC_INT_EOC) {
@ -315,7 +321,7 @@ float px4_arch_adc_reference_v()
uint32_t px4_arch_adc_temp_sensor_mask()
{
return 1 << APX4_ADC_INTERNAL_TEMP_SENSOR_CHANNEL;
return 1 << PX4_ADC_INTERNAL_TEMP_SENSOR_CHANNEL;
}
uint32_t px4_arch_adc_dn_fullcount()

4
platforms/nuttx/src/px4/stm/stm32h7/include/px4_arch/micro_hal.h
View File

@ -62,6 +62,8 @@ int stm32h7_flash_lock(size_t addr);
int stm32h7_flash_unlock(size_t addr);
int stm32h7_flash_writeprotect(size_t block, bool enabled);
#define stm32_flash_lock() stm32h7_flash_lock(PX4_FLASH_BASE)
#define APX4_ADC_INTERNAL_TEMP_SENSOR_CHANNEL 17 //Valid for ADC3 on H7x3
#define PX4_ADC_ADC3_CHANNEL_OFFSET 7
#define PX4_ADC_ADC3_BASE STM32_ADC3_BASE
#define PX4_ADC_INTERNAL_TEMP_SENSOR_CHANNEL (18 + PX4_ADC_ADC3_CHANNEL_OFFSET) //Valid for ADC3 on H7x3
__END_DECLS