forked from Archive/PX4-Autopilot
Add bit definitions for STM32 USB OTG FS Host-mode control and status registers
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4480 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
8beb69be2f
commit
736fcc20da
|
|
@ -549,16 +549,16 @@
|
|||
# define OTGFS_HNPTXSTS_NPTQXSAV_FULL (0 < OTGFS_HNPTXSTS_NPTQXSAV_SHIFT)
|
||||
#define OTGFS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */
|
||||
#define OTGFS_HNPTXSTS_NPTXQTOP_MASK (0x7f < OTGFS_HNPTXSTS_NPTXQTOP_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
|
||||
# define OTGFS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */
|
||||
# define OTGFS_HNPTXSTS_TYPE_MASK (3 < OTGFS_HNPTXSTS_TYPE_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_TYPE_INOUT (0 < OTGFS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */
|
||||
# define OTGFS_HNPTXSTS_TYPE_ZLP (1 < OTGFS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */
|
||||
# define OTGFS_HNPTXSTS_TYPE_HALT (3 < OTGFS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */
|
||||
# define OTGFS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
|
||||
# define OTGFS_HNPTXSTS_CHNUM_MASK (15 < OTGFS_HNPTXSTS_CHNUM_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
|
||||
# define OTGFS_HNPTXSTS_EPNUM_MASK (15 < OTGFS_HNPTXSTS_EPNUM_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_STS_SHIFT (25) /* Bits 25-26: Status */
|
||||
# define OTGFS_HNPTXSTS_STS_MASK (3 < OTGFS_HNPTXSTS_STS_SHIFT)
|
||||
# define OTGFS_HNPTXSTS_STS_INOUT (0 < OTGFS_HNPTXSTS_STS_SHIFT) /* IN/OUT token */
|
||||
# define OTGFS_HNPTXSTS_STS_ZLP (1 < OTGFS_HNPTXSTS_STS_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */
|
||||
# define OTGFS_HNPTXSTS_STS_HALT (3 < OTGFS_HNPTXSTS_STS_SHIFT) /* Channel halt command */
|
||||
# define OTGFS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
|
||||
/* Bit 31 Reserved, must be kept at reset value */
|
||||
/* general core configuration register */
|
||||
/* Bits 15:0 Reserved, must be kept at reset value */
|
||||
|
|
@ -588,27 +588,132 @@
|
|||
/* Host-mode control and status registers */
|
||||
|
||||
/* Host configuration register */
|
||||
#define OTGFS_HCFG_
|
||||
|
||||
#define OTGFS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */
|
||||
#define OTGFS_HCFG_FSLSPCS_MASK (3 < OTGFS_HCFG_FSLSPCS_SHIFT)
|
||||
# define OTGFS_HCFG_FSLSPCS_FS48MHz (1 < OTGFS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */
|
||||
# define OTGFS_HCFG_FSLSPCS_LS48MHz (1 < OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */
|
||||
# define OTGFS_HCFG_FSLSPCS_LS6MHz (2 < OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */
|
||||
#define OTGFS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */
|
||||
/* Bits 31:3 Reserved, must be kept at reset value */
|
||||
/* Host frame interval register */
|
||||
#define OTGFS_HFIR_
|
||||
|
||||
#define OTGFS_HFIR_MASK (0xffff)
|
||||
|
||||
/* Host frame number/frame time remaining register */
|
||||
#define OTGFS_HFNUM_
|
||||
|
||||
#define OTGFS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */
|
||||
#define OTGFS_HFNUM_FRNUM_MASK (0xffff < OTGFS_HFNUM_FRNUM_SHIFT)
|
||||
#define OTGFS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */
|
||||
#define OTGFS_HFNUM_FTREM_MASK (0xffff < OTGFS_HFNUM_FTREM_SHIFT)
|
||||
|
||||
/* Host periodic transmit FIFO/queue status register */
|
||||
#define OTGFS_HPTXSTS_
|
||||
/* Host all channels interrupt register */
|
||||
#define OTGFS_HAINT_
|
||||
/* Host all channels interrupt mask register */
|
||||
#define OTGFS_HAINTMSK_
|
||||
|
||||
#define OTGFS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */
|
||||
#define OTGFS_HPTXSTS_PTXFSAVL_MASK (0xffff < OTGFS_HPTXSTS_PTXFSAVL_SHIFT)
|
||||
# define OTGFS_HPTXSTS_PTXFSAVL_FULL (0 < OTGFS_HPTXSTS_PTXFSAVL_SHIFT)
|
||||
#define OTGFS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */
|
||||
#define OTGFS_HPTXSTS_PTXQSAV_MASK (0xff < OTGFS_HPTXSTS_PTXQSAV_SHIFT)
|
||||
# define OTGFS_HPTXSTS_PTXQSAV_FULL (0 < OTGFS_HPTXSTS_PTXQSAV_SHIFT)
|
||||
#define OTGFS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */
|
||||
#define OTGFS_HPTXSTS_PTXQTOP_MASK (0x7f < OTGFS_HPTXSTS_PTXQTOP_SHIFT)
|
||||
# define OTGFS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
|
||||
# define OTGFS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */
|
||||
# define OTGFS_HPTXSTS_TYPE_MASK (3 < OTGFS_HPTXSTS_TYPE_SHIFT)
|
||||
# define OTGFS_HPTXSTS_TYPE_INOUT (0 < OTGFS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */
|
||||
# define OTGFS_HPTXSTS_TYPE_ZLP (1 < OTGFS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */
|
||||
# define OTGFS_HPTXSTS_TYPE_HALT (3 < OTGFS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */
|
||||
# define OTGFS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
|
||||
# define OTGFS_HPTXSTS_EPNUM_MASK (15 < OTGFS_HPTXSTS_EPNUM_SHIFT)
|
||||
# define OTGFS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */
|
||||
|
||||
/* Host all channels interrupt and all channels interrupt mask registers */
|
||||
|
||||
#define OTGFS_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */
|
||||
|
||||
/* Host port control and status register */
|
||||
#define OTGFS_HPRT_
|
||||
|
||||
#define OTGFS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */
|
||||
#define OTGFS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */
|
||||
#define OTGFS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */
|
||||
#define OTGFS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */
|
||||
#define OTGFS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */
|
||||
#define OTGFS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */
|
||||
#define OTGFS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */
|
||||
#define OTGFS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */
|
||||
#define OTGFS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */
|
||||
/* Bit 9 Reserved, must be kept at reset value */
|
||||
#define OTGFS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */
|
||||
#define OTGFS_HPRT_PLSTS_MASK (3 < OTGFS_HPRT_PLSTS_SHIFT)
|
||||
# define OTGFS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */
|
||||
# define OTGFS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */
|
||||
#define OTGFS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */
|
||||
#define OTGFS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */
|
||||
#define OTGFS_HPRT_PTCTL_MASK (15 < OTGFS_HPRT_PTCTL_SHIFT)
|
||||
# define OTGFS_HPRT_PTCTL_DISABLED (0 < OTGFS_HPRT_PTCTL_SHIFT) /* Test mode disabled */
|
||||
# define OTGFS_HPRT_PTCTL_J (1 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_J mode */
|
||||
# define OTGFS_HPRT_PTCTL_L (2 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_K mode */
|
||||
# define OTGFS_HPRT_PTCTL_SE0_NAK (3 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */
|
||||
# define OTGFS_HPRT_PTCTL_PACKET (4 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */
|
||||
# define OTGFS_HPRT_PTCTL_FORCE (5 < OTGFS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */
|
||||
#define OTGFS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */
|
||||
#define OTGFS_HPRT_PSPD_MASK (3 < OTGFS_HPRT_PSPD_SHIFT)
|
||||
# define OTGFS_HPRT_PSPD_FS (1 < OTGFS_HPRT_PSPD_SHIFT) /* Full speed */
|
||||
# define OTGFS_HPRT_PSPD_LS (2 < OTGFS_HPRT_PSPD_SHIFT) /* Low speed */
|
||||
/* Bits 31:19 Reserved, must be kept at reset value */
|
||||
|
||||
/* Host channel-n characteristics register */
|
||||
#define OTGFS_HCCHAR0_
|
||||
|
||||
#define OTGFS_HCCHAR0_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
|
||||
#define OTGFS_HCCHAR_MPSIZ_MASK (0x7ff < OTGFS_HCCHAR_MPSIZ_SHIFT)
|
||||
#define OTGFS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */
|
||||
#define OTGFS_HCCHAR_EPNUM_MASK (15 < OTGFS_HCCHAR_EPNUM_SHIFT)
|
||||
#define OTGFS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */
|
||||
# define OTGFS_HCCHAR_EPDIR_OUT (0)
|
||||
# define OTGFS_HCCHAR_EPDIR_IN OTGFS_HCCHAR_EPDIR
|
||||
/* Bit 16 Reserved, must be kept at reset value */
|
||||
#define OTGFS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */
|
||||
#define OTGFS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
|
||||
#define OTGFS_HCCHAR_EPTYP_MASK (3 < OTGFS_HCCHAR_EPTYP_SHIFT)
|
||||
# define OTGFS_HCCHAR_EPTYP_CTRL (0 < OTGFS_HCCHAR_EPTYP_SHIFT) /* Control */
|
||||
# define OTGFS_HCCHAR_EPTYP_ISOC (1 < OTGFS_HCCHAR_EPTYP_SHIFT) /* Isochronous */
|
||||
# define OTGFS_HCCHAR_EPTYP_BULK (2 < OTGFS_HCCHAR_EPTYP_SHIFT) /* Bulk */
|
||||
# define OTGFS_HCCHAR_EPTYP_INTR (3 < OTGFS_HCCHAR_EPTYP_SHIFT) /* Interrupt */
|
||||
#define OTGFS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */
|
||||
#define OTGFS_HCCHAR_MCNT_MASK (3 < OTGFS_HCCHAR_MCNT_SHIFT)
|
||||
#define OTGFS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */
|
||||
#define OTGFS_HCCHAR_DAD_MASK (0x7f < OTGFS_HCCHAR_DAD_SHIFT)
|
||||
#define OTGFS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */
|
||||
#define OTGFS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */
|
||||
#define OTGFS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */
|
||||
|
||||
/* Host channel-n interrupt and Host channel-0 interrupt mask registers */
|
||||
|
||||
#define OTGFS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */
|
||||
#define OTGFS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */
|
||||
/* Bit 2 Reserved, must be kept at reset value */
|
||||
#define OTGFS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */
|
||||
#define OTGFS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */
|
||||
#define OTGFS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */
|
||||
#define OTGFS_HCINTMSK_NYET (1 << 6) /* Bit 6: response received interrupt mask */
|
||||
#define OTGFS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */
|
||||
#define OTGFS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */
|
||||
#define OTGFS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */
|
||||
#define OTGFS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */
|
||||
/* Bits 31:11 Reserved, must be kept at reset value */
|
||||
/* Host channel-n interrupt register */
|
||||
#define OTGFS_HCINT0_
|
||||
/* Host channel-0 interrupt mask register */
|
||||
#define OTGFS_HCINTMSK0_
|
||||
/* Host channel-n interrupt register */
|
||||
#define OTGFS_HCTSIZ0_
|
||||
|
||||
#define OTGFS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
|
||||
#define OTGFS_HCTSIZ_XFRSIZ_MASK (0x7ffff < OTGFS_HCTSIZ_XFRSIZ_SHIFT)
|
||||
#define OTGFS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */
|
||||
#define OTGFS_HCTSIZ_PKTCNT_MASK (0x3ff < OTGFS_HCTSIZ_PKTCNT_SHIFT)
|
||||
#define OTGFS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */
|
||||
#define OTGFS_HCTSIZ_DPID_MASK (3 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_DATA0 (0 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_DATA2 (1 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_DATA1 (2 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
# define OTGFS_HCTSIZ_DPID_MDATA (3 < OTGFS_HCTSIZ_DPID_SHIFT)
|
||||
/* Bit 31 Reserved, must be kept at reset value */
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue