forked from Archive/PX4-Autopilot
Merge pull request #168 from PX4/i2c_workaround
I2C driver workaround for NuttX
This commit is contained in:
Lorenz Meier
commit
6cc840a95b
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@ -107,23 +107,17 @@
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#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS)
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# define CONFIG_STM32_I2CTIMEOSEC 0
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# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */
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# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */
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#elif !defined(CONFIG_STM32_I2CTIMEOSEC)
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# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */
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#elif !defined(CONFIG_STM32_I2CTIMEOMS)
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# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */
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# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */
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#endif
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/* Interrupt wait time timeout in system timer ticks */
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#ifndef CONFIG_STM32_I2CTIMEOTICKS
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# define CONFIG_STM32_I2CTIMEOTICKS \
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(SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
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#endif
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#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
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# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS)
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#endif
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#define CONFIG_STM32_I2CTIMEOTICKS \
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(SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
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/* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC. In that
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* case, it is necessary to disable FSMC before each I2C1 access and re-enable FSMC
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@ -135,18 +129,6 @@
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# define I2C1_FSMC_CONFLICT
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#endif
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/* Macros to convert a I2C pin to a GPIO output */
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#if defined(CONFIG_STM32_STM32F10XX)
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# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \
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GPIO_MODE_50MHz)
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#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\
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GPIO_SPEED_50MHz | GPIO_OUTPUT_SET)
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#endif
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#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
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/* Debug ****************************************************************************/
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/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
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@ -218,16 +200,18 @@ struct stm32_trace_s
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struct stm32_i2c_config_s
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{
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uint32_t base; /* I2C base address */
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uint32_t clk_bit; /* Clock enable bit */
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uint32_t reset_bit; /* Reset bit */
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uint32_t scl_pin; /* GPIO configuration for SCL as SCL */
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uint32_t sda_pin; /* GPIO configuration for SDA as SDA */
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uint32_t base; /* I2C base address */
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#ifndef CONFIG_I2C_POLLED
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int (*isr)(int, void *); /* Interrupt handler */
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uint32_t ev_irq; /* Event IRQ */
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uint32_t er_irq; /* Error IRQ */
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int ( *isr)(int, void *); /* Interrupt handler */
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#endif
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uint32_t clk_bit; /* Clock enable bit */
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uint32_t reset_bit; /* Reset bit */
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uint32_t scl_pin; /* GPIO configuration for SCL as SCL */
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uint32_t scl_gpio; /* GPIO configuration for SCL as a GPIO */
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uint32_t sda_pin; /* GPIO configuration for SDA as SDA */
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uint32_t sda_gpio; /* GPIO configuration for SDA as a GPIO */
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uint32_t ev_irq; /* Event IRQ */
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uint32_t er_irq; /* Error IRQ */
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};
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/* I2C Device Private Data */
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@ -235,31 +219,31 @@ struct stm32_i2c_config_s
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struct stm32_i2c_priv_s
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{
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const struct stm32_i2c_config_s *config; /* Port configuration */
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int refs; /* Referernce count */
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sem_t sem_excl; /* Mutual exclusion semaphore */
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int refs; /* Referernce count */
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sem_t sem_excl; /* Mutual exclusion semaphore */
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#ifndef CONFIG_I2C_POLLED
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sem_t sem_isr; /* Interrupt wait semaphore */
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sem_t sem_isr; /* Interrupt wait semaphore */
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#endif
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volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */
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volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */
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uint8_t msgc; /* Message count */
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struct i2c_msg_s *msgv; /* Message list */
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uint8_t *ptr; /* Current message buffer */
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int dcnt; /* Current message length */
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uint16_t flags; /* Current message flags */
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uint8_t msgc; /* Message count */
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struct i2c_msg_s *msgv; /* Message list */
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uint8_t *ptr; /* Current message buffer */
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int dcnt; /* Current message length */
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uint16_t flags; /* Current message flags */
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/* I2C trace support */
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#ifdef CONFIG_I2C_TRACE
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int tndx; /* Trace array index */
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uint32_t start_time; /* Time when the trace was started */
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int tndx; /* Trace array index */
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uint32_t start_time; /* Time when the trace was started */
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/* The actual trace data */
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struct stm32_trace_s trace[CONFIG_I2C_NTRACE];
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#endif
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uint32_t status; /* End of transfer SR2|SR1 status */
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uint32_t status; /* End of transfer SR2|SR1 status */
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};
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/* I2C Device, Instance */
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@ -286,11 +270,8 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
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uint8_t offset, uint16_t clearbits,
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uint16_t setbits);
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static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev);
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#ifdef CONFIG_STM32_I2C_DYNTIMEO
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static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
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#endif /* CONFIG_STM32_I2C_DYNTIMEO */
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
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static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int timeout_us);
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static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv, int timeout_us);
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static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev);
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static inline void stm32_i2c_sem_init(FAR struct i2c_dev_s *dev);
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static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev);
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@ -300,7 +281,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t statu
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static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
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enum stm32_trace_e event, uint32_t parm);
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static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
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#endif /* CONFIG_I2C_TRACE */
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#endif
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static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
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uint32_t frequency);
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static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
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@ -310,7 +291,7 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
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#ifdef I2C1_FSMC_CONFLICT
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static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv);
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static inline void stm32_i2c_enablefsmc(uint32_t ahbenr);
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#endif /* I2C1_FSMC_CONFLICT */
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#endif
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static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
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#ifndef CONFIG_I2C_POLLED
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#ifdef CONFIG_STM32_I2C1
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@ -348,18 +329,27 @@ static int stm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *m
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************************************************************************************/
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#ifdef CONFIG_STM32_I2C1
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# ifndef GPIO_I2C1_SCL_GPIO
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# define GPIO_I2C1_SCL_GPIO 0
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# endif
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# ifndef GPIO_I2C1_SDA_GPIO
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# define GPIO_I2C1_SDA_GPIO 0
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# endif
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static const struct stm32_i2c_config_s stm32_i2c1_config =
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{
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.base = STM32_I2C1_BASE,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c1_isr,
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#endif
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.clk_bit = RCC_APB1ENR_I2C1EN,
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.reset_bit = RCC_APB1RSTR_I2C1RST,
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.scl_pin = GPIO_I2C1_SCL,
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.scl_gpio = GPIO_I2C1_SCL_GPIO,
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.sda_pin = GPIO_I2C1_SDA,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c1_isr,
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.sda_gpio = GPIO_I2C1_SDA_GPIO,
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.ev_irq = STM32_IRQ_I2C1EV,
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.er_irq = STM32_IRQ_I2C1ER
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#endif
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};
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struct stm32_i2c_priv_s stm32_i2c1_priv =
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@ -377,18 +367,27 @@ struct stm32_i2c_priv_s stm32_i2c1_priv =
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#endif
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#ifdef CONFIG_STM32_I2C2
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# ifndef GPIO_I2C2_SCL_GPIO
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# define GPIO_I2C2_SCL_GPIO 0
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# endif
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# ifndef GPIO_I2C2_SDA_GPIO
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# define GPIO_I2C2_SDA_GPIO 0
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# endif
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static const struct stm32_i2c_config_s stm32_i2c2_config =
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{
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.base = STM32_I2C2_BASE,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c2_isr,
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#endif
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.clk_bit = RCC_APB1ENR_I2C2EN,
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.reset_bit = RCC_APB1RSTR_I2C2RST,
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.scl_pin = GPIO_I2C2_SCL,
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.scl_gpio = GPIO_I2C2_SCL_GPIO,
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.sda_pin = GPIO_I2C2_SDA,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c2_isr,
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.sda_gpio = GPIO_I2C2_SDA_GPIO,
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.ev_irq = STM32_IRQ_I2C2EV,
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.er_irq = STM32_IRQ_I2C2ER
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#endif
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};
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struct stm32_i2c_priv_s stm32_i2c2_priv =
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@ -406,18 +405,27 @@ struct stm32_i2c_priv_s stm32_i2c2_priv =
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#endif
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#ifdef CONFIG_STM32_I2C3
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# ifndef GPIO_I2C3_SCL_GPIO
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# define GPIO_I2C3_SCL_GPIO 0
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# endif
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# ifndef GPIO_I2C3_SDA_GPIO
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# define GPIO_I2C3_SDA_GPIO 0
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# endif
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static const struct stm32_i2c_config_s stm32_i2c3_config =
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{
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.base = STM32_I2C3_BASE,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c3_isr,
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#endif
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.clk_bit = RCC_APB1ENR_I2C3EN,
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.reset_bit = RCC_APB1RSTR_I2C3RST,
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.scl_pin = GPIO_I2C3_SCL,
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.scl_gpio = GPIO_I2C3_SCL_GPIO,
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.sda_pin = GPIO_I2C3_SDA,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c3_isr,
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.sda_gpio = GPIO_I2C3_SDA_GPIO,
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.ev_irq = STM32_IRQ_I2C3EV,
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.er_irq = STM32_IRQ_I2C3ER
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#endif
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};
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struct stm32_i2c_priv_s stm32_i2c3_priv =
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@ -517,35 +525,6 @@ static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev)
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}
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}
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/************************************************************************************
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* Name: stm32_i2c_tousecs
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*
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* Description:
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* Return a micro-second delay based on the number of bytes left to be processed.
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*
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************************************************************************************/
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#ifdef CONFIG_STM32_I2C_DYNTIMEO
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static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
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{
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size_t bytecount = 0;
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int i;
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/* Count the number of bytes left to process */
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for (i = 0; i < msgc; i++)
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{
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bytecount += msgs[i].length;
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}
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/* Then return a number of microseconds based on a user provided scaling
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* factor.
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*/
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return (useconds_t)(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount);
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}
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#endif
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/************************************************************************************
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* Name: stm32_i2c_sem_waitdone
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*
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@ -555,7 +534,7 @@ static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
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************************************************************************************/
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#ifndef CONFIG_I2C_POLLED
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int timeout_us)
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{
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struct timespec abstime;
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irqstate_t flags;
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@ -587,24 +566,31 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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#if CONFIG_STM32_I2CTIMEOSEC > 0
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abstime.tv_sec += CONFIG_STM32_I2CTIMEOSEC;
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#endif
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#if CONFIG_STM32_I2CTIMEOUS_PER_BYTE > 0
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/* Add a value proportional to the number of bytes in the transfer */
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/* Count the number of bytes left to process */
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int i;
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int bytecount = 0;
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for (i = 0; i < priv->msgc; i++)
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{
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bytecount += priv->msgv[i].length;
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}
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#ifdef CONFIG_STM32_I2C_DYNTIMEO
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abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv);
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if (abstime.tv_nsec > 1000 * 1000 * 1000)
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{
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abstime.tv_sec++;
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abstime.tv_nsec -= 1000 * 1000 * 1000;
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}
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#elif CONFIG_STM32_I2CTIMEOMS > 0
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abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000;
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abstime.tv_nsec += (CONFIG_STM32_I2CTIMEOUS_PER_BYTE * bytecount) * 1000;
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if (abstime.tv_nsec > 1000 * 1000 * 1000)
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{
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abstime.tv_sec++;
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abstime.tv_nsec -= 1000 * 1000 * 1000;
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}
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#else
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#if CONFIG_STM32_I2CTIMEOMS > 0
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abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000;
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if (abstime.tv_nsec > 1000 * 1000 * 1000)
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{
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abstime.tv_sec++;
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abstime.tv_nsec -= 1000 * 1000 * 1000;
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}
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#endif
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#endif
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/* Wait until either the transfer is complete or the timeout expires */
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@ -638,21 +624,12 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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return ret;
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}
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#else
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int timeout_us)
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{
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uint32_t timeout;
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uint32_t start;
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uint32_t elapsed;
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int ret;
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/* Get the timeout value */
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#ifdef CONFIG_STM32_I2C_DYNTIMEO
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timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv));
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#else
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timeout = CONFIG_STM32_I2CTIMEOTICKS;
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#endif
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/* Signal the interrupt handler that we are waiting. NOTE: Interrupts
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* are currently disabled but will be temporarily re-enabled below when
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* sem_timedwait() sleeps.
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@ -675,11 +652,10 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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}
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/* Loop until the transfer is complete. */
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while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
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while (priv->intstate != INTSTATE_DONE && elapsed < USEC2TICK(timeout_us));
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i2cvdbg("intstate: %d elapsed: %d threshold: %d status: %08x\n",
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priv->intstate, elapsed, timeout, priv->status);
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priv->intstate, elapsed, USEC2TICK(timeout_us), priv->status);
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/* Set the interrupt state back to IDLE */
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@ -697,22 +673,13 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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*
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************************************************************************************/
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static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
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static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv, int timeout_us)
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{
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uint32_t start;
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uint32_t elapsed;
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||||
uint32_t timeout;
|
||||
uint32_t cr1;
|
||||
uint32_t sr1;
|
||||
|
||||
/* Select a timeout */
|
||||
|
||||
#ifdef CONFIG_STM32_I2C_DYNTIMEO
|
||||
timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP);
|
||||
#else
|
||||
timeout = CONFIG_STM32_I2CTIMEOTICKS;
|
||||
#endif
|
||||
|
||||
/* Wait as stop might still be in progress; but stop might also
|
||||
* be set because of a timeout error: "The [STOP] bit is set and
|
||||
* cleared by software, cleared by hardware when a Stop condition is
|
||||
|
|
@ -745,7 +712,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
|
|||
|
||||
/* Loop until the stop is complete or a timeout occurs. */
|
||||
|
||||
while (elapsed < timeout);
|
||||
while (elapsed < USEC2TICK(timeout_us));
|
||||
|
||||
/* If we get here then a timeout occurred with the STOP condition
|
||||
* still pending.
|
||||
|
|
@ -965,7 +932,7 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
|
|||
{
|
||||
/* Fast mode speed calculation with Tlow/Thigh = 16/9 */
|
||||
|
||||
#ifdef CONFIG_STM32_I2C_DUTY16_9
|
||||
#ifdef CONFIG_I2C_DUTY16_9
|
||||
speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25));
|
||||
|
||||
/* Set DUTY and fast speed bits */
|
||||
|
|
@ -1104,7 +1071,7 @@ static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv)
|
|||
|
||||
/* Is this I2C1 */
|
||||
|
||||
#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3)
|
||||
#ifdef CONFIG_STM32_I2C2
|
||||
if (priv->config->base == STM32_I2C1_BASE)
|
||||
#endif
|
||||
{
|
||||
|
|
@ -1231,29 +1198,26 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
|
|||
{
|
||||
stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
|
||||
|
||||
/* No interrupts or context switches may occur in the following
|
||||
* sequence. Otherwise, additional bytes may be sent by the
|
||||
* device.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_I2C_POLLED
|
||||
irqstate_t state = irqsave();
|
||||
#endif
|
||||
|
||||
/* Receive a byte */
|
||||
|
||||
*priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
|
||||
|
||||
/* Disable acknowledge when last byte is to be received */
|
||||
|
||||
priv->dcnt--;
|
||||
if (priv->dcnt == 1)
|
||||
{
|
||||
stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0);
|
||||
}
|
||||
priv->dcnt--;
|
||||
|
||||
#ifdef CONFIG_I2C_POLLED
|
||||
irqrestore(state);
|
||||
#endif
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1444,6 +1408,7 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
|
|||
/* Enable power and reset the peripheral */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit);
|
||||
|
||||
modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit);
|
||||
modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0);
|
||||
|
||||
|
|
@ -1463,10 +1428,10 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
|
|||
/* Attach ISRs */
|
||||
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
irq_attach(priv->config->ev_irq, priv->config->isr);
|
||||
irq_attach(priv->config->er_irq, priv->config->isr);
|
||||
up_enable_irq(priv->config->ev_irq);
|
||||
up_enable_irq(priv->config->er_irq);
|
||||
irq_attach(priv->config->ev_irq, priv->config->isr);
|
||||
irq_attach(priv->config->er_irq, priv->config->isr);
|
||||
up_enable_irq(priv->config->ev_irq);
|
||||
up_enable_irq(priv->config->er_irq);
|
||||
#endif
|
||||
|
||||
/* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz
|
||||
|
|
@ -1496,23 +1461,17 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
|
|||
|
||||
stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0);
|
||||
|
||||
/* Unconfigure GPIO pins */
|
||||
|
||||
stm32_unconfiggpio(priv->config->scl_pin);
|
||||
stm32_unconfiggpio(priv->config->sda_pin);
|
||||
|
||||
/* Disable and detach interrupts */
|
||||
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
up_disable_irq(priv->config->ev_irq);
|
||||
up_disable_irq(priv->config->er_irq);
|
||||
irq_detach(priv->config->ev_irq);
|
||||
irq_detach(priv->config->er_irq);
|
||||
#endif
|
||||
|
||||
/* Disable clocking */
|
||||
|
||||
modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
@ -1574,14 +1533,14 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
|||
struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev;
|
||||
FAR struct stm32_i2c_priv_s *priv = inst->priv;
|
||||
uint32_t status = 0;
|
||||
uint32_t ahbenr;
|
||||
//uint32_t ahbenr;
|
||||
int errval = 0;
|
||||
|
||||
ASSERT(count);
|
||||
|
||||
/* Disable FSMC that shares a pin with I2C1 (LBAR) */
|
||||
|
||||
ahbenr = stm32_i2c_disablefsmc(priv);
|
||||
(void)stm32_i2c_disablefsmc(priv);
|
||||
|
||||
/* Wait for any STOP in progress. NOTE: If we have to disable the FSMC
|
||||
* then we cannot do this at the top of the loop, unfortunately. The STOP
|
||||
|
|
@ -1589,7 +1548,11 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
|||
*/
|
||||
|
||||
#ifndef I2C1_FSMC_CONFLICT
|
||||
stm32_i2c_sem_waitstop(priv);
|
||||
#if CONFIG_STM32_I2CTIMEOUS_START_STOP > 0
|
||||
stm32_i2c_sem_waitstop(priv, CONFIG_STM32_I2CTIMEOUS_START_STOP);
|
||||
#else
|
||||
stm32_i2c_sem_waitstop(priv, CONFIG_STM32_I2CTIMEOMS + CONFIG_STM32_I2CTIMEOSEC * 1000000);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Clear any pending error interrupts */
|
||||
|
|
@ -1610,6 +1573,22 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
|||
priv->msgv = msgs;
|
||||
priv->msgc = count;
|
||||
|
||||
/* Calculate timeout values */
|
||||
int timeout_us = 0;
|
||||
#if CONFIG_STM32_I2CTIMEOUS_PER_BYTE > 0
|
||||
/* Count the number of bytes left to process */
|
||||
int i;
|
||||
int bytecount = 10;
|
||||
for (i = 0; i < count; i++)
|
||||
{
|
||||
bytecount += msgs[i].length;
|
||||
}
|
||||
timeout_us = CONFIG_STM32_I2CTIMEOUS_PER_BYTE * bytecount;
|
||||
//i2cvdbg("i2c wait: %d\n", timeout_us);
|
||||
#else
|
||||
timeout_us = CONFIG_STM32_I2CTIMEOMS + CONFIG_STM32_I2CTIMEOSEC * 1000000;
|
||||
#endif
|
||||
|
||||
/* Reset I2C trace logic */
|
||||
|
||||
stm32_i2c_tracereset(priv);
|
||||
|
|
@ -1629,7 +1608,7 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
|||
* the BUSY flag.
|
||||
*/
|
||||
|
||||
if (stm32_i2c_sem_waitdone(priv) < 0)
|
||||
if (stm32_i2c_sem_waitdone(priv, timeout_us) < 0)
|
||||
{
|
||||
status = stm32_i2c_getstatus(priv);
|
||||
errval = ETIMEDOUT;
|
||||
|
|
@ -1644,9 +1623,7 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
|||
*/
|
||||
|
||||
stm32_i2c_clrstart(priv);
|
||||
|
||||
/* Clear busy flag in case of timeout */
|
||||
|
||||
// XXX also clear busy flag in case of timeout
|
||||
status = priv->status & 0xffff;
|
||||
}
|
||||
else
|
||||
|
|
@ -1976,15 +1953,13 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev)
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_I2C_RESET
|
||||
int up_i2creset(FAR struct i2c_dev_s * dev)
|
||||
{
|
||||
struct stm32_i2c_priv_s * priv;
|
||||
unsigned int clock_count;
|
||||
unsigned int stretch_count;
|
||||
uint32_t scl_gpio;
|
||||
uint32_t sda_gpio;
|
||||
unsigned clock_count;
|
||||
unsigned stretch_count;
|
||||
int ret = ERROR;
|
||||
irqstate_t state;
|
||||
|
||||
ASSERT(dev);
|
||||
|
||||
|
|
@ -2004,73 +1979,83 @@ int up_i2creset(FAR struct i2c_dev_s * dev)
|
|||
|
||||
stm32_i2c_deinit(priv);
|
||||
|
||||
/* Use GPIO configuration to un-wedge the bus */
|
||||
/* If possible, use GPIO configuration to un-wedge the bus */
|
||||
|
||||
scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
|
||||
sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);
|
||||
|
||||
/* Let SDA go high */
|
||||
stm32_gpiowrite(sda_gpio, 1);
|
||||
|
||||
/* Clock the bus until any slaves currently driving it let it go. */
|
||||
|
||||
clock_count = 0;
|
||||
while (!stm32_gpioread(sda_gpio))
|
||||
if ((priv->config->scl_gpio != 0) && (priv->config->sda_gpio != 0))
|
||||
{
|
||||
/* Give up if we have tried too hard */
|
||||
stm32_configgpio(priv->config->scl_gpio);
|
||||
stm32_configgpio(priv->config->sda_gpio);
|
||||
|
||||
if (clock_count++ > 10)
|
||||
{
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Sniff to make sure that clock stretching has finished.
|
||||
*
|
||||
* If the bus never relaxes, the reset has failed.
|
||||
/*
|
||||
* Clock the bus until any slaves currently driving it let it go.
|
||||
*/
|
||||
|
||||
stretch_count = 0;
|
||||
while (!stm32_gpioread(scl_gpio))
|
||||
clock_count = 0;
|
||||
while (!stm32_gpioread(priv->config->sda_gpio))
|
||||
{
|
||||
|
||||
/* Give up if we have tried too hard */
|
||||
|
||||
if (stretch_count++ > 10)
|
||||
if (clock_count++ > 1000)
|
||||
{
|
||||
goto out;
|
||||
}
|
||||
|
||||
up_udelay(10);
|
||||
/*
|
||||
* Sniff to make sure that clock stretching has finished.
|
||||
*
|
||||
* If the bus never relaxes, the reset has failed.
|
||||
*/
|
||||
|
||||
stretch_count = 0;
|
||||
while (!stm32_gpioread(priv->config->scl_gpio))
|
||||
{
|
||||
|
||||
/* Give up if we have tried too hard */
|
||||
|
||||
if (stretch_count++ > 1000)
|
||||
{
|
||||
goto out;
|
||||
}
|
||||
|
||||
up_udelay(10);
|
||||
|
||||
}
|
||||
|
||||
/* Drive SCL low */
|
||||
|
||||
stm32_gpiowrite(priv->config->scl_gpio, 0);
|
||||
up_udelay(10);
|
||||
|
||||
/* Drive SCL high again */
|
||||
|
||||
stm32_gpiowrite(priv->config->scl_gpio, 1);
|
||||
up_udelay(10);
|
||||
|
||||
}
|
||||
|
||||
/* Drive SCL low */
|
||||
/*
|
||||
* Generate a start followed by a stop to reset slave
|
||||
* state machines.
|
||||
*/
|
||||
|
||||
stm32_gpiowrite(scl_gpio, 0);
|
||||
stm32_gpiowrite(priv->config->sda_gpio, 0);
|
||||
up_udelay(10);
|
||||
stm32_gpiowrite(priv->config->scl_gpio, 0);
|
||||
up_udelay(10);
|
||||
stm32_gpiowrite(priv->config->scl_gpio, 1);
|
||||
up_udelay(10);
|
||||
stm32_gpiowrite(priv->config->sda_gpio, 1);
|
||||
up_udelay(10);
|
||||
|
||||
/* Drive SCL high again */
|
||||
/*
|
||||
* Revert the GPIO configuration.
|
||||
*/
|
||||
stm32_unconfiggpio(priv->config->sda_gpio);
|
||||
stm32_unconfiggpio(priv->config->scl_gpio);
|
||||
|
||||
stm32_gpiowrite(scl_gpio, 1);
|
||||
up_udelay(10);
|
||||
}
|
||||
|
||||
/* Generate a start followed by a stop to reset slave
|
||||
* state machines.
|
||||
*/
|
||||
|
||||
stm32_gpiowrite(sda_gpio, 0);
|
||||
up_udelay(10);
|
||||
stm32_gpiowrite(scl_gpio, 0);
|
||||
up_udelay(10);
|
||||
stm32_gpiowrite(scl_gpio, 1);
|
||||
up_udelay(10);
|
||||
stm32_gpiowrite(sda_gpio, 1);
|
||||
up_udelay(10);
|
||||
|
||||
/* Revert the GPIO configuration. */
|
||||
|
||||
stm32_unconfiggpio(sda_gpio);
|
||||
stm32_unconfiggpio(scl_gpio);
|
||||
|
||||
/* Re-init the port */
|
||||
|
||||
stm32_i2c_init(priv);
|
||||
|
|
@ -2078,11 +2063,11 @@ int up_i2creset(FAR struct i2c_dev_s * dev)
|
|||
|
||||
out:
|
||||
|
||||
/* Release the port for re-use by other clients */
|
||||
/* release the port for re-use by other clients */
|
||||
|
||||
stm32_i2c_sem_post(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_I2C_RESET */
|
||||
|
||||
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */
|
||||
#endif /* defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) */
|
||||
|
|
|
|||
|
|
@ -348,6 +348,16 @@ CONFIG_CAN_LOOPBACK=n
|
|||
CONFIG_CAN1_BAUD=700000
|
||||
CONFIG_CAN2_BAUD=700000
|
||||
|
||||
|
||||
# XXX remove after integration testing
|
||||
# Allow 180 us per byte, a wide margin for the 400 KHz clock we're using
|
||||
# e.g. 9.6 ms for an EEPROM page write, 0.9 ms for a MAG update
|
||||
CONFIG_STM32_I2CTIMEOUS_PER_BYTE=200
|
||||
# Constant overhead for generating I2C start / stop conditions
|
||||
CONFIG_STM32_I2CTIMEOUS_START_STOP=700
|
||||
# XXX this is bad and we want it gone
|
||||
CONFIG_I2C_WRITEREAD=y
|
||||
|
||||
#
|
||||
# I2C configuration
|
||||
#
|
||||
|
|
@ -357,14 +367,32 @@ CONFIG_I2C_TRANSFER=y
|
|||
CONFIG_I2C_TRACE=n
|
||||
CONFIG_I2C_RESET=y
|
||||
|
||||
|
||||
|
||||
# XXX re-enable after integration testing
|
||||
|
||||
#
|
||||
# I2C configuration
|
||||
#
|
||||
#CONFIG_I2C=y
|
||||
#CONFIG_I2C_POLLED=y
|
||||
#CONFIG_I2C_TRANSFER=y
|
||||
#CONFIG_I2C_TRACE=n
|
||||
#CONFIG_I2C_RESET=y
|
||||
|
||||
# Dynamic timeout
|
||||
#CONFIG_STM32_I2C_DYNTIMEO=y
|
||||
#CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=500
|
||||
#CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=200
|
||||
|
||||
# Fixed per-transaction timeout
|
||||
CONFIG_STM32_I2CTIMEOSEC=0
|
||||
CONFIG_STM32_I2CTIMEOMS=10
|
||||
#CONFIG_STM32_I2CTIMEOSEC=0
|
||||
#CONFIG_STM32_I2CTIMEOMS=10
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#
|
||||
# General build options
|
||||
|
|
|
|||
Loading…
Reference in New Issue