forked from Archive/PX4-Autopilot
Add an interface to the STM32 I2C driver that provides a way to reset the driver and the bus.
This can be used to unwedge the bus when transactions are failing due to a device being out of sync.
This commit is contained in:
px4dev
parent
39eb2a3ba0
commit
6669c7faa9
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@ -196,11 +196,29 @@ struct stm32_trace_s
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uint32_t time; /* First of event or first status */
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};
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/* I2C Device hardware configuration */
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struct stm32_i2c_config_s
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{
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uint32_t base; /* I2C base address */
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#ifndef CONFIG_I2C_POLLED
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int ( *isr)(int, void *); /* Interrupt handler */
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#endif
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uint32_t clk_bit; /* Clock enable bit */
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uint32_t reset_bit; /* Reset bit */
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uint32_t scl_pin; /* GPIO configuration for SCL as SCL */
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uint32_t scl_gpio; /* GPIO configuration for SCL as a GPIO */
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uint32_t sda_pin; /* GPIO configuration for SDA as SDA */
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uint32_t sda_gpio; /* GPIO configuration for SDA as a GPIO */
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uint32_t ev_irq; /* Event IRQ */
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uint32_t er_irq; /* Error IRQ */
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};
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/* I2C Device Private Data */
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struct stm32_i2c_priv_s
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{
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uint32_t base; /* I2C base address */
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const struct stm32_i2c_config_s *config; /* Port configuration */
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int refs; /* Referernce count */
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sem_t sem_excl; /* Mutual exclusion semaphore */
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#ifndef CONFIG_I2C_POLLED
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@ -311,9 +329,32 @@ static int stm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *m
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************************************************************************************/
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#ifdef CONFIG_STM32_I2C1
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struct stm32_i2c_priv_s stm32_i2c1_priv =
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# ifndef GPIO_I2C1_SCL_GPIO
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# define GPIO_I2C1_SCL_GPIO 0
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# endif
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# ifndef GPIO_I2C1_SDA_GPIO
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# define GPIO_I2C1_SDA_GPIO 0
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# endif
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static const struct stm32_i2c_config_s stm32_i2c1_config =
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{
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.base = STM32_I2C1_BASE,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c1_isr,
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#endif
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.clk_bit = RCC_APB1ENR_I2C1EN,
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.reset_bit = RCC_APB1RSTR_I2C1RST,
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.scl_pin = GPIO_I2C1_SCL,
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.scl_gpio = GPIO_I2C1_SCL_GPIO,
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.sda_pin = GPIO_I2C1_SDA,
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.sda_gpio = GPIO_I2C1_SDA_GPIO,
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.ev_irq = STM32_IRQ_I2C1EV,
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.er_irq = STM32_IRQ_I2C1ER
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};
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struct stm32_i2c_priv_s stm32_i2c1_priv =
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{
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.config = &stm32_i2c1_config,
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.refs = 0,
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.intstate = INTSTATE_IDLE,
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.msgc = 0,
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@ -326,9 +367,32 @@ struct stm32_i2c_priv_s stm32_i2c1_priv =
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#endif
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#ifdef CONFIG_STM32_I2C2
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struct stm32_i2c_priv_s stm32_i2c2_priv =
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# ifndef GPIO_I2C2_SCL_GPIO
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# define GPIO_I2C2_SCL_GPIO 0
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# endif
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# ifndef GPIO_I2C2_SDA_GPIO
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# define GPIO_I2C2_SDA_GPIO 0
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# endif
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static const struct stm32_i2c_config_s stm32_i2c2_config =
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{
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.base = STM32_I2C2_BASE,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c2_isr,
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#endif
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.clk_bit = RCC_APB1ENR_I2C2EN,
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.reset_bit = RCC_APB1RSTR_I2C2RST,
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.scl_pin = GPIO_I2C2_SCL,
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.scl_gpio = GPIO_I2C2_SCL_GPIO,
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.sda_pin = GPIO_I2C2_SDA,
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.sda_gpio = GPIO_I2C2_SDA_GPIO,
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.ev_irq = STM32_IRQ_I2C2EV,
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.er_irq = STM32_IRQ_I2C2ER
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};
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struct stm32_i2c_priv_s stm32_i2c2_priv =
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{
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.config = &stm32_i2c2_config,
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.refs = 0,
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.intstate = INTSTATE_IDLE,
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.msgc = 0,
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@ -341,9 +405,32 @@ struct stm32_i2c_priv_s stm32_i2c2_priv =
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#endif
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#ifdef CONFIG_STM32_I2C3
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struct stm32_i2c_priv_s stm32_i2c3_priv =
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# ifndef GPIO_I2C3_SCL_GPIO
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# define GPIO_I2C3_SCL_GPIO 0
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# endif
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# ifndef GPIO_I2C3_SDA_GPIO
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# define GPIO_I2C3_SDA_GPIO 0
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# endif
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static const struct stm32_i2c_config_s stm32_i2c3_config =
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{
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.base = STM32_I2C3_BASE,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c3_isr,
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#endif
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.clk_bit = RCC_APB1ENR_I2C3EN,
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.reset_bit = RCC_APB1RSTR_I2C3RST,
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.scl_pin = GPIO_I2C3_SCL,
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.scl_gpio = GPIO_I2C3_SCL_GPIO,
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.sda_pin = GPIO_I2C3_SDA,
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.sda_gpio = GPIO_I2C3_SDA_GPIO,
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.ev_irq = STM32_IRQ_I2C3EV,
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.er_irq = STM32_IRQ_I2C3ER
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};
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struct stm32_i2c_priv_s stm32_i2c3_priv =
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{
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.config = &stm32_i2c3_config,
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.refs = 0,
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.intstate = INTSTATE_IDLE,
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.msgc = 0,
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@ -355,7 +442,6 @@ struct stm32_i2c_priv_s stm32_i2c3_priv =
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};
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#endif
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/* Device Structures, Instantiation */
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struct i2c_ops_s stm32_i2c_ops =
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@ -391,7 +477,7 @@ struct i2c_ops_s stm32_i2c_ops =
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static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
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uint8_t offset)
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{
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return getreg16(priv->base + offset);
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return getreg16(priv->config->base + offset);
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}
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/************************************************************************************
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@ -405,7 +491,7 @@ static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
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static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
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uint16_t value)
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{
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putreg16(value, priv->base + offset);
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putreg16(value, priv->config->base + offset);
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}
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/************************************************************************************
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@ -420,7 +506,7 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
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uint8_t offset, uint16_t clearbits,
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uint16_t setbits)
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{
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modifyreg16(priv->base + offset, clearbits, setbits);
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modifyreg16(priv->config->base + offset, clearbits, setbits);
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}
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/************************************************************************************
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@ -986,7 +1072,7 @@ static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv)
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/* Is this I2C1 */
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#ifdef CONFIG_STM32_I2C2
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if (priv->base == STM32_I2C1_BASE)
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if (priv->config->base == STM32_I2C1_BASE)
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#endif
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{
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/* Disable FSMC unconditionally */
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@ -1310,114 +1396,35 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
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{
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/* Power-up and configure GPIOs */
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switch (priv->base)
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{
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#ifdef CONFIG_STM32_I2C1
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case STM32_I2C1_BASE:
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/* Enable power and reset the peripheral */
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/* Enable power and reset the peripheral */
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modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit);
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modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C1EN);
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modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit);
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modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0);
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modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_I2C1RST);
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modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST, 0);
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/* Configure pins */
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if (stm32_configgpio(GPIO_I2C1_SCL) < 0)
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{
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return ERROR;
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}
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if (stm32_configgpio(GPIO_I2C1_SDA) < 0)
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{
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stm32_unconfiggpio(GPIO_I2C1_SCL);
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return ERROR;
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}
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/* Attach ISRs */
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#ifndef CONFIG_I2C_POLLED
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irq_attach(STM32_IRQ_I2C1EV, stm32_i2c1_isr);
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irq_attach(STM32_IRQ_I2C1ER, stm32_i2c1_isr);
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up_enable_irq(STM32_IRQ_I2C1EV);
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up_enable_irq(STM32_IRQ_I2C1ER);
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#endif
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break;
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#endif
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/* Configure pins */
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#ifdef CONFIG_STM32_I2C2
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case STM32_I2C2_BASE:
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/* Enable power and reset the peripheral */
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modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C2EN);
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modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_I2C2RST);
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modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST, 0);
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/* Configure pins */
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if (stm32_configgpio(GPIO_I2C2_SCL) < 0)
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{
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return ERROR;
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}
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if (stm32_configgpio(GPIO_I2C2_SDA) < 0)
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{
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stm32_unconfiggpio(GPIO_I2C2_SCL);
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return ERROR;
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}
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/* Attach ISRs */
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#ifndef CONFIG_I2C_POLLED
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irq_attach(STM32_IRQ_I2C2EV, stm32_i2c2_isr);
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irq_attach(STM32_IRQ_I2C2ER, stm32_i2c2_isr);
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up_enable_irq(STM32_IRQ_I2C2EV);
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up_enable_irq(STM32_IRQ_I2C2ER);
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#endif
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break;
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#endif
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#ifdef CONFIG_STM32_I2C3
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case STM32_I2C3_BASE:
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/* Enable power and reset the peripheral */
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modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C3EN);
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modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_I2C3RST);
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modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_I2C3RST, 0);
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/* Configure pins */
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if (stm32_configgpio(GPIO_I2C3_SCL) < 0)
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{
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return ERROR;
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}
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if (stm32_configgpio(GPIO_I2C3_SDA) < 0)
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{
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stm32_unconfiggpio(GPIO_I2C3_SCL);
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return ERROR;
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}
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/* Attach ISRs */
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#ifndef CONFIG_I2C_POLLED
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irq_attach(STM32_IRQ_I2C3EV, stm32_i2c3_isr);
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irq_attach(STM32_IRQ_I2C3ER, stm32_i2c3_isr);
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up_enable_irq(STM32_IRQ_I2C3EV);
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up_enable_irq(STM32_IRQ_I2C3ER);
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#endif
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break;
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#endif
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default:
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return ERROR;
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if (stm32_configgpio(priv->config->scl_pin) < 0)
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{
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return ERROR;
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}
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if (stm32_configgpio(priv->config->sda_pin) < 0)
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{
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stm32_unconfiggpio(priv->config->scl_pin);
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return ERROR;
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}
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/* Attach ISRs */
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#ifndef CONFIG_I2C_POLLED
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irq_attach(priv->config->ev_irq, priv->config->isr);
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irq_attach(priv->config->er_irq, priv->config->isr);
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up_enable_irq(priv->config->ev_irq);
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up_enable_irq(priv->config->er_irq);
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#endif
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/* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz
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* or 4 MHz for 400 kHz. This also disables all I2C interrupts.
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*/
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@ -1445,56 +1452,16 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
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stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0);
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switch (priv->base)
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{
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#ifdef CONFIG_STM32_I2C1
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case STM32_I2C1_BASE:
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stm32_unconfiggpio(GPIO_I2C1_SCL);
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stm32_unconfiggpio(GPIO_I2C1_SDA);
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stm32_unconfiggpio(priv->config->scl_pin);
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stm32_unconfiggpio(priv->config->sda_pin);
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#ifndef CONFIG_I2C_POLLED
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up_disable_irq(STM32_IRQ_I2C1EV);
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up_disable_irq(STM32_IRQ_I2C1ER);
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irq_detach(STM32_IRQ_I2C1EV);
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irq_detach(STM32_IRQ_I2C1ER);
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up_disable_irq(priv->config->ev_irq);
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up_disable_irq(priv->config->er_irq);
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irq_detach(priv->config->ev_irq);
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irq_detach(priv->config->er_irq);
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#endif
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modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_I2C1EN, 0);
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break;
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#endif
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#ifdef CONFIG_STM32_I2C2
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case STM32_I2C2_BASE:
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stm32_unconfiggpio(GPIO_I2C2_SCL);
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stm32_unconfiggpio(GPIO_I2C2_SDA);
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#ifndef CONFIG_I2C_POLLED
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up_disable_irq(STM32_IRQ_I2C2EV);
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up_disable_irq(STM32_IRQ_I2C2ER);
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irq_detach(STM32_IRQ_I2C2EV);
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irq_detach(STM32_IRQ_I2C2ER);
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#endif
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modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_I2C2EN, 0);
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break;
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#endif
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#ifdef CONFIG_STM32_I2C3
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case STM32_I2C3_BASE:
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stm32_unconfiggpio(GPIO_I2C3_SCL);
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stm32_unconfiggpio(GPIO_I2C3_SDA);
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#ifndef CONFIG_I2C_POLLED
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up_disable_irq(STM32_IRQ_I2C3EV);
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up_disable_irq(STM32_IRQ_I2C3ER);
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irq_detach(STM32_IRQ_I2C3EV);
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irq_detach(STM32_IRQ_I2C3ER);
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#endif
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modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_I2C3EN, 0);
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break;
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#endif
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default:
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return ERROR;
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}
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modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
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return OK;
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}
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@ -1979,159 +1946,103 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev)
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int up_i2creset(FAR struct i2c_dev_s * dev)
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{
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unsigned clock_count;
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unsigned stretch_count;
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// ASSERT(dev);
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// stm32_i2c_sem_wait(dev); /* ensure that address or flags don't change meanwhile */
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struct stm32_i2c_priv_s * priv = NULL;
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// struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev;
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// FAR struct stm32_i2c_priv_s *priv = inst->priv;
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// /* Clear any pending error interrupts */
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// stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0);
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// /* "Note: When the STOP, START or PEC bit is set, the software must
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// * not perform any write access to I2C_CR1 before this bit is
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// * cleared by hardware. Otherwise there is a risk of setting a
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// * second STOP, START or PEC request." However, if the bits are
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// * not cleared by hardware, then we will have to do that from hardware.
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// */
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// stm32_i2c_clrstart(priv);
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// /* Reset peripheral */
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// uint16_t cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET);
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// /* Set reset flag */
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// cr1 &= I2C_CR1_SWRST;
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// stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1);
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// /* Clear CR1 */
|
||||
// stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0);
|
||||
|
||||
// switch (priv->base)
|
||||
// {
|
||||
// case STM32_I2C1_BASE:
|
||||
// modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_I2C1RST);
|
||||
// modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST, 0);
|
||||
// break;
|
||||
// case STM32_I2C2_BASE:
|
||||
// modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_I2C2RST);
|
||||
// modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST, 0);
|
||||
// break;
|
||||
// case STM32_I2C3_BASE:
|
||||
// modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_I2C3RST);
|
||||
// modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_I2C3RST, 0);
|
||||
// break;
|
||||
// }
|
||||
|
||||
|
||||
|
||||
// stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, (STM32_PCLK1_FREQUENCY / 1000000));
|
||||
// stm32_i2c_setclock(priv, inst->frequency);
|
||||
// inst->flags = 0;
|
||||
|
||||
// /* Enable I2C */
|
||||
|
||||
// stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int irqs;
|
||||
|
||||
ASSERT(dev);
|
||||
|
||||
/* Decrement refs and check for underflow */
|
||||
|
||||
if (((struct stm32_i2c_inst_s *)dev)->priv->refs == 0)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
irqs = irqsave();
|
||||
|
||||
irqrestore(irqs);
|
||||
|
||||
/* Disable power and other HW resource (GPIO's) */
|
||||
|
||||
//stm32_i2c_deinit( ((struct stm32_i2c_inst_s *)dev)->priv );
|
||||
|
||||
/* Release unused resources */
|
||||
|
||||
//stm32_i2c_sem_destroy( (struct i2c_dev_s *)dev );
|
||||
|
||||
struct stm32_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */
|
||||
struct stm32_i2c_inst_s * inst = NULL; /* device, single instance */
|
||||
|
||||
#if STM32_PCLK1_FREQUENCY < 4000000
|
||||
# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
|
||||
#endif
|
||||
|
||||
#if STM32_PCLK1_FREQUENCY < 2000000
|
||||
# warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
|
||||
return NULL;
|
||||
#endif
|
||||
|
||||
/* Get I2C private structure */
|
||||
|
||||
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
|
||||
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
|
||||
|
||||
// switch (port)
|
||||
// {
|
||||
// #ifdef CONFIG_STM32_I2C1
|
||||
// case 1:
|
||||
// priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
|
||||
// break;
|
||||
// #endif
|
||||
// #ifdef CONFIG_STM32_I2C2
|
||||
// case 2:
|
||||
// priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
|
||||
// break;
|
||||
// #endif
|
||||
// #ifdef CONFIG_STM32_I2C3
|
||||
// case 3:
|
||||
// priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
|
||||
// break;
|
||||
// #endif
|
||||
// default:
|
||||
// return NULL;
|
||||
// }
|
||||
/* De-init the port */
|
||||
|
||||
/* Allocate instance */
|
||||
inst = (struct stm32_i2c_inst_s *)dev;
|
||||
stm32_i2c_deinit(priv);
|
||||
|
||||
/* Initialize instance */
|
||||
/* If possible, use GPIO configuration to un-wedge the bus */
|
||||
|
||||
inst->ops = &stm32_i2c_ops;
|
||||
inst->priv = priv;
|
||||
inst->frequency = 100000;
|
||||
inst->address = 0;
|
||||
inst->flags = 0;
|
||||
|
||||
/* Init private data for the first time, increment refs count,
|
||||
* power-up hardware and configure GPIOs.
|
||||
*/
|
||||
|
||||
irqs = irqsave();
|
||||
|
||||
if ((volatile int)priv->refs++ == 0)
|
||||
if ((priv->config->scl_gpio != 0) && (priv->config->sda_gpio != 0))
|
||||
{
|
||||
stm32_i2c_sem_init( (struct i2c_dev_s *)inst );
|
||||
stm32_i2c_init( priv );
|
||||
stm32_configgpio(priv->config->scl_gpio);
|
||||
stm32_configgpio(priv->config->sda_gpio);
|
||||
|
||||
/*
|
||||
* Clock the bus until any slaves currently driving it let it go.
|
||||
*/
|
||||
|
||||
clock_count = 0;
|
||||
while (!stm32_gpioread(priv->config->sda_gpio))
|
||||
{
|
||||
|
||||
/* Give up if we have tried too hard */
|
||||
|
||||
if (clock_count++ > 1000)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sniff to make sure that clock stretching has finished.
|
||||
*
|
||||
* If the bus never relaxes, the reset has failed.
|
||||
*/
|
||||
|
||||
stretch_count = 0;
|
||||
while (!stm32_gpioread(priv->config->scl_gpio))
|
||||
{
|
||||
|
||||
/* Give up if we have tried too hard */
|
||||
|
||||
if (stretch_count++ > 1000)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
up_udelay(10);
|
||||
|
||||
}
|
||||
|
||||
/* Drive SCL low */
|
||||
|
||||
stm32_gpiowrite(priv->config->scl_gpio, 0);
|
||||
up_udelay(10);
|
||||
|
||||
/* Drive SCL high again */
|
||||
|
||||
stm32_gpiowrite(priv->config->scl_gpio, 1);
|
||||
up_udelay(10);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Generate a start followed by a stop to reset slave
|
||||
* state machines.
|
||||
*/
|
||||
|
||||
stm32_gpiowrite(priv->config->sda_gpio, 0);
|
||||
up_udelay(10);
|
||||
stm32_gpiowrite(priv->config->scl_gpio, 0);
|
||||
up_udelay(10);
|
||||
stm32_gpiowrite(priv->config->scl_gpio, 1);
|
||||
up_udelay(10);
|
||||
stm32_gpiowrite(priv->config->sda_gpio, 1);
|
||||
up_udelay(10);
|
||||
|
||||
/*
|
||||
* Revert the GPIO configuration.
|
||||
*/
|
||||
stm32_unconfiggpio(priv->config->sda_gpio);
|
||||
stm32_unconfiggpio(priv->config->scl_gpio);
|
||||
|
||||
}
|
||||
|
||||
irqrestore(irqs);
|
||||
|
||||
/* Re-init the port */
|
||||
|
||||
stm32_i2c_init(priv);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C2) */
|
||||
#endif /* defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) */
|
||||
|
|
|
|||
|
|
@ -325,6 +325,23 @@ EXTERN FAR struct i2c_dev_s *up_i2cinitialize(int port);
|
|||
|
||||
EXTERN int up_i2cuninitialize(FAR struct i2c_dev_s * dev);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_i2creset
|
||||
*
|
||||
* Description:
|
||||
* Reset the port and the associated I2C bus. Useful when the bus or an
|
||||
* attached slave has become wedged or unresponsive.
|
||||
*
|
||||
* Input Parameter:
|
||||
* Device structure as returned by the up_i2cinitalize()
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success, ERROR if the bus cannot be unwedged.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN int up_i2creset(FAR struct i2c_dev_s * dev);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue