From 5a714f6d99806da8847905251e82a6105aa045c1 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 20 Dec 2011 18:28:50 +0000 Subject: [PATCH] Finishes the PWM driver for the STM32 git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4206 7fd9a85b-ad96-42d3-883c-3090e2eb8679 --- nuttx/Documentation/NuttX.html | 16 ++++++++------ nuttx/Documentation/README.html | 9 +++++++- nuttx/arch/arm/src/stm32/stm32_pwm.c | 24 ++++++++++----------- nuttx/configs/README.txt | 10 +++++++-- nuttx/configs/hymini-stm32v/include/board.h | 14 ++++++++++++ nuttx/configs/stm3210e-eval/include/board.h | 15 +++++++++++++ nuttx/configs/stm3240g-eval/README.txt | 16 ++++++++++++++ nuttx/configs/stm3240g-eval/include/board.h | 24 +++++++++++++++++++-- nuttx/configs/vsn/include/board.h | 14 ++++++++++++ 9 files changed, 119 insertions(+), 23 deletions(-) diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index d3d4af4f12..585b8e6583 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -983,7 +983,7 @@
  • ARM7TDMI (4)
  • ARM920T (1)
  • ARM926EJS (3)
    • -
  • ARM Cortex-M3 (10)
    • +
  • ARM Cortex-M3 (11)
  • ARM Cortex-M4 (4)
  • Atmel AVR @@ -1385,19 +1385,23 @@

    STMicro STM32F103x. - Support for three MCUs and two board configurations are available. - MCU support includes: STM32F103ZET6, STM32F103RET6, and STM32F107VC. - Board support includes: + Support for four MCUs and three board configurations are available. + MCU support includes: STM32F103ZET6, STM32F103RET6, STM32F103VCT, and STM32F107VC. + Boards supported include:

    1. - This port uses the STMicro STM3210E-EVAL development board that + A port for the STMicro STM3210E-EVAL development board that features the STM32F103ZET6 MCU.
    2. - ISOTEL NetClamps VSN V1.2 ready2go sensor network platform based on the + The ISOTEL NetClamps VSN V1.2 ready2go sensor network platform based on the STMicro STM32F103RET6. Contributed by Uros Platise.
      3. +
    3. + A port for the HY-Mini STM32v board. This board is based on the + STM32F103VCT chip. Contributed by Laurent Latil. +

    These ports uses a GNU arm-elf toolchain* under either Linux or Cygwin (with native Windows GNU diff --git a/nuttx/Documentation/README.html b/nuttx/Documentation/README.html index c8b740c23d..33b5f2d10e 100755 --- a/nuttx/Documentation/README.html +++ b/nuttx/Documentation/README.html @@ -8,7 +8,7 @@

    NuttX README Files

    -

    Last Updated: October 10, 2011

    +

    Last Updated: December 20, 2011

    @@ -79,6 +79,11 @@ | | | |- ostest/README.txt | | | |- poll/README.txt | | | `- README.txt + | | |- hymini-stm32v/ + | | | |- include/README.txt + | | | |- RIDE/README.txt + | | | |- src/README.txt + | | | `- README.txt | | |- kwikstik-k40/ | | | `- README.txt | | |- lm3s6965-ek/ @@ -154,6 +159,8 @@ | | | |- RIDE/README.txt | | | |- src/README.txt | | | `- README.txt + | | |- stm3240g-eval/ + | | | `- README.txt | | |- sure-pic32mx/ | | | `- README.txt | | |- twr-k60n512/ diff --git a/nuttx/arch/arm/src/stm32/stm32_pwm.c b/nuttx/arch/arm/src/stm32/stm32_pwm.c index 379ec2ba46..35524226c0 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pwm.c +++ b/nuttx/arch/arm/src/stm32/stm32_pwm.c @@ -146,7 +146,7 @@ static struct stm32_pwmtimer_s g_pwm1dev = .channel = CONFIG_STM32_TIM1_CHANNEL, .base = STM32_TIM1_BASE, .pincfg = PWM_TIM1_PINCFG, - .pclk = STM32_PCLK2_FREQUENCY, + .pclk = STM32_APB2_TIM1_CLKIN, }; #endif @@ -158,7 +158,7 @@ static struct stm32_pwmtimer_s g_pwm2dev = .channel = CONFIG_STM32_TIM2_CHANNEL, .base = STM32_TIM2_BASE, .pincfg = PWM_TIM2_PINCFG, - .pclk = STM32_PCLK1_FREQUENCY, + .pclk = STM32_APB1_TIM2_CLKIN, }; #endif @@ -170,7 +170,7 @@ static struct stm32_pwmtimer_s g_pwm3dev = .channel = CONFIG_STM32_TIM3_CHANNEL, .base = STM32_TIM3_BASE, .pincfg = PWM_TIM3_PINCFG, - .pclk = STM32_PCLK1_FREQUENCY, + .pclk = STM32_APB1_TIM3_CLKIN, }; #endif @@ -182,7 +182,7 @@ static struct stm32_pwmtimer_s g_pwm4dev = .channel = CONFIG_STM32_TIM4_CHANNEL, .base = STM32_TIM4_BASE, .pincfg = PWM_TIM4_PINCFG, - .pclk = STM32_PCLK1_FREQUENCY, + .pclk = STM32_APB1_TIM4_CLKIN, }; #endif @@ -194,7 +194,7 @@ static struct stm32_pwmtimer_s g_pwm5dev = .channel = CONFIG_STM32_TIM5_CHANNEL, .base = STM32_TIM5_BASE, .pincfg = PWM_TIM5_PINCFG, - .pclk = STM32_PCLK1_FREQUENCY, + .pclk = STM32_APB1_TIM5_CLKIN, }; #endif @@ -206,7 +206,7 @@ static struct stm32_pwmtimer_s g_pwm8dev = .channel = CONFIG_STM32_TIM8_CHANNEL, .base = STM32_TIM8_BASE, .pincfg = PWM_TIM8_PINCFG, - .pclk = STM32_PCLK2_FREQUENCY, + .pclk = STM32_APB2_TIM8_CLKIN, }; #endif @@ -218,7 +218,7 @@ static struct stm32_pwmtimer_s g_pwm9dev = .channel = CONFIG_STM32_TIM9_CHANNEL, .base = STM32_TIM9_BASE, .pincfg = PWM_TIM9_PINCFG, - .pclk = STM32_PCLK2_FREQUENCY, + .pclk = STM32_APB2_TIM9_CLKIN, }; #endif @@ -230,7 +230,7 @@ static struct stm32_pwmtimer_s g_pwm10dev = .channel = CONFIG_STM32_TIM10_CHANNEL, .base = STM32_TIM10_BASE, .pincfg = PWM_TIM10_PINCFG, - .pclk = STM32_PCLK2_FREQUENCY, + .pclk = STM32_APB2_TIM10_CLKIN, }; #endif @@ -242,7 +242,7 @@ static struct stm32_pwmtimer_s g_pwm11dev = .channel = CONFIG_STM32_TIM11_CHANNEL, .base = STM32_TIM11_BASE, .pincfg = PWM_TIM11_PINCFG, - .pclk = STM32_PCLK2_FREQUENCY, + .pclk = STM32_APB2_TIM11_CLKIN, }; #endif @@ -254,7 +254,7 @@ static struct stm32_pwmtimer_s g_pwm12dev = .channel = CONFIG_STM32_TIM12_CHANNEL, .base = STM32_TIM12_BASE, .pincfg = PWM_TIM12_PINCFG, - .pclk = STM32_PCLK1_FREQUENCY, + .pclk = STM32_APB1_TIM12_CLKIN, }; #endif @@ -266,7 +266,7 @@ static struct stm32_pwmtimer_s g_pwm13dev = .channel = CONFIG_STM32_TIM13_CHANNEL, .base = STM32_TIM13_BASE, .pincfg = PWM_TIM13_PINCFG, - .pclk = STM32_PCLK1_FREQUENCY, + .pclk = STM32_APB1_TIM13_CLKIN, }; #endif @@ -278,7 +278,7 @@ static struct stm32_pwmtimer_s g_pwm14dev = .channel = CONFIG_STM32_TIM14_CHANNEL, .base = STM32_TIM14_BASE, .pincfg = PWM_TIM14_PINCFG, - .pclk = STM32_PCLK1_FREQUENCY, + .pclk = STM32_APB1_TIM14_CLKIN, }; #endif diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index aa9d00cf38..a85348babe 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -1237,7 +1237,8 @@ configs/ez80f0910200zco tools. The development environment is Cygwin under WinXP. configs/hymini-stm32v - A configuration for the HY-Mini STM32v board. + A configuration for the HY-Mini STM32v board. This board is based on the + STM32F103VCT chip. configs/kwikstik-k40. Kinetis K40 Cortex-M4 MCU. This port uses the FreeScale KwikStik-K40 @@ -1249,7 +1250,7 @@ configs/lm3s6965-ek arm-elf toolchain*. STATUS: This port is complete and mature. configs/lm3s8962-ek - Stellaris LMS38962 Evaluation Kit + Stellaris LMS38962 Evaluation Kit. configs/lpcxpresso-lpc1768 Embedded Artists base board with NXP LPCExpresso LPC1768. This board @@ -1380,6 +1381,11 @@ configs/stm3210e-evel microcontroller (ARM Cortex-M3). This port uses the GNU Cortex-M3 toolchain. +configs/stm32140g-eval + STMicro STM3210G-EVAL development board based on the STMicro STM32F103ZET6 + microcontroller (ARM Cortex-M4 with FPU). This port uses a GNU Cortex-M4 + toolchain (such as CodeSourcery). + configs/sure-pic32mx The "Advanced USB Storage Demo Board," Model DB-DP11215, from Sure Electronics (http://www.sureelectronics.net/). This board features diff --git a/nuttx/configs/hymini-stm32v/include/board.h b/nuttx/configs/hymini-stm32v/include/board.h index fbecc0b6c1..719ad1c740 100755 --- a/nuttx/configs/hymini-stm32v/include/board.h +++ b/nuttx/configs/hymini-stm32v/include/board.h @@ -88,11 +88,25 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK #define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) +/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + /* USB divider -- Divide PLL clock by 1.5 */ #define STM32_CFGR_USBPRE 0 diff --git a/nuttx/configs/stm3210e-eval/include/board.h b/nuttx/configs/stm3210e-eval/include/board.h index 02db848fed..653ec89991 100755 --- a/nuttx/configs/stm3210e-eval/include/board.h +++ b/nuttx/configs/stm3210e-eval/include/board.h @@ -82,12 +82,27 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK #define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) +/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + /* USB divider -- Divide PLL clock by 1.5 */ #define STM32_CFGR_USBPRE 0 diff --git a/nuttx/configs/stm3240g-eval/README.txt b/nuttx/configs/stm3240g-eval/README.txt index ac3ebb1033..746d0e5eca 100755 --- a/nuttx/configs/stm3240g-eval/README.txt +++ b/nuttx/configs/stm3240g-eval/README.txt @@ -14,6 +14,7 @@ Contents - STM3240G-EVAL-specific Configuration Options - LEDs - Ethernet + - PWM - Configurations Development Environment @@ -203,6 +204,21 @@ events as follows: on a small proportion of the time. *** LED2 may also flicker normally if signals are processed. +PWM +=== + +The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output +a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this +purpose: + + PD13 FSMC_A18 / MC_TIM4_CH2 pin 33 (EnB) + +FSMC must be disabled in this case! PD13 is available at: + + Daughterboard Extension Connector, CN3, pin 32 - available + TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD. + Motor Control Connector CN15, pin 33 -- no available unless to connect SB14. + STM3240G-EVAL-specific Configuration Options ============================================ diff --git a/nuttx/configs/stm3240g-eval/include/board.h b/nuttx/configs/stm3240g-eval/include/board.h index 4002f918a3..046691dd9f 100755 --- a/nuttx/configs/stm3240g-eval/include/board.h +++ b/nuttx/configs/stm3240g-eval/include/board.h @@ -126,14 +126,34 @@ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) +/* Timers driven from APB12will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 diff --git a/nuttx/configs/vsn/include/board.h b/nuttx/configs/vsn/include/board.h index 9f7ec07565..b47df4d6e7 100644 --- a/nuttx/configs/vsn/include/board.h +++ b/nuttx/configs/vsn/include/board.h @@ -97,11 +97,25 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK #define STM32_PCLK2_FREQUENCY STM32_BOARD_HCLK +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + /* APB1 clock (PCLK1) is HCLK (36MHz) */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK #define STM32_PCLK1_FREQUENCY STM32_BOARD_HCLK +/* APB1 timers 2-4 will receive PCLK1. */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + /* Timer 1..8 Frequencies */ #define STM32_TIM27_FREQUENCY (STM32_BOARD_HCLK)