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px4-firmware
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Fix the clock enable register for FMUv2 PWM outputs 1-4. 

Teach the stm32 pwm driver about the MOE bit on advanced timers.
This commit is contained in:
px4dev 2013-07-29 23:13:46 -07:00
parent 1410625dea
commit 57cbf724f1
2 changed files with 13 additions and 1 deletions
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2
src/drivers/boards/px4fmuv2/px4fmu_pwm_servo.c
View File

@ -53,7 +53,7 @@
__EXPORT const struct pwm_servo_timer pwm_timers[PWM_SERVO_MAX_TIMERS] = {
{
.base = STM32_TIM1_BASE,
.clock_register = STM32_RCC_APB1ENR,
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN
},

12
src/drivers/stm32/drv_pwm_servo.c
View File

@ -88,6 +88,7 @@
#define rCCR4(_tmr) REG(_tmr, STM32_GTIM_CCR4_OFFSET)
#define rDCR(_tmr) REG(_tmr, STM32_GTIM_DCR_OFFSET)
#define rDMAR(_tmr) REG(_tmr, STM32_GTIM_DMAR_OFFSET)
#define rBDTR(_tmr) REG(_tmr, STM32_ATIM_BDTR_OFFSET)
static void pwm_timer_init(unsigned timer);
static void pwm_timer_set_rate(unsigned timer, unsigned rate);
@ -110,6 +111,11 @@ pwm_timer_init(unsigned timer)
rCCER(timer) = 0;
rDCR(timer) = 0;
if ((pwm_timers[timer].base == STM32_TIM1_BASE) || (pwm_timers[timer].base == STM32_TIM8_BASE)) {
/* master output enable = on */
rBDTR(timer) = ATIM_BDTR_MOE;
}
/* configure the timer to free-run at 1MHz */
rPSC(timer) = (pwm_timers[timer].clock_freq / 1000000) - 1;
@ -163,6 +169,9 @@ pwm_channel_init(unsigned channel)
rCCER(timer) |= GTIM_CCER_CC4E;
break;
}
/* generate an update event; reloads the counter and all registers */
rEGR(timer) = GTIM_EGR_UG;
}
int
@ -203,6 +212,9 @@ up_pwm_servo_set(unsigned channel, servo_position_t value)
return -1;
}
/* generate an update event; reloads the counter and all registers */
rEGR(timer) = GTIM_EGR_UG;
return 0;
}