forked from Archive/PX4-Autopilot
imu/invensense/mpu6000: minor improvements
- at start perform full sensor signal path reset and wait for max time - issue full sensor reset on any error - only allocate DRDY perf counter if GPIO is available - allow running faster than accel ODR (safe limit of 2 kHz in place)
This commit is contained in:
Daniel Agar
parent
01f4486b32
commit
5286ed3a11
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@ -64,30 +64,27 @@ static constexpr float TEMPERATURE_SENSITIVITY = 340.f; // LSB/C
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static constexpr float TEMPERATURE_OFFSET = 36.53f; // C
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enum class Register : uint8_t {
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CONFIG = 0x1A,
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GYRO_CONFIG = 0x1B,
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ACCEL_CONFIG = 0x1C,
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CONFIG = 0x1A,
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GYRO_CONFIG = 0x1B,
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ACCEL_CONFIG = 0x1C,
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FIFO_EN = 0x23,
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I2C_MST_CTRL = 0x24,
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FIFO_EN = 0x23,
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INT_PIN_CFG = 0x37,
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INT_ENABLE = 0x38,
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INT_PIN_CFG = 0x37,
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INT_ENABLE = 0x38,
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INT_STATUS = 0x3A,
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TEMP_OUT_H = 0x41,
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TEMP_OUT_L = 0x42,
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TEMP_OUT_H = 0x41,
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TEMP_OUT_L = 0x42,
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SIGNAL_PATH_RESET = 0x68,
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USER_CTRL = 0x6A,
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PWR_MGMT_1 = 0x6B,
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USER_CTRL = 0x6A,
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PWR_MGMT_1 = 0x6B,
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FIFO_COUNTH = 0x72,
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FIFO_COUNTL = 0x73,
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FIFO_R_W = 0x74,
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WHO_AM_I = 0x75,
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FIFO_COUNTH = 0x72,
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FIFO_COUNTL = 0x73,
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FIFO_R_W = 0x74,
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WHO_AM_I = 0x75,
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};
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// CONFIG
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@ -124,22 +121,12 @@ enum FIFO_EN_BIT : uint8_t {
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// INT_PIN_CFG
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enum INT_PIN_CFG_BIT : uint8_t {
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INT_LEVEL = Bit7,
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INT_RD_CLEAR = Bit4,
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INT_LEVEL = Bit7,
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};
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// INT_ENABLE
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enum INT_ENABLE_BIT : uint8_t {
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FIFO_OFLOW_EN = Bit4,
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DATA_RDY_INT_EN = Bit0
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};
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// INT_STATUS
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enum INT_STATUS_BIT : uint8_t {
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FIFO_OFLOW_INT = Bit4,
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DATA_RDY_INT = Bit0,
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DATA_RDY_INT_EN = Bit0,
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};
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// SIGNAL_PATH_RESET
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@ -152,11 +139,8 @@ enum SIGNAL_PATH_RESET_BIT : uint8_t {
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// USER_CTRL
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enum USER_CTRL_BIT : uint8_t {
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FIFO_EN = Bit6,
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I2C_MST_EN = Bit5,
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I2C_IF_DIS = Bit4,
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FIFO_RESET = Bit2,
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SIG_COND_RESET = Bit0,
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};
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@ -165,8 +149,7 @@ enum PWR_MGMT_1_BIT : uint8_t {
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DEVICE_RESET = Bit7,
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SLEEP = Bit6,
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CLKSEL_2 = Bit2,
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CLKSEL_1 = Bit1,
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// CLKSEL[2:0]
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CLKSEL_0 = Bit0,
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};
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@ -48,6 +48,10 @@ MPU6000::MPU6000(I2CSPIBusOption bus_option, int bus, uint32_t device, enum Rota
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_px4_accel(get_device_id(), ORB_PRIO_HIGH, rotation),
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_px4_gyro(get_device_id(), ORB_PRIO_HIGH, rotation)
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{
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if (drdy_gpio != 0) {
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_drdy_interval_perf = perf_alloc(PC_INTERVAL, MODULE_NAME": DRDY interval");
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}
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ConfigureSampleRate(_px4_gyro.get_max_rate_hz());
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}
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@ -77,6 +81,7 @@ int MPU6000::init()
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bool MPU6000::Reset()
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{
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_state = STATE::RESET;
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DataReadyInterruptDisable();
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ScheduleClear();
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ScheduleNow();
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return true;
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@ -91,8 +96,8 @@ void MPU6000::exit_and_cleanup()
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void MPU6000::print_status()
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{
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I2CSPIDriverBase::print_status();
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PX4_INFO("FIFO empty interval: %d us (%.3f Hz)", _fifo_empty_interval_us,
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static_cast<double>(1000000 / _fifo_empty_interval_us));
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PX4_INFO("FIFO empty interval: %d us (%.3f Hz)", _fifo_empty_interval_us, 1e6 / _fifo_empty_interval_us);
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perf_print_counter(_transfer_perf);
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perf_print_counter(_bad_register_perf);
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@ -120,13 +125,17 @@ int MPU6000::probe()
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void MPU6000::RunImpl()
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{
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const hrt_abstime now = hrt_absolute_time();
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switch (_state) {
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case STATE::RESET:
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// PWR_MGMT_1: Device Reset
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RegisterWrite(Register::PWR_MGMT_1, PWR_MGMT_1_BIT::DEVICE_RESET);
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_reset_timestamp = hrt_absolute_time();
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_reset_timestamp = now;
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_consecutive_failures = 0;
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_total_failures = 0;
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_state = STATE::WAIT_FOR_RESET;
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ScheduleDelayed(100_ms);
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ScheduleDelayed(100_ms); // Wait 100ms (Document Number: RM-MPU-6000A-00 Page 41 of 46)
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break;
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case STATE::WAIT_FOR_RESET:
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@ -136,17 +145,19 @@ void MPU6000::RunImpl()
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if ((RegisterRead(Register::WHO_AM_I) == WHOAMI)
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&& (RegisterRead(Register::PWR_MGMT_1) == 0x40)) {
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// SIGNAL_PATH_RESET: ensure the reset is performed properly
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// Wakeup and reset digital signal path
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RegisterWrite(Register::PWR_MGMT_1, 0);
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RegisterWrite(Register::SIGNAL_PATH_RESET,
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SIGNAL_PATH_RESET_BIT::GYRO_RESET | SIGNAL_PATH_RESET_BIT::ACCEL_RESET | SIGNAL_PATH_RESET_BIT::TEMP_RESET);
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RegisterSetAndClearBits(Register::USER_CTRL, USER_CTRL_BIT::SIG_COND_RESET, USER_CTRL_BIT::I2C_IF_DIS);
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// if reset succeeded then configure
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_state = STATE::CONFIGURE;
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ScheduleDelayed(100_ms);
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ScheduleDelayed(100_ms); // Wait another 100ms (Document Number: RM-MPU-6000A-00 Page 41 of 46)
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} else {
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// RESET not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 100_ms) {
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if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) {
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PX4_DEBUG("Reset failed, retrying");
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_state = STATE::RESET;
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ScheduleDelayed(100_ms);
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@ -168,7 +179,7 @@ void MPU6000::RunImpl()
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_data_ready_interrupt_enabled = true;
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// backup schedule as a watchdog timeout
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ScheduleDelayed(10_ms);
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ScheduleDelayed(100_ms);
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} else {
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_data_ready_interrupt_enabled = false;
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@ -178,73 +189,87 @@ void MPU6000::RunImpl()
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FIFOReset();
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} else {
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PX4_DEBUG("Configure failed, retrying");
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// try again in 10 ms
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// CONFIGURE not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) {
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PX4_DEBUG("Configure failed, resetting");
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_state = STATE::RESET;
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} else {
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PX4_DEBUG("Configure failed, retrying");
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}
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ScheduleDelayed(10_ms);
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}
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break;
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case STATE::FIFO_READ: {
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hrt_abstime timestamp_sample = 0;
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if (_data_ready_interrupt_enabled) {
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// re-schedule as watchdog timeout
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ScheduleDelayed(10_ms);
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}
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if (_data_ready_interrupt_enabled && (hrt_elapsed_time(×tamp_sample) < (_fifo_empty_interval_us / 2))) {
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// use timestamp from data ready interrupt if enabled and seems valid
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timestamp_sample = _fifo_watermark_interrupt_timestamp;
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} else {
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// use the time now roughly corresponding with the last sample we'll pull from the FIFO
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timestamp_sample = hrt_absolute_time();
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}
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const uint16_t fifo_count = FIFOReadCount();
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const uint8_t samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) *
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SAMPLES_PER_TRANSFER; // round down to nearest
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bool failure = false;
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if (samples > FIFO_MAX_SAMPLES) {
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// not technically an overflow, but more samples than we expected or can publish
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perf_count(_fifo_overflow_perf);
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failure = true;
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FIFOReset();
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} else if (samples >= SAMPLES_PER_TRANSFER) {
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// require at least SAMPLES_PER_TRANSFER (we want at least 1 new accel sample per transfer)
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if (!FIFORead(timestamp_sample, samples)) {
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failure = true;
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_px4_accel.increase_error_count();
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_px4_gyro.increase_error_count();
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// scheduled from interrupt if _drdy_fifo_read_samples was set
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if (_drdy_fifo_read_samples.fetch_and(0) == _fifo_gyro_samples) {
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perf_count_interval(_drdy_interval_perf, now);
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}
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} else if (samples == 0) {
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failure = true;
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perf_count(_fifo_empty_perf);
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// push backup schedule back
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ScheduleDelayed(_fifo_empty_interval_us * 2);
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}
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if (failure || hrt_elapsed_time(&_last_config_check_timestamp) > 10_ms) {
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// check registers incrementally
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if (RegisterCheck(_register_cfg[_checked_register], true)) {
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_last_config_check_timestamp = timestamp_sample;
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// always check current FIFO count
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bool success = false;
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const uint16_t fifo_count = FIFOReadCount();
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if (fifo_count >= FIFO::SIZE) {
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FIFOReset();
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perf_count(_fifo_overflow_perf);
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} else if (fifo_count == 0) {
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perf_count(_fifo_empty_perf);
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} else {
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// FIFO count (size in bytes) should be a multiple of the FIFO::DATA structure
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const uint8_t samples = fifo_count / sizeof(FIFO::DATA);
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if (samples > FIFO_MAX_SAMPLES) {
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// not technically an overflow, but more samples than we expected or can publish
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FIFOReset();
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perf_count(_fifo_overflow_perf);
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} else if (samples >= 1) {
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if (FIFORead(now, samples)) {
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success = true;
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_consecutive_failures = 0;
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}
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}
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}
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if (!success) {
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_consecutive_failures++;
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_total_failures++;
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// full reset if things are failing consistently
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if (_consecutive_failures > 100 || _total_failures > 1000) {
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Reset();
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return;
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}
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}
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if (!success || hrt_elapsed_time(&_last_config_check_timestamp) > 10_ms) {
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// check configuration registers periodically or immediately following any failure
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if (RegisterCheck(_register_cfg[_checked_register])) {
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_last_config_check_timestamp = now;
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_checked_register = (_checked_register + 1) % size_register_cfg;
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} else {
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// register check failed, force reconfigure
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PX4_DEBUG("Health check failed, reconfiguring");
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_state = STATE::CONFIGURE;
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ScheduleNow();
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// register check failed, force reset
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perf_count(_bad_register_perf);
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Reset();
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}
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} else {
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// periodically update temperature (1 Hz)
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if (hrt_elapsed_time(&_temperature_update_timestamp) > 1_s) {
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// periodically update temperature (~1 Hz)
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if (hrt_elapsed_time(&_temperature_update_timestamp) >= 1_s) {
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UpdateTemperature();
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_temperature_update_timestamp = timestamp_sample;
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_temperature_update_timestamp = now;
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}
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}
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}
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@ -259,23 +284,23 @@ void MPU6000::ConfigureAccel()
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switch (AFS_SEL) {
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case AFS_SEL_2G:
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_px4_accel.set_scale(CONSTANTS_ONE_G / 16384);
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_px4_accel.set_range(2 * CONSTANTS_ONE_G);
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_px4_accel.set_scale(CONSTANTS_ONE_G / 16384.f);
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_px4_accel.set_range(2.f * CONSTANTS_ONE_G);
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break;
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case AFS_SEL_4G:
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_px4_accel.set_scale(CONSTANTS_ONE_G / 8192);
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_px4_accel.set_range(4 * CONSTANTS_ONE_G);
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_px4_accel.set_scale(CONSTANTS_ONE_G / 8192.f);
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_px4_accel.set_range(4.f * CONSTANTS_ONE_G);
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break;
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case AFS_SEL_8G:
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_px4_accel.set_scale(CONSTANTS_ONE_G / 4096);
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_px4_accel.set_range(8 * CONSTANTS_ONE_G);
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_px4_accel.set_scale(CONSTANTS_ONE_G / 4096.f);
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_px4_accel.set_range(8.f * CONSTANTS_ONE_G);
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break;
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case AFS_SEL_16G:
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_px4_accel.set_scale(CONSTANTS_ONE_G / 2048);
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_px4_accel.set_range(16 * CONSTANTS_ONE_G);
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_px4_accel.set_scale(CONSTANTS_ONE_G / 2048.f);
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_px4_accel.set_range(16.f * CONSTANTS_ONE_G);
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break;
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}
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}
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@ -310,27 +335,31 @@ void MPU6000::ConfigureGyro()
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void MPU6000::ConfigureSampleRate(int sample_rate)
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{
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if (sample_rate == 0) {
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sample_rate = 800; // default to 800 Hz
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sample_rate = 1000; // default to 1000 Hz
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}
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// round down to nearest FIFO sample dt * SAMPLES_PER_TRANSFER
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const float min_interval = SAMPLES_PER_TRANSFER * FIFO_SAMPLE_DT;
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// round down to nearest FIFO sample dt
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const float min_interval = FIFO_SAMPLE_DT * 4; // limit to 2 kHz (500 us interval)
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_fifo_empty_interval_us = math::max(roundf((1e6f / (float)sample_rate) / min_interval) * min_interval, min_interval);
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_fifo_gyro_samples = math::min((float)_fifo_empty_interval_us / (1e6f / GYRO_RATE), (float)FIFO_MAX_SAMPLES);
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_fifo_gyro_samples = roundf(math::min((float)_fifo_empty_interval_us / (1e6f / GYRO_RATE), (float)FIFO_MAX_SAMPLES));
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// recompute FIFO empty interval (us) with actual gyro sample limit
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_fifo_empty_interval_us = _fifo_gyro_samples * (1e6f / GYRO_RATE);
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_fifo_accel_samples = math::min(_fifo_empty_interval_us / (1e6f / ACCEL_RATE), (float)FIFO_MAX_SAMPLES);
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}
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bool MPU6000::Configure()
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{
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// first set and clear all configured register bits
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for (const auto ®_cfg : _register_cfg) {
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RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
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}
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// now check that all are configured
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bool success = true;
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for (const auto ® : _register_cfg) {
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if (!RegisterCheck(reg)) {
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for (const auto ®_cfg : _register_cfg) {
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if (!RegisterCheck(reg_cfg)) {
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success = false;
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}
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}
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@ -349,12 +378,13 @@ int MPU6000::DataReadyInterruptCallback(int irq, void *context, void *arg)
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void MPU6000::DataReady()
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{
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perf_count(_drdy_interval_perf);
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const uint8_t count = _drdy_count.fetch_add(1) + 1;
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if (_data_ready_count.fetch_add(1) >= (_fifo_gyro_samples - 1)) {
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_data_ready_count.store(0);
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_fifo_watermark_interrupt_timestamp = hrt_absolute_time();
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_fifo_read_samples.store(_fifo_gyro_samples);
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uint8_t expected = 0;
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// at least the required number of samples in the FIFO
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if ((count >= _fifo_gyro_samples) && _drdy_fifo_read_samples.compare_exchange(&expected, _fifo_gyro_samples)) {
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_drdy_count.store(0);
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ScheduleNow();
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}
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}
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@ -366,7 +396,7 @@ bool MPU6000::DataReadyInterruptConfigure()
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}
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// Setup data ready on falling edge
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return px4_arch_gpiosetevent(_drdy_gpio, false, true, true, &MPU6000::DataReadyInterruptCallback, this) == 0;
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return px4_arch_gpiosetevent(_drdy_gpio, false, true, true, &DataReadyInterruptCallback, this) == 0;
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}
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bool MPU6000::DataReadyInterruptDisable()
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@ -378,7 +408,7 @@ bool MPU6000::DataReadyInterruptDisable()
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return px4_arch_gpiosetevent(_drdy_gpio, false, false, false, nullptr, nullptr) == 0;
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}
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bool MPU6000::RegisterCheck(const register_config_t ®_cfg, bool notify)
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bool MPU6000::RegisterCheck(const register_config_t ®_cfg)
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{
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bool success = true;
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@ -394,16 +424,6 @@ bool MPU6000::RegisterCheck(const register_config_t ®_cfg, bool notify)
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success = false;
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}
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if (!success) {
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RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
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if (notify) {
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perf_count(_bad_register_perf);
|
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_px4_accel.increase_error_count();
|
||||
_px4_gyro.increase_error_count();
|
||||
}
|
||||
}
|
||||
|
||||
return success;
|
||||
}
|
||||
|
||||
|
|
@ -426,17 +446,12 @@ void MPU6000::RegisterWrite(Register reg, uint8_t value)
|
|||
void MPU6000::RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t clearbits)
|
||||
{
|
||||
const uint8_t orig_val = RegisterRead(reg);
|
||||
uint8_t val = orig_val;
|
||||
|
||||
if (setbits) {
|
||||
val |= setbits;
|
||||
uint8_t val = (orig_val & ~clearbits) | setbits;
|
||||
|
||||
if (orig_val != val) {
|
||||
RegisterWrite(reg, val);
|
||||
}
|
||||
|
||||
if (clearbits) {
|
||||
val &= ~clearbits;
|
||||
}
|
||||
|
||||
RegisterWrite(reg, val);
|
||||
}
|
||||
|
||||
uint16_t MPU6000::FIFOReadCount()
|
||||
|
|
@ -454,10 +469,9 @@ uint16_t MPU6000::FIFOReadCount()
|
|||
return combine(fifo_count_buf[1], fifo_count_buf[2]);
|
||||
}
|
||||
|
||||
bool MPU6000::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples)
|
||||
bool MPU6000::FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples)
|
||||
{
|
||||
perf_begin(_transfer_perf);
|
||||
|
||||
FIFOTransferBuffer buffer{};
|
||||
const size_t transfer_size = math::min(samples * sizeof(FIFO::DATA) + 1, FIFO::SIZE);
|
||||
set_frequency(SPI_SPEED_SENSOR);
|
||||
|
|
@ -470,8 +484,8 @@ bool MPU6000::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples)
|
|||
|
||||
perf_end(_transfer_perf);
|
||||
|
||||
ProcessGyro(timestamp_sample, buffer, samples);
|
||||
return ProcessAccel(timestamp_sample, buffer, samples);
|
||||
ProcessGyro(timestamp_sample, buffer.f, samples);
|
||||
return ProcessAccel(timestamp_sample, buffer.f, samples);
|
||||
}
|
||||
|
||||
void MPU6000::FIFOReset()
|
||||
|
|
@ -485,9 +499,8 @@ void MPU6000::FIFOReset()
|
|||
RegisterSetAndClearBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_RESET, USER_CTRL_BIT::FIFO_EN);
|
||||
|
||||
// reset while FIFO is disabled
|
||||
_data_ready_count.store(0);
|
||||
_fifo_watermark_interrupt_timestamp = 0;
|
||||
_fifo_read_samples.store(0);
|
||||
_drdy_count.store(0);
|
||||
_drdy_fifo_read_samples.store(0);
|
||||
|
||||
// FIFO_EN: enable both gyro and accel
|
||||
// USER_CTRL: re-enable FIFO
|
||||
|
|
@ -498,51 +511,74 @@ void MPU6000::FIFOReset()
|
|||
}
|
||||
}
|
||||
|
||||
bool MPU6000::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples)
|
||||
static bool fifo_accel_equal(const FIFO::DATA &f0, const FIFO::DATA &f1)
|
||||
{
|
||||
return (memcmp(&f0.ACCEL_XOUT_H, &f1.ACCEL_XOUT_H, 6) == 0);
|
||||
}
|
||||
|
||||
bool MPU6000::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples)
|
||||
{
|
||||
PX4Accelerometer::FIFOSample accel;
|
||||
accel.timestamp_sample = timestamp_sample;
|
||||
accel.dt = _fifo_empty_interval_us / _fifo_accel_samples;
|
||||
accel.samples = 0;
|
||||
accel.dt = FIFO_SAMPLE_DT * SAMPLES_PER_TRANSFER;
|
||||
|
||||
bool bad_data = false;
|
||||
|
||||
// FIFO contains 8 duplicated accel samples per gyro sample
|
||||
int accel_samples = 0;
|
||||
for (int i = 0; i < samples; i++) {
|
||||
_fifo_accel_samples_count++;
|
||||
|
||||
for (int i = 0; i < samples; i = i + 8) {
|
||||
const FIFO::DATA &fifo_sample = buffer.f[i];
|
||||
int16_t accel_x = combine(fifo_sample.ACCEL_XOUT_H, fifo_sample.ACCEL_XOUT_L);
|
||||
int16_t accel_y = combine(fifo_sample.ACCEL_YOUT_H, fifo_sample.ACCEL_YOUT_L);
|
||||
int16_t accel_z = combine(fifo_sample.ACCEL_ZOUT_H, fifo_sample.ACCEL_ZOUT_L);
|
||||
// only process new FIFO samples (1 every 8 samples expected)
|
||||
const bool new_sample = !fifo_accel_equal(fifo[i], _fifo_sample_last_new_accel);
|
||||
|
||||
// sensor's frame is +x forward, +y left, +z up
|
||||
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
||||
accel.x[accel_samples] = accel_x;
|
||||
accel.y[accel_samples] = (accel_y == INT16_MIN) ? INT16_MAX : -accel_y;
|
||||
accel.z[accel_samples] = (accel_z == INT16_MIN) ? INT16_MAX : -accel_z;
|
||||
accel_samples++;
|
||||
// process every 8th sample
|
||||
if (_fifo_accel_samples_count == SAMPLES_PER_TRANSFER) {
|
||||
int16_t accel_x = combine(fifo[i].ACCEL_XOUT_H, fifo[i].ACCEL_XOUT_L);
|
||||
int16_t accel_y = combine(fifo[i].ACCEL_YOUT_H, fifo[i].ACCEL_YOUT_L);
|
||||
int16_t accel_z = combine(fifo[i].ACCEL_ZOUT_H, fifo[i].ACCEL_ZOUT_L);
|
||||
|
||||
// sensor's frame is +x forward, +y left, +z up
|
||||
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
||||
accel.x[accel.samples] = accel_x;
|
||||
accel.y[accel.samples] = (accel_y == INT16_MIN) ? INT16_MAX : -accel_y;
|
||||
accel.z[accel.samples] = (accel_z == INT16_MIN) ? INT16_MAX : -accel_z;
|
||||
accel.samples++;
|
||||
|
||||
} else if (new_sample && (_fifo_accel_samples_count > 1)) {
|
||||
// a new unique sample after fewer than 8 samples is an error
|
||||
bad_data = true;
|
||||
perf_count(_bad_transfer_perf);
|
||||
}
|
||||
|
||||
// reset previous unique sample and counter
|
||||
if (new_sample || (_fifo_accel_samples_count == SAMPLES_PER_TRANSFER)) {
|
||||
_fifo_accel_samples_count = 0;
|
||||
_fifo_sample_last_new_accel = fifo[i];
|
||||
}
|
||||
}
|
||||
|
||||
accel.samples = accel_samples;
|
||||
_px4_accel.set_error_count(perf_event_count(_bad_register_perf) + perf_event_count(_bad_transfer_perf) +
|
||||
perf_event_count(_fifo_empty_perf) + perf_event_count(_fifo_overflow_perf));
|
||||
|
||||
_px4_accel.updateFIFO(accel);
|
||||
if (accel.samples > 0) {
|
||||
_px4_accel.updateFIFO(accel);
|
||||
}
|
||||
|
||||
return !bad_data;
|
||||
}
|
||||
|
||||
void MPU6000::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples)
|
||||
void MPU6000::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples)
|
||||
{
|
||||
PX4Gyroscope::FIFOSample gyro;
|
||||
gyro.timestamp_sample = timestamp_sample;
|
||||
gyro.samples = samples;
|
||||
gyro.dt = _fifo_empty_interval_us / _fifo_gyro_samples;
|
||||
gyro.dt = FIFO_SAMPLE_DT;
|
||||
|
||||
for (int i = 0; i < samples; i++) {
|
||||
const FIFO::DATA &fifo_sample = buffer.f[i];
|
||||
|
||||
const int16_t gyro_x = combine(fifo_sample.GYRO_XOUT_H, fifo_sample.GYRO_XOUT_L);
|
||||
const int16_t gyro_y = combine(fifo_sample.GYRO_YOUT_H, fifo_sample.GYRO_YOUT_L);
|
||||
const int16_t gyro_z = combine(fifo_sample.GYRO_ZOUT_H, fifo_sample.GYRO_ZOUT_L);
|
||||
const int16_t gyro_x = combine(fifo[i].GYRO_XOUT_H, fifo[i].GYRO_XOUT_L);
|
||||
const int16_t gyro_y = combine(fifo[i].GYRO_YOUT_H, fifo[i].GYRO_YOUT_L);
|
||||
const int16_t gyro_z = combine(fifo[i].GYRO_ZOUT_H, fifo[i].GYRO_ZOUT_L);
|
||||
|
||||
// sensor's frame is +x forward, +y left, +z up
|
||||
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
||||
|
|
@ -551,6 +587,9 @@ void MPU6000::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransfe
|
|||
gyro.z[i] = (gyro_z == INT16_MIN) ? INT16_MAX : -gyro_z;
|
||||
}
|
||||
|
||||
_px4_gyro.set_error_count(perf_event_count(_bad_register_perf) + perf_event_count(_bad_transfer_perf) +
|
||||
perf_event_count(_fifo_empty_perf) + perf_event_count(_fifo_overflow_perf));
|
||||
|
||||
_px4_gyro.updateFIFO(gyro);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -73,10 +73,10 @@ private:
|
|||
void exit_and_cleanup() override;
|
||||
|
||||
// Sensor Configuration
|
||||
static constexpr float FIFO_SAMPLE_DT{125.f};
|
||||
static constexpr uint32_t SAMPLES_PER_TRANSFER{8}; // ensure at least 1 new accel sample per transfer
|
||||
static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT}; // 8 kHz gyro
|
||||
static constexpr float ACCEL_RATE{GYRO_RATE / 8.f}; // 1 kHz accel
|
||||
static constexpr float FIFO_SAMPLE_DT{1e6f / 8000.f};
|
||||
static constexpr uint32_t SAMPLES_PER_TRANSFER{8}; // ensure at least 1 new accel sample per transfer
|
||||
static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT}; // 8000 Hz gyro
|
||||
static constexpr float ACCEL_RATE{GYRO_RATE / SAMPLES_PER_TRANSFER}; // 1000 Hz accel
|
||||
|
||||
static constexpr uint32_t FIFO_MAX_SAMPLES{math::min(FIFO::SIZE / sizeof(FIFO::DATA), sizeof(PX4Gyroscope::FIFOSample::x) / sizeof(PX4Gyroscope::FIFOSample::x[0]))};
|
||||
|
||||
|
|
@ -108,20 +108,18 @@ private:
|
|||
bool DataReadyInterruptConfigure();
|
||||
bool DataReadyInterruptDisable();
|
||||
|
||||
bool RegisterCheck(const register_config_t ®_cfg, bool notify = false);
|
||||
bool RegisterCheck(const register_config_t ®_cfg);
|
||||
|
||||
uint8_t RegisterRead(Register reg);
|
||||
void RegisterWrite(Register reg, uint8_t value);
|
||||
void RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t clearbits);
|
||||
void RegisterSetBits(Register reg, uint8_t setbits) { RegisterSetAndClearBits(reg, setbits, 0); }
|
||||
void RegisterClearBits(Register reg, uint8_t clearbits) { RegisterSetAndClearBits(reg, 0, clearbits); }
|
||||
|
||||
uint16_t FIFOReadCount();
|
||||
bool FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples);
|
||||
bool FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples);
|
||||
void FIFOReset();
|
||||
|
||||
bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
|
||||
void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
|
||||
bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples);
|
||||
void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples);
|
||||
void UpdateTemperature();
|
||||
|
||||
const spi_drdy_gpio_t _drdy_gpio;
|
||||
|
|
@ -135,15 +133,19 @@ private:
|
|||
perf_counter_t _fifo_empty_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO empty")};
|
||||
perf_counter_t _fifo_overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO overflow")};
|
||||
perf_counter_t _fifo_reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO reset")};
|
||||
perf_counter_t _drdy_interval_perf{perf_alloc(PC_INTERVAL, MODULE_NAME": DRDY interval")};
|
||||
perf_counter_t _drdy_interval_perf{nullptr};
|
||||
|
||||
hrt_abstime _reset_timestamp{0};
|
||||
hrt_abstime _last_config_check_timestamp{0};
|
||||
hrt_abstime _fifo_watermark_interrupt_timestamp{0};
|
||||
hrt_abstime _temperature_update_timestamp{0};
|
||||
unsigned _consecutive_failures{0};
|
||||
unsigned _total_failures{0};
|
||||
|
||||
px4::atomic<uint8_t> _data_ready_count{0};
|
||||
px4::atomic<uint8_t> _fifo_read_samples{0};
|
||||
FIFO::DATA _fifo_sample_last_new_accel{};
|
||||
int _fifo_accel_samples_count{0};
|
||||
|
||||
px4::atomic<uint8_t> _drdy_fifo_read_samples{0};
|
||||
px4::atomic<uint8_t> _drdy_count{0};
|
||||
bool _data_ready_interrupt_enabled{false};
|
||||
|
||||
enum class STATE : uint8_t {
|
||||
|
|
@ -157,18 +159,17 @@ private:
|
|||
|
||||
uint16_t _fifo_empty_interval_us{1250}; // default 1250 us / 800 Hz transfer interval
|
||||
uint8_t _fifo_gyro_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
|
||||
uint8_t _fifo_accel_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / ACCEL_RATE))};
|
||||
|
||||
uint8_t _checked_register{0};
|
||||
static constexpr uint8_t size_register_cfg{7};
|
||||
register_config_t _register_cfg[size_register_cfg] {
|
||||
// Register | Set bits, Clear bits
|
||||
{ Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::DEVICE_RESET | PWR_MGMT_1_BIT::SLEEP },
|
||||
{ Register::ACCEL_CONFIG, ACCEL_CONFIG_BIT::AFS_SEL_16G, 0 },
|
||||
{ Register::GYRO_CONFIG, GYRO_CONFIG_BIT::FS_SEL_2000_DPS, 0 },
|
||||
{ Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN | USER_CTRL_BIT::I2C_IF_DIS, USER_CTRL_BIT::I2C_MST_EN},
|
||||
{ Register::ACCEL_CONFIG, ACCEL_CONFIG_BIT::AFS_SEL_16G, 0 },
|
||||
{ Register::FIFO_EN, FIFO_EN_BIT::XG_FIFO_EN | FIFO_EN_BIT::YG_FIFO_EN | FIFO_EN_BIT::ZG_FIFO_EN | FIFO_EN_BIT::ACCEL_FIFO_EN, FIFO_EN_BIT::TEMP_FIFO_EN },
|
||||
{ Register::INT_PIN_CFG, INT_PIN_CFG_BIT::INT_LEVEL, 0 },
|
||||
{ Register::INT_ENABLE, INT_ENABLE_BIT::DATA_RDY_INT_EN, 0 }
|
||||
{ Register::INT_ENABLE, INT_ENABLE_BIT::DATA_RDY_INT_EN, 0 },
|
||||
{ Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN | USER_CTRL_BIT::I2C_IF_DIS, 0 },
|
||||
{ Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::DEVICE_RESET | PWR_MGMT_1_BIT::SLEEP },
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue