forked from Archive/PX4-Autopilot
Calypso update
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4684 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
c88c7c9b4b
commit
51c1f0c7bd
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@ -41,6 +41,7 @@
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#include <arch/calypso/memory.h>
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#include <arch/calypso/armio.h>
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#include "up_arch.h"
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/****************************************************************************
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* HW access
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@ -92,10 +93,10 @@ static int kbd_gpio_irq(int irq, uint32_t *regs)
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void calypso_armio(void)
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{
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/* Enable ARMIO clock */
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writew(1<<5, ARMIO_REG(CNTL_REG));
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putreg16(1<<5, ARMIO_REG(CNTL_REG));
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/* Mask GPIO interrupt and keypad interrupt */
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writew(KBD_INT|GPIO_INT, ARMIO_REG(KBD_GPIO_MASKIT));
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putreg16(KBD_INT|GPIO_INT, ARMIO_REG(KBD_GPIO_MASKIT));
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/* Attach and enable the interrupt */
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irq_attach(IRQ_KEYPAD_GPIO, (xcpt_t)kbd_gpio_irq);
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@ -1,5 +1,5 @@
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/****************************************************************************
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* calypso_heap.c
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* arch/arm/src/calypso/calypso_heap.c
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* Initialize memory interfaces of Calypso MCU
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*
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* (C) 2010 by Harald Welte <laforge@gnumonks.org>
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@ -50,6 +50,7 @@
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#include <arch/calypso/memory.h>
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#include "arm.h"
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#include "up_arch.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -124,12 +125,12 @@ static void _irq_enable(enum irq_nr nr, int enable)
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nr -= 16;
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}
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val = readw(reg);
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val = getreg16(reg);
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if (enable)
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val &= ~(1 << nr);
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else
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val |= (1 << nr);
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writew(val, reg);
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putreg16(val, reg);
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}
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static void set_default_priorities(void)
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@ -142,14 +143,14 @@ static void set_default_priorities(void)
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if (prio > 31)
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prio = 31;
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val = readw(IRQ_REG(ILR_IRQ(i)));
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val = getreg16(IRQ_REG(ILR_IRQ(i)));
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val &= ~(0x1f << 2);
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val |= prio << 2;
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/* Make edge mode default. Hopefully causes less trouble */
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val |= 0x02;
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writew(val, IRQ_REG(ILR_IRQ(i)));
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putreg16(val, IRQ_REG(ILR_IRQ(i)));
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}
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}
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@ -190,12 +191,12 @@ void up_irqinitialize(void)
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set_default_priorities();
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/* mask all interrupts off */
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writew(0xffff, IRQ_REG(MASK_IT_REG1));
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writew(0xffff, IRQ_REG(MASK_IT_REG2));
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putreg16(0xffff, IRQ_REG(MASK_IT_REG1));
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putreg16(0xffff, IRQ_REG(MASK_IT_REG2));
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/* clear all pending interrupts */
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writew(0, IRQ_REG(IT_REG1));
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writew(0, IRQ_REG(IT_REG2));
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putreg16(0, IRQ_REG(IT_REG1));
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putreg16(0, IRQ_REG(IT_REG2));
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/* enable interrupts globally to the ARM core */
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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@ -251,7 +252,7 @@ int up_prioritize_irq(int nr, int prio)
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prio = 31;
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val = prio << 2;
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writew(val, IRQ_REG(ILR_IRQ(nr)));
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putreg16(val, IRQ_REG(ILR_IRQ(nr)));
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return 0; // XXX: what's the return???
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}
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@ -273,13 +274,13 @@ void up_decodeirq(uint32_t *regs)
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current_regs = regs;
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/* Detect & deliver the IRQ */
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num = readb(IRQ_REG(IRQ_NUM)) & 0x1f;
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num = getreg8(IRQ_REG(IRQ_NUM)) & 0x1f;
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irq_dispatch(num, regs);
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/* Start new IRQ agreement */
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tmp = readb(IRQ_REG(IRQ_CTRL));
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tmp = getreg8(IRQ_REG(IRQ_CTRL));
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tmp |= 0x01;
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writeb(tmp, IRQ_REG(IRQ_CTRL));
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putreg8(tmp, IRQ_REG(IRQ_CTRL));
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current_regs = saved_regs;
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}
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@ -300,13 +301,13 @@ void calypso_fiq(void)
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current_regs = (uint32_t *)#
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/* Detect & deliver like an IRQ but we are in FIQ context */
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num = readb(IRQ_REG(FIQ_NUM)) & 0x1f;
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num = getreg8(IRQ_REG(FIQ_NUM)) & 0x1f;
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irq_dispatch(num, regs);
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/* Start new FIQ agreement */
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tmp = readb(IRQ_REG(IRQ_CTRL));
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tmp = getreg8(IRQ_REG(IRQ_CTRL));
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tmp |= 0x02;
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writeb(tmp, IRQ_REG(IRQ_CTRL));
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putreg8(tmp, IRQ_REG(IRQ_CTRL));
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current_regs = regs;
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}
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@ -1,5 +1,5 @@
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/****************************************************************************
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* calypso/calypso_serial.c
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* arch/arm/src/calypso/calypso_serial.c
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*
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* Copyright (C) 2011 Stefan Richter. All rights reserved.
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* Author: Stefan Richter <ichgeh@l--putt.de>
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@ -1,10 +1,12 @@
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/****************************************************************************
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* calypso_spi.c
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* arch/arm/src/calypso/calypso_spi.c
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* SPI driver for TI Calypso
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*
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* Copyright (C) 2010 Harald Welte <laforge@gnumonks.org>
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* Copyright (C) 2011 Stefan Richter <ichgeh@l--putt.de>
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*
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* All rights reserved.
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* Part of this source code is derivated from Osmocom-BB project and was
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* relicensed as BSD with permission from original authors.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -38,6 +40,11 @@
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#include <nuttx/config.h>
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#include <nuttx/spi.h>
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#include <debug.h>
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#include "up_arch.h"
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#include "calypso_spi.h"
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#warning "MOST OF SPI API IS INCOMPLETE! (Wrapper around Osmocom driver)"
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extern void spi_init(void);
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extern int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din);
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@ -127,6 +134,90 @@ static struct calypso_spidev_s g_spidev =
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.nbits = 0,
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};
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void spi_init(void)
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{
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putreg16(SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS | SPI_SET1_RDWR_IRQ_DIS,
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SPI_REG(REG_SET1));
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putreg16(0x0001, SPI_REG(REG_SET2));
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}
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int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
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{
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uint8_t bytes_per_xfer;
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uint8_t reg_status, reg_ctrl = 0;
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uint32_t tmp;
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if (bitlen == 0)
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return 0;
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if (bitlen > 32)
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return -1;
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if (dev_idx > 4)
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return -1;
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bytes_per_xfer = bitlen / 8;
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if (bitlen % 8)
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bytes_per_xfer ++;
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reg_ctrl |= (bitlen - 1) << SPI_CTRL_NB_SHIFT;
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reg_ctrl |= (dev_idx & 0x7) << SPI_CTRL_AD_SHIFT;
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if (bitlen <= 8) {
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tmp = *(uint8_t *)dout;
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tmp <<= 24 + (8-bitlen); /* align to MSB */
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} else if (bitlen <= 16) {
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tmp = *(uint16_t *)dout;
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tmp <<= 16 + (16-bitlen); /* align to MSB */
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} else {
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tmp = *(uint32_t *)dout;
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tmp <<= (32-bitlen); /* align to MSB */
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}
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dbg("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
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dev_idx, bitlen, tmp);
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/* fill transmit registers */
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putreg16(tmp >> 16, SPI_REG(REG_TX_MSB));
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putreg16(tmp & 0xffff, SPI_REG(REG_TX_LSB));
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/* initiate transfer */
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if (din)
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reg_ctrl |= SPI_CTRL_RDWR;
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else
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reg_ctrl |= SPI_CTRL_WR;
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putreg16(reg_ctrl, SPI_REG(REG_CTRL));
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dbg("reg_ctrl=0x%04x ", reg_ctrl);
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/* wait until the transfer is complete */
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while (1) {
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reg_status = getreg16(SPI_REG(REG_STATUS));
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dbg("status=0x%04x ", reg_status);
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if (din && (reg_status & SPI_STATUS_RE))
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break;
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else if (reg_status & SPI_STATUS_WE)
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break;
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}
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/* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */
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usleep(1000);
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if (din) {
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tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16;
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tmp |= getreg16(SPI_REG(REG_RX_LSB));
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dbg("data_in=0x%08x ", tmp);
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if (bitlen <= 8)
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*(uint8_t *)din = tmp & 0xff;
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else if (bitlen <= 16)
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*(uint16_t *)din = tmp & 0xffff;
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else
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*(uint32_t *)din = tmp;
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}
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dbg('\n');
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return 0;
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}
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FAR struct spi_dev_s *up_spiinitialize(int port)
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{
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switch(port) {
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@ -45,6 +45,7 @@
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#include <arch/calypso/memory.h>
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#include <arch/calypso/timer.h>
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#include "up_arch.h"
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#define BASE_ADDR_TIMER 0xfffe3800
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#define TIMER2_OFFSET 0x3000
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@ -74,12 +75,12 @@ void hwtimer_enable(int num, int on)
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return;
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}
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ctl = readb(TIMER_REG(num, CNTL_TIMER));
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ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
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if (on)
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ctl |= CNTL_START|CNTL_CLOCK_ENABLE;
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else
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ctl &= ~CNTL_START;
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writeb(ctl, TIMER_REG(num, CNTL_TIMER));
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putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
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}
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void hwtimer_config(int num, uint8_t pre_scale, int auto_reload)
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@ -90,22 +91,22 @@ void hwtimer_config(int num, uint8_t pre_scale, int auto_reload)
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if (auto_reload)
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ctl |= CNTL_AUTO_RELOAD;
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writeb(ctl, TIMER_REG(num, CNTL_TIMER));
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putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
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}
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void hwtimer_load(int num, uint16_t val)
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{
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writew(val, TIMER_REG(num, LOAD_TIMER));
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putreg16(val, TIMER_REG(num, LOAD_TIMER));
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}
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uint16_t hwtimer_read(int num)
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{
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uint8_t ctl = readb(TIMER_REG(num, CNTL_TIMER));
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uint8_t ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
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/* somehow a read results in an abort */
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if ((ctl & (CNTL_START|CNTL_CLOCK_ENABLE)) != (CNTL_START|CNTL_CLOCK_ENABLE))
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return 0xFFFF;
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return readw(TIMER_REG(num, READ_TIMER));
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return getreg16(TIMER_REG(num, READ_TIMER));
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}
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/************************************************************
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@ -143,18 +144,18 @@ static void wdog_irq(__unused enum irq_nr nr)
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void wdog_enable(int on)
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{
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if (!on) {
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writew(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE));
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writew(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE));
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putreg16(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE));
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putreg16(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE));
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}
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}
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void wdog_reset(void)
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{
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// enable watchdog
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writew(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
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putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
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// force expiration
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writew(0x0000, WDOG_REG(WD_LOAD_TIMER));
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writew(0x0000, WDOG_REG(WD_LOAD_TIMER));
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putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
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putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
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}
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/************************************************************
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@ -47,6 +47,8 @@
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#include <arch/calypso/memory.h>
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#include <arch/calypso/clock.h>
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#include "up_arch.h"
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#define REG_DPLL 0xffff9800
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#define DPLL_LOCK (1 << 0)
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#define DPLL_BREAKLN (1 << 1)
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@ -98,7 +100,7 @@ enum memif_reg {
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static void dump_reg16(uint32_t addr, char *name)
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{
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printf("%s=0x%04x\n", name, readw(addr));
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printf("%s=0x%04x\n", name, getreg16(addr));
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}
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void calypso_clk_dump(void)
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@ -114,31 +116,31 @@ void calypso_pll_set(uint16_t inp)
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{
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uint8_t mult = inp >> 8;
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uint8_t div = inp & 0xff;
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uint16_t reg = readw(REG_DPLL);
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uint16_t reg = getreg16(REG_DPLL);
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reg &= ~0x0fe0;
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reg |= (div & 0x3) << DPLL_PLL_DIV_SHIFT;
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reg |= (mult & 0x1f) << DPLL_PLL_MULT_SHIFT;
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reg |= DPLL_PLL_ENABLE;
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writew(reg, REG_DPLL);
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putreg16(reg, REG_DPLL);
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}
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void calypso_reset_set(enum calypso_rst calypso_rst, int active)
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{
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uint8_t reg = readb(CLKM_REG(CNTL_RST));
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uint8_t reg = getreg8(CLKM_REG(CNTL_RST));
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if (active)
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reg |= calypso_rst;
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else
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reg &= ~calypso_rst;
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writeb(reg, CLKM_REG(CNTL_RST));
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putreg8(reg, CLKM_REG(CNTL_RST));
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}
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int calypso_reset_get(enum calypso_rst calypso_rst)
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{
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uint8_t reg = readb(CLKM_REG(CNTL_RST));
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uint8_t reg = getreg8(CLKM_REG(CNTL_RST));
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if (reg & calypso_rst)
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return 1;
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@ -148,8 +150,8 @@ int calypso_reset_get(enum calypso_rst calypso_rst)
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void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div)
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{
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uint16_t cntl_clock = readw(CLKM_REG(CNTL_CLK));
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uint16_t cntl_arm_clk = readw(CLKM_REG(CNTL_ARM_CLK));
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uint16_t cntl_clock = getreg16(CLKM_REG(CNTL_CLK));
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uint16_t cntl_arm_clk = getreg16(CLKM_REG(CNTL_ARM_CLK));
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/* First set the vtcxo_div2 */
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cntl_clock &= ~CLK_VCLKOUT_DIV2;
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@ -157,7 +159,7 @@ void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div)
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cntl_clock |= CLK_VTCXO_DIV2;
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else
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cntl_clock &= ~CLK_VTCXO_DIV2;
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writew(cntl_clock, CLKM_REG(CNTL_CLK));
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putreg16(cntl_clock, CLKM_REG(CNTL_CLK));
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/* Then configure the MCLK divider */
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cntl_arm_clk &= ~ARM_CLK_CLKIN_SEL0;
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@ -168,7 +170,7 @@ void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div)
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cntl_arm_clk &= ~ARM_CLK_MCLK_DIV5;
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cntl_arm_clk &= ~(0x7 << ARM_CLK_MCLK_DIV_SHIFT);
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cntl_arm_clk |= (mclk_div << ARM_CLK_MCLK_DIV_SHIFT);
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writew(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK));
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putreg16(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK));
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/* Then finally set the PLL */
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calypso_pll_set(inp);
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@ -177,32 +179,32 @@ void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div)
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void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
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enum calypso_mem_width width, int we)
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{
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writew((ws & 0x1f) | ((width & 3) << 5) | ((we & 1) << 7),
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putreg16((ws & 0x1f) | ((width & 3) << 5) | ((we & 1) << 7),
|
||||
BASE_ADDR_MEMIF + bank);
|
||||
}
|
||||
|
||||
void calypso_bootrom(int enable)
|
||||
{
|
||||
uint16_t conf = readw(MEMIF_REG(EXTRA_CONF));
|
||||
uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF));
|
||||
|
||||
conf |= (3 << 8);
|
||||
|
||||
if (enable)
|
||||
conf &= ~(1 << 9);
|
||||
|
||||
writew(conf, MEMIF_REG(EXTRA_CONF));
|
||||
putreg16(conf, MEMIF_REG(EXTRA_CONF));
|
||||
}
|
||||
|
||||
void calypso_debugunit(int enable)
|
||||
{
|
||||
uint16_t conf = readw(MEMIF_REG(EXTRA_CONF));
|
||||
uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF));
|
||||
|
||||
if (enable)
|
||||
conf &= ~(1 << 11);
|
||||
else
|
||||
conf |= (1 << 11);
|
||||
|
||||
writew(conf, MEMIF_REG(EXTRA_CONF));
|
||||
putreg16(conf, MEMIF_REG(EXTRA_CONF));
|
||||
}
|
||||
|
||||
#define REG_RHEA_CNTL 0xfffff900
|
||||
|
|
@ -212,7 +214,7 @@ void calypso_debugunit(int enable)
|
|||
void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
|
||||
uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1)
|
||||
{
|
||||
writew(fac0 | (fac1 << 4) | (timeout << 8), REG_RHEA_CNTL);
|
||||
writew(ws_h | (ws_l << 5), REG_API_CNTL);
|
||||
writew(w_en0 | (w_en1 << 1), REG_ARM_RHEA);
|
||||
putreg16(fac0 | (fac1 << 4) | (timeout << 8), REG_RHEA_CNTL);
|
||||
putreg16(ws_h | (ws_l << 5), REG_API_CNTL);
|
||||
putreg16(w_en0 | (w_en1 << 1), REG_ARM_RHEA);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue