forked from Archive/PX4-Autopilot
Fixes to STM32 definitions from Freddie Chopin
git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5297 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
d1d50b4e0e
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4960d58d8b
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@ -61,11 +61,13 @@
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* External interrupts (vectors >= 16)
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*/
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#if defined(CONFIG_STM32_VALUELINE) && defined(CONFIG_STM32_MEDIUMDENSITY)
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/* Value line devices */
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#if defined(CONFIG_STM32_VALUELINE)
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# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
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# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
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# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
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# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */
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# define STM32_IRQ_RTC (19) /* 3: RTC Wakeup through EXTI line interrupt */
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# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */
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# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */
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# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */
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@ -80,12 +82,15 @@
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# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
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# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
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# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
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# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */
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# define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */
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/* 19-22: reserved */
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# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */
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# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */
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# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt (TIM16 global interrupt) */
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# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts (TIM17 global interrupt) */
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# define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */
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# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */
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# define STM32_IRQ_TIM16 (41) /* TIM16 global interrupt */
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# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */
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# define STM32_IRQ_TIM17 (42) /* TIM17 global interrupt */
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# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */
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# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */
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# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */
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@ -100,29 +105,29 @@
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# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */
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# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */
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# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */
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# define STM32_IRQ_RTCALR (57) /* 41: RTC alarm through EXTI line interrupt */
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# define STM32_IRQ_RTCALR (57) /* 41: RTC alarms (A and B) through EXTI line interrupt */
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# define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */
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# if defined(CONFIG_STM32_HIGHDENSITY)
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# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */
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# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */
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# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */
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# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */
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# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */
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# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */
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/* 46-47: reserved */
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# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */
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# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */
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/* 49: reserved */
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# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
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# define STM32_IRQ_SPI3 (67) /* 51: SPI1 global interrupt */
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# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
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# define STM32_IRQ_UART5 (69) /* 53: USART3 global interrupt */
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# else
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/* 43-53: reserved */
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# endif
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# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
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# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
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# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
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# define STM32_IRQ_UART5 (69) /* 53: USART5 global interrupt */
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# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
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# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
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# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
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# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
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# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
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# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 global interrupt */
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# define NR_IRQS (76)
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# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */
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# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */
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# define NR_IRQS (77)
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/* Connectivity Line Devices */
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#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
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# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
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# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
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@ -193,6 +198,9 @@
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# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
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# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
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# define NR_IRQS (84)
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/* Medium and High Density Devices */
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#else
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# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
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# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
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@ -129,7 +129,7 @@
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#if 0 /* Needs further investigation */
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#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
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#endif
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@ -85,7 +85,7 @@
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#endif
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#if 0 /* Needs further investigation */
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#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
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#endif
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@ -85,7 +85,7 @@
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#endif
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#if 0 /* Needs further investigation */
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#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
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#endif
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@ -60,7 +60,14 @@
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#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00 - 0x40000fff: TIM5 timer */
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#define STM32_TIM6_BASE 0x40001000 /* 0x40001000 - 0x400013ff: TIM6 timer */
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#define STM32_TIM7_BASE 0x40001400 /* 0x40001400 - 0x400007ff: TIM7 timer */
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/* 0x40001800 - 0x40000fff: Reserved */
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#if defined(CONFIG_STM32_VALUELINE)
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# define STM32_TIM12_BASE 0x40001800 /* 0x40001800 - 0x40001bff: TIM12 timer */
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# define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00 - 0x40001fff: TIM13 timer */
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# define STM32_TIM14_BASE 0x40002000 /* 0x40002000 - 0x400023ff: TIM14 timer */
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/* 0x40002400 - 0x400027ff: Reserved */
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#else
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/* 0x40001800 - 0x40027fff: Reserved */
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#endif
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#define STM32_RTC_BASE 0x40002800 /* 0x40002800 - 0x40002bff: RTC */
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#define STM32_WWDG_BASE 0x40002c00 /* 0x40002C00 - 0x40002fff: Window watchdog (WWDG) */
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#define STM32_IWDG_BASE 0x40003000 /* 0x40003000 - 0x400033ff: Independent watchdog (IWDG) */
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@ -83,7 +90,12 @@
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#define STM32_BKP_BASE 0x40006c00 /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */
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#define STM32_PWR_BASE 0x40007000 /* 0x40007000 - 0x400073ff: Power control PWR */
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#define STM32_DAC_BASE 0x40007400 /* 0x40007400 - 0x400077ff: DAC */
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#if defined(CONFIG_STM32_VALUELINE)
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# define STM32_CEC_BASE 0x40007800 /* 0x40007800 - 0x40007bff: CEC */
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/* 0x40007c00 - 0x4000ffff: Reserved */
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#else
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/* 0x40007800 - 0x4000ffff: Reserved */
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#endif
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/* APB2 bus */
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@ -102,44 +114,53 @@
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#define STM32_SPI1_BASE 0x40013000 /* 0x40013000 - 0x400133ff: SPI1 */
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#define STM32_TIM8_BASE 0x40013400 /* 0x40013400 - 0x400137ff: TIM8 timer */
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#define STM32_USART1_BASE 0x40013800 /* 0x40013800 - 0x40013bff: USART1 */
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#define STM32_ADC3_BASE 0x40012800 /* 0x40012800 - 0x40013fff: ADC3 */
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/* 0x40014000 - 0x40017fff: Reserved */
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#define STM32_ADC3_BASE 0x40012800 /* 0x40012800 - 0x40013c00: ADC3 */
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#if defined(CONFIG_STM32_VALUELINE)
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/* 0x40013c00 - 0x40013fff: Reserved */
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# define STM32_TIM15_BASE 0x40014400 /* 0x40014400 - 0x400147ff: TIM15 */
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# define STM32_TIM16_BASE 0x40014400 /* 0x40014400 - 0x400147ff: TIM16 */
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# define STM32_TIM17_BASE 0x40014800 /* 0x40014800 - 0x40014bff: TIM17 */
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/* 0x40014c00 - 0x4001ffff: Reserved */
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#else
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/* 0x40013c00 - 0x4001ffff: Reserved */
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#endif
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/* AHB bus */
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#define STM32_SDIO_BASE 0x40018000 /* 0x40018000 - 0x400183ff: SDIO */
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/* 0x40018400 - 0x40017fff: Reserved */
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#define STM32_DMA1_BASE 0x40020000 /* 0x40020000 - 0x400203ff: DMA1 */
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#define STM32_DMA2_BASE 0x40020400 /* 0x40020000 - 0x400207ff: DMA2 */
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/* 0x40020800 - 0x40020fff: Reserved */
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#define STM32_RCC_BASE 0x40021000 /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
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/* 0x40021400 - 0x40021fff: Reserved */
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#define STM32_OTGFS_BASE 0x50000000 /* 0x50000000 - 0x500003ff: USB OTG FS */
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#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */
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#define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: CRC */
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/* 0x40023400 - 0x40027fff: Reserved */
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#define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */
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/* 0x40030000 - 0x4fffffff: Reserved */
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#define STM32_SDIO_BASE 0x40018000 /* 0x40018000 - 0x400183ff: SDIO */
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/* 0x40018400 - 0x40017fff: Reserved */
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#define STM32_DMA1_BASE 0x40020000 /* 0x40020000 - 0x400203ff: DMA1 */
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#define STM32_DMA2_BASE 0x40020400 /* 0x40020000 - 0x400207ff: DMA2 */
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/* 0x40020800 - 0x40020fff: Reserved */
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#define STM32_RCC_BASE 0x40021000 /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
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/* 0x40021400 - 0x40021fff: Reserved */
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#define STM32_OTGFS_BASE 0x50000000 /* 0x50000000 - 0x500003ff: USB OTG FS */
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#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */
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#define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: CRC */
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/* 0x40023400 - 0x40027fff: Reserved */
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#define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */
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/* 0x40030000 - 0x4fffffff: Reserved */
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/* Peripheral BB base */
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#define STM32_PERIPHBB_BASE 0x42000000
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#define STM32_PERIPHBB_BASE 0x42000000
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/* Flexible SRAM controller (FSMC) */
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#define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
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#define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
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#define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
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#define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
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#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
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#define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
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#define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
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#define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
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#define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
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#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
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#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
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#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
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/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
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* address range
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*/
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#define STM32_SCS_BASE 0xe000e000
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#define STM32_DEBUGMCU_BASE 0xe0042000
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#define STM32_SCS_BASE 0xe000e000
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#define STM32_DEBUGMCU_BASE 0xe0042000
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_MEMORYMAP_H */
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@ -49,15 +49,15 @@
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* definition that provides the number of supported vectors.
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*/
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#ifdef CONFIG_ARMV7M_CMNVECTOR
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# ifdef CONFIG_ARMV7M_CMNVECTOR
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/* Reserve 60 interrupt table entries for I/O interrupts. */
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/* Reserve 61 interrupt table entries for I/O interrupts. */
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# define ARMV7M_PERIPHERAL_INTERRUPTS 60
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# define ARMV7M_PERIPHERAL_INTERRUPTS 61
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#else
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# error This target requires CONFIG_ARMV7M_CMNVECTOR
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#endif /* CONFIG_ARMV7M_CMNVECTOR */
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# error This target requires CONFIG_ARMV7M_CMNVECTOR
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# endif /* CONFIG_ARMV7M_CMNVECTOR */
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#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
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