forked from Archive/PX4-Autopilot
px4fmu-v2, px4fmu-v3:Restruture SPI Selects and DRDY
The removes the alias so it is clear what bus and port bit
is associated with as CS or DRDY signal.
This becomes important when varients of V2 a) use the CS on differnt
busses or b) swap a RDY (in) for a CS (out). In both cases,
a CS on once buss, can back feed and cause sensor reset to not be
able to turn off the power if all the pins are not tunered
off
This commit is contained in:
David Sidrane
Lorenz Meier
parent
d58a802eaa
commit
43843b753d
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@ -70,41 +70,119 @@
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#define GPIO_LED1 (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN12)
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/* External interrupts */
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#define GPIO_EXTI_GYRO_DRDY (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN0)
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#define GPIO_EXTI_MAG_DRDY (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN1)
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#define GPIO_EXTI_ACCEL_DRDY (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN4)
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#define GPIO_EXTI_MPU_DRDY (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN15)
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/*
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* Define the ability to shut off off the sensor signals
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* by changing the signals to inputs
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*/
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/* Data ready pins off */
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#define GPIO_GYRO_DRDY_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTB|GPIO_PIN0)
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#define GPIO_MAG_DRDY_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTB|GPIO_PIN1)
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#define GPIO_ACCEL_DRDY_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTB|GPIO_PIN4)
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#define GPIO_EXTI_MPU_DRDY_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_EXTI|GPIO_PORTD|GPIO_PIN15)
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#define _PIN_OFF(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_50MHz))
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/* SPI1 off */
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#define GPIO_SPI1_SCK_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTA|GPIO_PIN5)
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#define GPIO_SPI1_MISO_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTA|GPIO_PIN6)
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#define GPIO_SPI1_MOSI_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTA|GPIO_PIN7)
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/* Due to inconsistent use of chip select and dry signal on
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* different board that use this build. We are defining the GPIO
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* inclusive of the SPI port and GPIO to help identify pins the
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* are part of the sensor Net's controlled by different power
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* domains.
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*
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* Only the GPIO_SPIb_xxx_Ppi will be used in the code to insure this are no
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* cross connections.
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*
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* --------------- SPI1 -------------------- SPI4 -------------- Incompatibilities ---------
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* FMUv2: FmuV3 Cube PixhawkMini
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* Power Domain: VDD_3V3_SENSORS_EN nVDD_5V_PERIPH_EN V3V:SPI1&SPI4 V3V:SPI1 No SPI4
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* PA5 SPI_INT_SCK
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* PA6 SPI_INT_MISO
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* PA7 SPI_INT_MOSI
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* PB0 GYRO_DRDY SPI4:EXTERN_DRDY NC
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* PB1 MAG_DRDY +SPI4:nEXTERN_CS NC
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* PB4 ACCEL_DRDY NC NC
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* PC1 Spare ADC ( NC ) +SPI1:SPI_INT_MAG_!CS
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* PC2 nMPU_CS @MPU6000|MPU9250 @MPU9250
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* PC13 nGYRO_CS SPI4:nGYRO_EXT_CS NC
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* PC14 GPIO_EXT_1 nBARO_EXT_CS -20608_DRDY
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* PC15 nACCEL_MAG_CS SPI4:nACCEL_MAG_EXT_CS 20608_CS
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* PD7 nBARO_CS
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* PD15 nMPU_DRDY @MPU6000|MPU9250 @MPU9250
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* PE2 SPI_EXT_SCK NC
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* PE4 nSPI_EXT_NSS SPI4:nMPU_EXT_CS NC
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* PE5 SPI_EXT_MISO NC
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* PE6 SPI_EXT_MOSI NC
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*
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* Notes: Prefixed with @ Does not effect board control
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* Prefixed with + Input used as Output
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* Prefixed with - Output used as Input
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* Prefixed with SPIn: Bus changed
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*
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* The board API provides for mechanism to perform a SPI bus reset.
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* To facilitate a SPI bus reset
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*
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* 1) All the pins: SPIn, CD, DRDY associated with the SPI bus are turned to inputs
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* with outputs driven low. (OFFIng)
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* 2) The power domain of that bus is turned off.
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* 3) A usleep it done for ms.
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* 4) The power domain of that bus is turned back on.
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* 5) The SPIn pins are re-initialized.
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* 6) The SPI CS, DRDY pins are re-initialized.
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*
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* To insure the complete net is de-energized and is not bing back fed, it is important to
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* note the all signals in the net list of the parts/bus.
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*
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* I.E. Not OFFIng PC1 on V3 would leave that pin back feeding the HMC part. As would not
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* OFFIng PE4, not associated with SPI1 on V2, but would back feed an MPUxxxx on V3
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*
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*/
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/* SPI1 chip selects off */
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#define GPIO_SPI_CS_GYRO_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTC|GPIO_PIN13)
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#define GPIO_SPI_CS_ACCEL_MAG_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTC|GPIO_PIN15)
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#define GPIO_SPI_CS_BARO_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTD|GPIO_PIN7)
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#define GPIO_SPI_CS_MPU_OFF (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTC|GPIO_PIN2)
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/* SPI chip selects */
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#define GPIO_SPI_CS_GYRO (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN13)
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#define GPIO_SPI_CS_ACCEL_MAG (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN15)
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#define GPIO_SPI_CS_BARO (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN7)
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#define GPIO_SPI_CS_FRAM (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN10)
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#define GPIO_SPI_CS_HMC (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN1)
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#define GPIO_SPI_CS_MPU (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN2)
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#define GPIO_SPI_CS_EXT0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN4)
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#define GPIO_SPI_CS_EXT1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN14)
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#define GPIO_SPI_CS_EXT2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN15)
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#define GPIO_SPI_CS_EXT3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN13)
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#define GPIO_SPI_CS_LIS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN4)
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/*----------------------------------------------------------*/
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/* FMUv2 SPI chip selects and DRDY */
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/*----------------------------------------------------------*/
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/* FMUv2 SPI1 chip selects */
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/* PC1 Spare ADC IN10 */
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#define GPIO_SPI1_CS_PC2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN2)
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#define GPIO_SPI1_CS_PC13 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN13)
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#define GPIO_SPI1_CS_PC15 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN15)
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#define GPIO_SPI1_CS_PD7 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN7)
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/* FMUv2 SPI2 chip selects */
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#define GPIO_SPI2_CS_PD10 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN10)
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/* FMUv2 SPI4 chip selects */
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#define GPIO_SPI4_GPIO_PC14 /* !V2M */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN14)
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#define GPIO_SPI4_NSS_PE4 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN4)
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/* FMUv2 SPI1 chip selects Assignments */
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#define GPIO_SPI1_CS_MPU GPIO_SPI1_CS_PC2
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#define GPIO_SPI1_CS_GYRO GPIO_SPI1_CS_PC13
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#define GPIO_SPI1_CS_ACCEL_MAG GPIO_SPI1_CS_PC15
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#define GPIO_SPI1_CS_BARO GPIO_SPI1_CS_PD7
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/* FMUv2 SPI2 chip selects Assignments */
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#define GPIO_SPI2_CS_FRAM GPIO_SPI2_CS_PD10
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/* FMUv2 SPI4 chip selects Assignments */
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#define GPIO_SPI4_GPIO_EXT GPIO_SPI4_GPIO_PC14
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#define GPIO_SPI4_EXT_NSS GPIO_SPI4_NSS_PE4
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/* FMUv2 DRDY */
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#define GPIO_SPI1_EXTI_DRDY_PB0 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN0)
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#define GPIO_SPI1_EXTI_DRDY_PB1 /*!V3 */ (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN1)
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#define GPIO_SPI1_EXTI_DRDY_PB4 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN4)
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#define GPIO_SPI1_EXTI_DRDY_PD15 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN15)
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/* FMUv2 DRDY Assignments */
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#define GPIO_SPI1_EXTI_GYRO_DRDY GPIO_SPI1_EXTI_DRDY_PB0
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#define GPIO_SPI1_EXTI_MAG_DRDY GPIO_SPI1_EXTI_DRDY_PB1
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#define GPIO_SPI1_EXTI_ACCEL_DRDY GPIO_SPI1_EXTI_DRDY_PB4
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#define GPIO_SPI1_EXTI_MPU_DRDY GPIO_SPI1_EXTI_DRDY_PD15
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/*----------------------------------------------------------*/
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/* End FMUv2 SPI chip selects and DRDY */
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/*----------------------------------------------------------*/
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#define PX4_SPI_BUS_SENSORS 1
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#define PX4_SPI_BUS_RAMTRON 2
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@ -112,27 +190,17 @@
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#define PX4_SPI_BUS_BARO PX4_SPI_BUS_SENSORS
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/* Use these in place of the spi_dev_e enumeration to select a specific SPI device on SPI1 */
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#define PX4_SPIDEV_GYRO 1
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#define PX4_SPIDEV_ACCEL_MAG 2
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#define PX4_SPIDEV_BARO 3
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#define PX4_SPIDEV_MPU 4
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#define PX4_SPIDEV_HMC 5
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#define PX4_SPIDEV_LIS 7
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#define PX4_SPIDEV_BMI 8
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#define PX4_SPIDEV_GYRO 1
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#define PX4_SPIDEV_ACCEL_MAG 2
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#define PX4_SPIDEV_BARO 3
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#define PX4_SPIDEV_MPU 4
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/* External bus */
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#define PX4_SPIDEV_EXT0 1
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#define PX4_SPIDEV_EXT1 2
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#define PX4_SPIDEV_EXT2 3
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#define PX4_SPIDEV_EXT3 4
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/* FMUv3 SPI on external bus */
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#define PX4_SPIDEV_EXT_MPU PX4_SPIDEV_EXT0
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#define PX4_SPIDEV_EXT_BARO PX4_SPIDEV_EXT1
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#define PX4_SPIDEV_EXT_ACCEL_MAG PX4_SPIDEV_EXT2
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#define PX4_SPIDEV_EXT_GYRO PX4_SPIDEV_EXT3
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#define PX4_SPIDEV_EXT_BMI PX4_SPIDEV_EXT_GYRO
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#define PX4_SPIDEV_EXT_MPU 10
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#define PX4_SPIDEV_EXT_GYRO 12
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#define PX4_SPIDEV_EXT_ACCEL_MAG 13
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#define PX4_SPIDEV_EXT_BARO 14
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#define PX4_SPIDEV_EXT_BMI 15
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/* I2C busses */
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#define PX4_I2C_BUS_EXPANSION 1
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@ -626,10 +626,6 @@ __EXPORT int board_app_initialize(uintptr_t arg)
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SPI_SETFREQUENCY(spi1, 10000000);
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SPI_SETBITS(spi1, 8);
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SPI_SETMODE(spi1, SPIDEV_MODE3);
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SPI_SELECT(spi1, PX4_SPIDEV_GYRO, false);
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SPI_SELECT(spi1, PX4_SPIDEV_ACCEL_MAG, false);
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SPI_SELECT(spi1, PX4_SPIDEV_BARO, false);
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SPI_SELECT(spi1, PX4_SPIDEV_MPU, false);
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up_udelay(20);
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/* Get the SPI port for the FRAM */
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@ -649,7 +645,6 @@ __EXPORT int board_app_initialize(uintptr_t arg)
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SPI_SETFREQUENCY(spi2, 12 * 1000 * 1000);
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SPI_SETBITS(spi2, 8);
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SPI_SETMODE(spi2, SPIDEV_MODE3);
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SPI_SELECT(spi2, SPIDEV_FLASH, false);
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spi4 = stm32_spibus_initialize(4);
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@ -657,8 +652,6 @@ __EXPORT int board_app_initialize(uintptr_t arg)
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SPI_SETFREQUENCY(spi4, 10000000);
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SPI_SETBITS(spi4, 8);
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SPI_SETMODE(spi4, SPIDEV_MODE3);
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SPI_SELECT(spi4, PX4_SPIDEV_EXT0, false);
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SPI_SELECT(spi4, PX4_SPIDEV_EXT1, false);
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#ifdef CONFIG_MMCSD
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/* First, get an instance of the SDIO interface */
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@ -69,123 +69,267 @@
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*
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************************************************************************************/
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__EXPORT void stm32_spiinitialize(void)
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{
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#ifdef CONFIG_STM32_SPI1
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stm32_configgpio(GPIO_SPI_CS_GYRO);
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stm32_configgpio(GPIO_SPI_CS_ACCEL_MAG);
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stm32_configgpio(GPIO_SPI_CS_BARO);
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stm32_configgpio(GPIO_SPI_CS_HMC);
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stm32_configgpio(GPIO_SPI_CS_MPU);
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/* Verification
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* PA5 PA6 PA7 PB0 PB1 PB4 PC1 PC2 PC13 PC14 PC15 PD7 PD15 PE2 PE4 PE5 PE6
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* driver X X X X X X
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* local V2 v2 V2 V3 a V2 V2M V2x a a 4
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*/
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static void stm32_spi1_initialize(void)
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{
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stm32_configgpio(GPIO_SPI1_CS_PC2);
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stm32_configgpio(GPIO_SPI1_CS_PD7);
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/* De-activate all peripherals,
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* required for some peripheral
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* state machines
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*/
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stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
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stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
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stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
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stm32_gpiowrite(GPIO_SPI_CS_HMC, 1);
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stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
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stm32_configgpio(GPIO_SPI1_EXTI_DRDY_PD15);
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stm32_configgpio(GPIO_EXTI_GYRO_DRDY);
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stm32_configgpio(GPIO_EXTI_MAG_DRDY);
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stm32_configgpio(GPIO_EXTI_ACCEL_DRDY);
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stm32_configgpio(GPIO_EXTI_MPU_DRDY);
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#endif
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# if !defined(BOARD_HAS_VERSIONING)
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stm32_configgpio(GPIO_SPI1_EXTI_DRDY_PB0);
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stm32_configgpio(GPIO_SPI1_EXTI_DRDY_PB1);
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stm32_configgpio(GPIO_SPI1_EXTI_DRDY_PB4);
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stm32_configgpio(GPIO_SPI1_CS_PC13);
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stm32_configgpio(GPIO_SPI1_CS_PC15);
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# else
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#ifdef CONFIG_STM32_SPI2
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stm32_configgpio(GPIO_SPI_CS_FRAM);
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stm32_gpiowrite(GPIO_SPI_CS_FRAM, 1);
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if (HW_VER_FMUV2 == board_get_hw_version()) {
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stm32_configgpio(GPIO_SPI1_EXTI_DRDY_PB0);
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stm32_configgpio(GPIO_SPI1_EXTI_DRDY_PB1);
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stm32_configgpio(GPIO_SPI1_EXTI_DRDY_PB4);
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stm32_configgpio(GPIO_SPI1_CS_PC13);
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stm32_configgpio(GPIO_SPI1_CS_PC15);
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} else if (HW_VER_FMUV2MINI == board_get_hw_version()) {
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stm32_configgpio(GPIO_SPI1_EXTI_20608_DRDY_PC14);
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stm32_configgpio(GPIO_SPI1_CS_PC15);
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} else if (HW_VER_FMUV3 == board_get_hw_version()) {
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stm32_configgpio(GPIO_SPI1_CS_PC1);
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}
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# endif
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}
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#endif
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#ifdef CONFIG_STM32_SPI4
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stm32_configgpio(GPIO_SPI_CS_EXT0);
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stm32_configgpio(GPIO_SPI_CS_EXT1);
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stm32_configgpio(GPIO_SPI_CS_EXT2);
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stm32_configgpio(GPIO_SPI_CS_EXT3);
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stm32_gpiowrite(GPIO_SPI_CS_EXT0, 1);
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stm32_gpiowrite(GPIO_SPI_CS_EXT1, 1);
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stm32_gpiowrite(GPIO_SPI_CS_EXT2, 1);
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stm32_gpiowrite(GPIO_SPI_CS_EXT3, 1);
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/* Verification
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* PA5 PA6 PA7 PB0 PB1 PB4 PC1 PC2 PC13 PC14 PC15 PD7 PD15 PE2 PE4 PE5 PE6
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* driver X X X X X X
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* local V3 V3 - V3 a V3 V23 V3 - -
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*/
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static void stm32_spi4_initialize(void)
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{
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stm32_configgpio(GPIO_SPI4_NSS_PE4);
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# if !defined(BOARD_HAS_VERSIONING)
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stm32_configgpio(GPIO_SPI4_GPIO_PC14);
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# else
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if (HW_VER_FMUV3 == board_get_hw_version()) {
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stm32_configgpio(GPIO_SPI4_EXTI_DRDY_PB0);
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stm32_configgpio(GPIO_SPI4_CS_PB1);
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stm32_configgpio(GPIO_SPI4_CS_PC13);
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stm32_configgpio(GPIO_SPI4_CS_PC15);
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}
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if (HW_VER_FMUV2MINI != board_get_hw_version()) {
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stm32_configgpio(GPIO_SPI4_GPIO_PC14);
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}
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# endif
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}
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#endif
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__EXPORT void stm32_spiinitialize(void)
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{
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#ifdef CONFIG_STM32_SPI1
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stm32_spi1_initialize();
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#endif
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#ifdef CONFIG_STM32_SPI2
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stm32_configgpio(GPIO_SPI2_CS_PD10);
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#endif
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#ifdef CONFIG_STM32_SPI4
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stm32_spi4_initialize();
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||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STM32_SPI1
|
||||
__EXPORT void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
|
||||
{
|
||||
/* SPI select is active low, so write !selected to select the device */
|
||||
|
||||
# if !defined(BOARD_HAS_VERSIONING)
|
||||
switch (devid) {
|
||||
case PX4_SPIDEV_GYRO:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_GYRO, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_HMC, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC13, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC15, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PD7, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC2, 1);
|
||||
break;
|
||||
|
||||
# if defined(PX4_SPIDEV_ICM_20608)
|
||||
|
||||
case PX4_SPIDEV_ICM_20608:
|
||||
# endif
|
||||
case PX4_SPIDEV_ACCEL_MAG:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_HMC, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC13, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC15, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PD7, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC2, 1);
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_BARO:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_BARO, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_HMC, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_HMC:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_HMC, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_LIS:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_LIS, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC13, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC15, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PD7, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC2, 1);
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_MPU:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_HMC, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_MPU, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC13, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC15, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PD7, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC2, !selected);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
# else // defined(BOARD_HAS_VERSIONING)
|
||||
|
||||
/* SPI select is active low, so write !selected to select the device */
|
||||
/* Verification
|
||||
* PA5 PA6 PA7 PB0 PB1 PB4 PC1 PC2 PC13 PC14 PC15 PD7 PD15 PE2 PE4 PE5 PE6
|
||||
* driver X X X X X X
|
||||
* local - - - V3 a V2 - V2M a - -
|
||||
*/
|
||||
|
||||
switch (devid) {
|
||||
case PX4_SPIDEV_GYRO:
|
||||
|
||||
/* Making sure the other peripherals are not selected */
|
||||
if (HW_VER_FMUV2 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC13, !selected);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 != board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC15, 1);
|
||||
}
|
||||
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PD7, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC2, 1);
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC1, 1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
# if defined(PX4_SPIDEV_ICM_20608)
|
||||
|
||||
case PX4_SPIDEV_ICM_20608:
|
||||
# endif
|
||||
case PX4_SPIDEV_ACCEL_MAG:
|
||||
|
||||
/* Making sure the other peripherals are not selected */
|
||||
if (HW_VER_FMUV2 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC13, 1);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 != board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC15, !selected);
|
||||
}
|
||||
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PD7, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC2, 1);
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC1, 1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_BARO:
|
||||
|
||||
/* Making sure the other peripherals are not selected */
|
||||
if (HW_VER_FMUV2 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC13, 1);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 != board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC15, 1);
|
||||
}
|
||||
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PD7, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC2, 1);
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC1, 1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_MPU:
|
||||
|
||||
/* Making sure the other peripherals are not selected */
|
||||
if (HW_VER_FMUV2 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC13, 1);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 != board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC15, 1);
|
||||
}
|
||||
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PD7, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC2, !selected);
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC1, 1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_HMC:
|
||||
if (HW_VER_FMUV2 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC13, 1);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 != board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC15, 1);
|
||||
}
|
||||
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PD7, 1);
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC2, 1);
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI1_CS_PC1, !selected);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
# endif
|
||||
}
|
||||
|
||||
__EXPORT uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI2
|
||||
__EXPORT void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
|
||||
{
|
||||
/* there can only be one device on this bus, so always select it */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_FRAM, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI2_CS_PD10, !selected);
|
||||
}
|
||||
|
||||
__EXPORT uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
|
||||
|
|
@ -195,93 +339,181 @@ __EXPORT uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devi
|
|||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32_SPI4
|
||||
__EXPORT void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
|
||||
{
|
||||
/* SPI select is active low, so write !selected to select the device */
|
||||
|
||||
# if !defined(BOARD_HAS_VERSIONING)
|
||||
switch (devid) {
|
||||
case PX4_SPIDEV_EXT0:
|
||||
case PX4_SPIDEV_EXT_MPU:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT0, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT1, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT2, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT3, 1);
|
||||
stm32_gpiowrite(GPIO_SPI4_NSS_PE4, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI4_GPIO_PC14, 1);
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_EXT1:
|
||||
case PX4_SPIDEV_EXT_BARO:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT0, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT1, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT2, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT3, 1);
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_EXT2:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT0, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT1, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT2, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT3, 1);
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_EXT3:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT0, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT1, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT2, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_EXT3, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI4_NSS_PE4, 1);
|
||||
stm32_gpiowrite(GPIO_SPI4_GPIO_PC14, !selected);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
#else // defined(BOARD_HAS_VERSIONING)
|
||||
/* SPI select is active low, so write !selected to select the device */
|
||||
/* Verification
|
||||
* PA5 PA6 PA7 PB0 PB1 PB4 PC1 PC2 PC13 PC14 PC15 PD7 PD15 PE2 PE4 PE5 PE6
|
||||
* driver X X X X X X
|
||||
* local - - - - - V3 !V2M V3 - - a
|
||||
*/
|
||||
|
||||
switch (devid) {
|
||||
case PX4_SPIDEV_EXT_MPU:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI4_NSS_PE4, !selected);
|
||||
|
||||
if (HW_VER_FMUV2MINI != board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI4_GPIO_PC14, 1);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI4_CS_PC15, 1);
|
||||
stm32_gpiowrite(GPIO_SPI4_CS_PC13, 1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_EXT_BARO:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI4_NSS_PE4, 1);
|
||||
|
||||
if (HW_VER_FMUV2MINI != board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI4_GPIO_PC14, !selected);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI4_CS_PC15, 1);
|
||||
stm32_gpiowrite(GPIO_SPI4_CS_PC13, 1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
# if defined(PX4_SPIDEV_ICM_20608)
|
||||
|
||||
case PX4_SPIDEV_ICM_20608:
|
||||
# endif
|
||||
case PX4_SPIDEV_EXT_ACCEL_MAG:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI4_NSS_PE4, 1);
|
||||
|
||||
if (HW_VER_FMUV2MINI != board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI4_GPIO_PC14, 1);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI4_CS_PC15, !selected);
|
||||
stm32_gpiowrite(GPIO_SPI4_CS_PC13, 1);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case PX4_SPIDEV_EXT_BMI:
|
||||
case PX4_SPIDEV_EXT_GYRO:
|
||||
/* Making sure the other peripherals are not selected */
|
||||
stm32_gpiowrite(GPIO_SPI4_NSS_PE4, 1);
|
||||
|
||||
if (HW_VER_FMUV2MINI != board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI4_GPIO_PC14, 1);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_gpiowrite(GPIO_SPI4_CS_PC15, 1);
|
||||
stm32_gpiowrite(GPIO_SPI4_CS_PC13, !selected);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
__EXPORT uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* V2, V2M SPI1 All signals SPI4, V3 ALL signals */
|
||||
/* Verification
|
||||
* PA5 PA6 PA7 PB0 PB1 PB4 PC1 PC2 PC13 PC14 PC15 PD7 PD15 PE2 PE4 PE5 PE6
|
||||
* local A A A A A A V3 A A !V2 A A A V3 V3 V3 V3
|
||||
*/
|
||||
|
||||
__EXPORT void board_spi_reset(int ms)
|
||||
{
|
||||
/* disable SPI bus */
|
||||
stm32_configgpio(GPIO_SPI_CS_GYRO_OFF);
|
||||
stm32_configgpio(GPIO_SPI_CS_ACCEL_MAG_OFF);
|
||||
stm32_configgpio(GPIO_SPI_CS_BARO_OFF);
|
||||
stm32_configgpio(GPIO_SPI_CS_MPU_OFF);
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_CS_PC2));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_CS_PC13));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_CS_PC15));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_CS_PD7));
|
||||
|
||||
stm32_gpiowrite(GPIO_SPI_CS_GYRO_OFF, 0);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG_OFF, 0);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_BARO_OFF, 0);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_MPU_OFF, 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_CS_PC2), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_CS_PC13), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_CS_PC15), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_CS_PD7), 0);
|
||||
|
||||
stm32_configgpio(GPIO_SPI1_SCK_OFF);
|
||||
stm32_configgpio(GPIO_SPI1_MISO_OFF);
|
||||
stm32_configgpio(GPIO_SPI1_MOSI_OFF);
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_SCK));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_MISO));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_MOSI));
|
||||
|
||||
stm32_gpiowrite(GPIO_SPI1_SCK_OFF, 0);
|
||||
stm32_gpiowrite(GPIO_SPI1_MISO_OFF, 0);
|
||||
stm32_gpiowrite(GPIO_SPI1_MOSI_OFF, 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_SCK), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_MISO), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_MOSI), 0);
|
||||
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_EXTI_DRDY_PB0));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_EXTI_DRDY_PB1));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_EXTI_DRDY_PB4));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_EXTI_DRDY_PD15));
|
||||
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_EXTI_DRDY_PB0), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_EXTI_DRDY_PB1), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_EXTI_DRDY_PB4), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_EXTI_DRDY_PD15), 0);
|
||||
|
||||
stm32_configgpio(GPIO_GYRO_DRDY_OFF);
|
||||
stm32_configgpio(GPIO_MAG_DRDY_OFF);
|
||||
stm32_configgpio(GPIO_ACCEL_DRDY_OFF);
|
||||
stm32_configgpio(GPIO_EXTI_MPU_DRDY_OFF);
|
||||
#if defined(BOARD_HAS_VERSIONING)
|
||||
|
||||
/* Pixhawk mini has reused the GPIO_SPI_CS_EXT1 signal that was associated
|
||||
* with SPI4. So we must do this only on HW_VER_FMUV2MINI
|
||||
*/
|
||||
if (HW_VER_FMUV2MINI == board_get_hw_version()) {
|
||||
stm32_configgpio(GPIO_20608_DRDY_OFF);
|
||||
stm32_gpiowrite(GPIO_20608_DRDY_OFF, 0);
|
||||
if (HW_VER_FMUV2 != board_get_hw_version()) {
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI4_CS_PC14));
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI4_CS_PC14), 0);
|
||||
}
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI1_CS_PC1));
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI1_CS_PC1), 0);
|
||||
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI4_NSS_PE4));
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI4_NSS_PE4), 0);
|
||||
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI4_SCK));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI4_MISO));
|
||||
stm32_configgpio(_PIN_OFF(GPIO_SPI4_MOSI));
|
||||
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI4_SCK), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI4_MISO), 0);
|
||||
stm32_gpiowrite(_PIN_OFF(GPIO_SPI4_MOSI), 0);
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
stm32_gpiowrite(GPIO_GYRO_DRDY_OFF, 0);
|
||||
stm32_gpiowrite(GPIO_MAG_DRDY_OFF, 0);
|
||||
stm32_gpiowrite(GPIO_ACCEL_DRDY_OFF, 0);
|
||||
|
||||
/* set the sensor rail off */
|
||||
stm32_configgpio(GPIO_VDD_3V3_SENSORS_EN);
|
||||
|
|
@ -300,37 +532,20 @@ __EXPORT void board_spi_reset(int ms)
|
|||
usleep(100);
|
||||
|
||||
/* reconfigure the SPI pins */
|
||||
#ifdef CONFIG_STM32_SPI1
|
||||
stm32_configgpio(GPIO_SPI_CS_GYRO);
|
||||
stm32_configgpio(GPIO_SPI_CS_ACCEL_MAG);
|
||||
stm32_configgpio(GPIO_SPI_CS_BARO);
|
||||
stm32_configgpio(GPIO_SPI_CS_MPU);
|
||||
|
||||
/* De-activate all peripherals,
|
||||
* required for some peripheral
|
||||
* state machines
|
||||
*/
|
||||
stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_ACCEL_MAG, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_BARO, 1);
|
||||
stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
|
||||
|
||||
stm32_configgpio(GPIO_SPI1_SCK);
|
||||
stm32_configgpio(GPIO_SPI1_MISO);
|
||||
stm32_configgpio(GPIO_SPI1_MOSI);
|
||||
|
||||
// FIXME:bring up the EXTI pins again
|
||||
/* Pixhawk mini has reused the GPIO_SPI_CS_EXT1 signal that was associated
|
||||
* with SPI4. So we must do this only on HW_VER_FMUV2MINI
|
||||
*/
|
||||
//if (HW_VER_FMUV2MINI == board_get_hw_version()) {
|
||||
// stm32_configgpio(GPIO_20608_DRDY_OFF);
|
||||
// stm32_gpiowrite(GPIO_20608_DRDY_OFF, 0);
|
||||
//}
|
||||
// stm32_configgpio(GPIO_GYRO_DRDY);
|
||||
// stm32_configgpio(GPIO_MAG_DRDY);
|
||||
// stm32_configgpio(GPIO_ACCEL_DRDY);
|
||||
// stm32_configgpio(GPIO_EXTI_MPU_DRDY);
|
||||
#if defined(BOARD_HAS_VERSIONING)
|
||||
|
||||
if (HW_VER_FMUV3 == board_get_hw_version()) {
|
||||
stm32_configgpio(GPIO_SPI4_SCK);
|
||||
stm32_configgpio(GPIO_SPI4_MISO);
|
||||
stm32_configgpio(GPIO_SPI4_MOSI);
|
||||
stm32_spi4_initialize();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
stm32_spi1_initialize();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,12 +47,141 @@
|
|||
#define BOARD_HAS_SIMPLE_HW_VERSIONING 1
|
||||
#define HW_VER_PB4 (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN4)
|
||||
#define HW_VER_PB12 (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN12)
|
||||
#define HW_VER_PB4_INIT (GPIO_EXTI_ACCEL_DRDY)
|
||||
#define HW_VER_PB4_INIT (GPIO_SPI1_EXTI_DRDY_PB4)
|
||||
#define HW_VER_PB12_INIT (GPIO_INPUT|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
|
||||
#define HW_VER_FMUV2_STATE 0x8 /* PB12:PU:1 PB12:PD:0 PB4:PU:0 PB4PD:0 */
|
||||
#define HW_VER_FMUV3_STATE 0xE /* PB12:PU:1 PB12:PD:1 PB4:PU:1 PB4PD:0 */
|
||||
#define HW_VER_FMUV2MINI_STATE 0xA /* PB12:PU:1 PB12:PD:0 PB4:PU:1 PB4PD:0 */
|
||||
#define HW_VER_TYPE_INIT {'V','2',0, 0}
|
||||
|
||||
/*----------------------------------------------------------*/
|
||||
/* FMUv3 Cube SPI chip selects and DRDY */
|
||||
/*----------------------------------------------------------*/
|
||||
/* Due to inconsistent use of chip select and dry signal on
|
||||
* different board that use this build. We are defining the GPIO
|
||||
* inclusive of the SPI port and GPIO to help identify pins the
|
||||
* are part of the sensor Net's controlled by different power
|
||||
* domains.
|
||||
*
|
||||
* --------------- SPI1 -------------------- SPI4 -------------- Incompatibilities ---------
|
||||
* FMUv3 Cube: FmuV2 PixhawkMini
|
||||
* Power Domain: VDD_3V3_SENSORS_EN NA V3V:SPI V5:SPI4 V3V:SPI1 No SPI4
|
||||
* PA5 SPI_INT_SCK
|
||||
* PA6 SPI_INT_MISO
|
||||
* PA7 SPI_INT_MOSI
|
||||
* PB0 EXTERN_DRDY SPI1:GYRO_DRDY NC
|
||||
* PB1 MAG_DRDY nEXTERN_CS -SPI1:MAG_DRDY NC
|
||||
* PB4 NC SPI1:ACCEL_DRDY NC
|
||||
* PC1 SPI_INT_MAG_!CS -ADC1_IN11 NC
|
||||
* PC2 nMPU_CS @MPU6000 @MPU9250
|
||||
* PC13 nGYRO_EXT_CS SPI1:nGYRO_CS NC
|
||||
* PC14 nBARO_EXT_CS GPIO_EXT_1 -20608_DRDY
|
||||
* PC15 nACCEL_MAG_EXT_CS SPI1:nACCEL_MAG_CS 20608_CS
|
||||
* PD7 nBARO_CS
|
||||
* PD15 nMPU_DRDY @MPU6000 @MPU9250
|
||||
* PE2 SPI_EXT_SCK NC
|
||||
* PE4 MPU_EXT_CS SPI4:nSPI_EXT_NSS NC
|
||||
* PE5 SPI_EXT_MISO NC
|
||||
* PE6 SPI_EXT_MOSI NC
|
||||
*
|
||||
*
|
||||
* Notes: Prefixed with @ Does not effect board control
|
||||
* Prefixed with + Input used as Output
|
||||
* Prefixed with - Output used as Input
|
||||
* Prefixed with SPIn: Bus changed
|
||||
*
|
||||
*/
|
||||
|
||||
/* FMUv3 Cube SPI1 chip selects */
|
||||
/* Was a spare ACD IN10 on V2 */
|
||||
#define GPIO_SPI1_CS_PC1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_SPI4_CS_PB1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_SPI4_CS_PC13 GPIO_SPI1_CS_PC13
|
||||
#define GPIO_SPI4_CS_PC14 GPIO_SPI4_GPIO_PC14
|
||||
#define GPIO_SPI4_CS_PC15 GPIO_SPI1_CS_PC15
|
||||
|
||||
/* FMUv3 Cube chip selects Assignments */
|
||||
/* Cube 2.0 V2.1 */
|
||||
#define GPIO_SPI1_CS_MPU GPIO_SPI1_CS_PC2 /* MPU600 MPU9250 */
|
||||
#define GPIO_SPI1_CS_BARO GPIO_SPI1_CS_PD7 /* MS5611 MS5611 */
|
||||
#define GPIO_SPI1_CS_HMC GPIO_SPI1_CS_PC1 /* HMC5983 Removed */
|
||||
|
||||
/* N.B. bus moves from SPI1 to SPI4 */
|
||||
#define GPIO_SPI4_GYRO_EXT_CS GPIO_SPI4_CS_PC13
|
||||
#define GPIO_SPI4_BARO_EXT_CS GPIO_SPI4_CS_PC14
|
||||
#define GPIO_SPI4_ACCEL_MAG_EXT_CS GPIO_SPI4_CS_PC15
|
||||
|
||||
/* No move */
|
||||
#define GPIO_SPI4_MPU_EXT_CS GPIO_SPI4_NSS_PE4
|
||||
|
||||
/* FMUv3 DRDY Assignments */
|
||||
#define GPIO_SPI4_EXTI_DRDY_PB0 GPIO_SPI1_EXTI_DRDY_PB0
|
||||
#define GPIO_SPI4_EXTI_EXTERN_DRDY GPIO_SPI4_EXTI_DRDY_PB0
|
||||
#define GPIO_SPI4_EXTERN_CS GPIO_SPI4_CS_PB1
|
||||
/* PB1 is an External CS on V3 */
|
||||
|
||||
#define PX4_SPIDEV_HMC 5
|
||||
|
||||
/*----------------------------------------------------------*/
|
||||
/* End FMUv3 Cube SPI chip selects and DRDY */
|
||||
/*----------------------------------------------------------*/
|
||||
/*----------------------------------------------------------*/
|
||||
/* Due to inconsistent use of chip select and dry signal on
|
||||
* different board that use this build. We are defining the GPIO
|
||||
* inclusive of the SPI port and GPIO to help identify pins the
|
||||
* are part of the sensor Net's controlled by different power
|
||||
* domains.
|
||||
*
|
||||
* --------------- SPI1 -------------------- SPI4 -------------- Incompatibilities ---------
|
||||
* FMUv2 Pixhawk Mini FmuV2 FmuV3 Cube
|
||||
* Power Domain: VDD_3V3_SENSORS_EN NA V3V:SPI V5:SPI4 V3V:SPI1&SPI4
|
||||
* PA5 SPI_INT_SCK
|
||||
* PA6 SPI_INT_MISO
|
||||
* PA7 SPI_INT_MOSI
|
||||
* PB0 NC SPI1:GYRO_DRDY SPI4:EXTERN_DRDY
|
||||
* PB1 NC -SPI1:MAG_DRDY +SPI4:nEXTERN_CS
|
||||
* PB4 NC SPI1:ACCEL_DRDY NC
|
||||
* PC1 Spare ADC ( NC ) +SPI1:SPI_INT_MAG_!CS
|
||||
* PC2 nMPU_CS @MPU6000 @MPU6000|MPU9250
|
||||
* PC13 NC SPI1:nGYRO_CS SPI4:nGYRO_EXT_CS
|
||||
* PC14 20608_DRDY +GPIO_EXT_1 nBARO_EXT_CS
|
||||
* PC15 20608_CS nACCEL_MAG_CS SPI4:nACCEL_MAG_EXT_CS
|
||||
* PD7 nBARO_CS
|
||||
* PD15 nMPU_DRDY @MPU6000 @MPU6000|MPU9250
|
||||
* PE2 NC SPI_EXT_SCK SPI_EXT_SCK
|
||||
* PE4 NC SPI4:nSPI_EXT_NSS SPI4:nMPU_EXT_CS
|
||||
* PE5 NC SPI_EXT_MISO SPI_EXT_MISO
|
||||
* PE6 NC SPI_EXT_MOSI SPI_EXT_MOSI
|
||||
*
|
||||
* Notes: Prefixed with @ Does not effect board control
|
||||
* Prefixed with + Input used as Output
|
||||
* Prefixed with - Output used as Input
|
||||
* Prefixed with SPIn: Bus changed
|
||||
*
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------*/
|
||||
/* FMUv2 PixhawkMini SPI chip selects and DRDY */
|
||||
/*----------------------------------------------------------*/
|
||||
|
||||
/* FMUv2 PixhawkMini SPI1 chip selects */
|
||||
|
||||
/* FMUv3 Cube chip selects Assignments */
|
||||
|
||||
#define GPIO_SPI1_CS_MPU GPIO_SPI1_CS_PC2 /* MPU9250 */
|
||||
#define GPIO_SPI1_CS_BARO GPIO_SPI1_CS_PD7 /* MS5611 */
|
||||
#define GPIO_SPI1_CS_20608 GPIO_SPI1_CS_PC15 /* ICM20608 */
|
||||
|
||||
/* FMUv3 DRDY Assignments */
|
||||
|
||||
/* Pixhawk mini has reused the PC14 GPIO_SPI_CS_EXT1 signal that was associated
|
||||
* with SPI4.
|
||||
*/
|
||||
#define GPIO_SPI1_EXTI_20608_DRDY_PC14 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN14)
|
||||
|
||||
#define PX4_SPIDEV_ICM_20608 6 /* ICM_20608 on PC15 */
|
||||
|
||||
/*----------------------------------------------------------*/
|
||||
/* FMUv2 PixhawkMini SPI chip selects and DRDY */
|
||||
/*----------------------------------------------------------*/
|
||||
#include "../px4fmu-v2/board_config.h"
|
||||
#define PX4_SPIDEV_ICM_20608 PX4_SPIDEV_ACCEL_MAG // PixhawkMini has ICM_20608 on GPIO_SPI_CS_ACCEL_MAG
|
||||
|
|
|
|||
Loading…
Reference in New Issue