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Add lpc178x_iocon.h from Rommel Marcelo
git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5550 42af7a65-404d-4744-a932-0658087f49c3
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/************************************************************************************
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* arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Rommel Marcelo
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* Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_IOCON_H
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#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_IOCON_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/lpc17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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#define LPC17_IOCON_P0_OFFSET (LPC17_IOCON_BASE+0x0000)
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#define LPC17_IOCON_P1_OFFSET (LPC17_IOCON_BASE+0x0080)
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#define LPC17_IOCON_P2_OFFSET (LPC17_IOCON_BASE+0x0100)
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#define LPC17_IOCON_P3_OFFSET (LPC17_IOCON_BASE+0x0180)
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#define LPC17_IOCON_P4_OFFSET (LPC17_IOCON_BASE+0x0200)
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#define LPC17_IOCON_P5_OFFSET (LPC17_IOCON_BASE+0x0280)
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#define LPC17_IOCON_PP0_OFFSET (0x0000) /* IOCON Port(n) register 0 */
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#define LPC17_IOCON_PP1_OFFSET (0x0004) /* IOCON Port(n) register 1 */
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#define LPC17_IOCON_PP2_OFFSET (0x0008) /* IOCON Port(n) register 2 */
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#define LPC17_IOCON_PP3_OFFSET (0x000c) /* IOCON Port(n) register 3 */
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#define LPC17_IOCON_PP4_OFFSET (0x0010) /* IOCON Port(n) register 4 */
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#define LPC17_IOCON_PP5_OFFSET (0x0014) /* IOCON Port(n) register 5 */
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#define LPC17_IOCON_PP6_OFFSET (0x0018) /* IOCON Port(n) register 6 */
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#define LPC17_IOCON_PP7_OFFSET (0x001c) /* IOCON Port(n) register 7 */
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#define LPC17_IOCON_PP8_OFFSET (0x0020) /* IOCON Port(n) register 8 */
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#define LPC17_IOCON_PP9_OFFSET (0x0024) /* IOCON Port(n) register 9 */
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#define LPC17_IOCON_PP10_OFFSET (0x0028) /* IOCON Port(n) register 10 */
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#define LPC17_IOCON_PP11_OFFSET (0x002c) /* IOCON Port(n) register 11 */
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#define LPC17_IOCON_PP12_OFFSET (0x0030) /* IOCON Port(n) register 12 */
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#define LPC17_IOCON_PP13_OFFSET (0x0034) /* IOCON Port(n) register 13 */
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#define LPC17_IOCON_PP14_OFFSET (0x0038) /* IOCON Port(n) register 14 */
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#define LPC17_IOCON_PP15_OFFSET (0x003c) /* IOCON Port(n) register 15 */
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#define LPC17_IOCON_PP16_OFFSET (0x0040) /* IOCON Port(n) register 16 */
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#define LPC17_IOCON_PP17_OFFSET (0x0044) /* IOCON Port(n) register 17 */
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#define LPC17_IOCON_PP18_OFFSET (0x0048) /* IOCON Port(n) register 18 */
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#define LPC17_IOCON_PP19_OFFSET (0x004c) /* IOCON Port(n) register 19 */
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#define LPC17_IOCON_PP20_OFFSET (0x0050) /* IOCON Port(n) register 20 */
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#define LPC17_IOCON_PP21_OFFSET (0x0054) /* IOCON Port(n) register 21 */
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#define LPC17_IOCON_PP22_OFFSET (0x0058) /* IOCON Port(n) register 22 */
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#define LPC17_IOCON_PP23_OFFSET (0x005c) /* IOCON Port(n) register 23 */
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#define LPC17_IOCON_PP24_OFFSET (0x0060) /* IOCON Port(n) register 24 */
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#define LPC17_IOCON_PP25_OFFSET (0x0064) /* IOCON Port(n) register 25 */
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#define LPC17_IOCON_PP26_OFFSET (0x0068) /* IOCON Port(n) register 26 */
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#define LPC17_IOCON_PP27_OFFSET (0x006c) /* IOCON Port(n) register 27 */
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#define LPC17_IOCON_PP28_OFFSET (0x0070) /* IOCON Port(n) register 28 */
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#define LPC17_IOCON_PP29_OFFSET (0x0074) /* IOCON Port(n) register 29 */
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#define LPC17_IOCON_PP30_OFFSET (0x0078) /* IOCON Port(n) register 30 */
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#define LPC17_IOCON_PP31_OFFSET (0x007c) /* IOCON Port(n) register 31 */
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/* Register addresses ***************************************************************/
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//~ #define LPC17_IOCON_PP1(portoffset) (portoffset+LPC17_IOCON_P0_OFFSET)
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/* Register bit definitions *********************************************************/
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/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */
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/* IOCON pin function select */
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#define IOCON_FUNC_GPIO (0)
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#define IOCON_FUNC_ALT1 (1)
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#define IOCON_FUNC_ALT2 (2)
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#define IOCON_FUNC_ALT3 (3)
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#define IOCON_FUNC_ALT4 (4)
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#define IOCON_FUNC_ALT5 (5)
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#define IOCON_FUNC_ALT6 (6)
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#define IOCON_FUNC_ALT7 (7)
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#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */
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#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT)
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#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */
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#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT )
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#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */
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#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT)
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#define IOCON_INV_SHIFT (6) /* Bit 6: Typ D,A,I,W */
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#define IOCON_INV_MASK (1 << IOCON_INV_SHIFT)
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#define IOCON_ADMODE_SHIFT (7) /* Bit 7: Type A */
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#define IOCON_ADMODE_MASK (1 << IOCON_ADMODE_SHIFT)
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#define IOCON_FILTER_SHIFT (8) /* Bit 8: Type A */
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#define IOCON_FILTER_MASK (1 << IOCON_FILTER_SHIFT)
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#define IOCON_SLEW_SHIFT (9) /* Bit 9: Type W*/
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#define IOCON_SLEW_MASK (1 << IOCON_SLEW_SHIFT)
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#define IOCON_HIDRIVE_SHIFT (9) /* Bit 9: Type I */
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#define IOCON_HIDRIVE_MASK (1 << IOCON_HIDRIVE_SHIFT)
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#define IOCON_OD_SHIFT (10) /* Bit 10: Type D,A,W */
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#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT)
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#define IOCON_DACEN_SHIFT (16) /* Bit 16: Type A */
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#define IOCON_DACEN_MASK (1 << IOCON_DACEN_SHIFT)
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/* Pin modes */
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#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */
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#define IOCON_MODE_PD (1) /* 00: pin has a pull-down resistor enabled */
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#define IOCON_MODE_PU (2) /* 00: pin has a pull-up resistor enabled */
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#define IOCON_MODE_RM (3) /* 00: pin has repeater mode enabled */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_IOCON_H */
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@ -47,7 +47,7 @@
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#if defined(LPC176x)
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#if defined(LPC176x)
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# include "chip/lpc176x_pinconn.h"
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# include "chip/lpc176x_pinconn.h"
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#elif defined(LPC178x)
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#elif defined(LPC178x)
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# include "chip/lpc178x_pinconn.h"
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# include "chip/lpc178x_iocon.h"
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#else
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#else
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# error "Unrecognized LPC17xx family"
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# error "Unrecognized LPC17xx family"
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#endif
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#endif
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