mro ctrl-zero-h7:Add remaining SRAM4 & DTCM to heap

This commit is contained in:
David Sidrane 2021-04-01 10:38:59 -07:00 committed by Daniel Agar
parent 5c7a9204a2
commit 2f9a57c604
2 changed files with 6 additions and 4 deletions

View File

@ -90,6 +90,7 @@ CONFIG_MEMSET_OPTSPEED=y
CONFIG_MMCSD=y
CONFIG_MMCSD_SDIO=y
CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y
CONFIG_MM_REGIONS=4
CONFIG_MTD=y
CONFIG_MTD_BYTE_WRITE=y
CONFIG_MTD_PARTITION=y
@ -163,8 +164,6 @@ CONFIG_STM32H7_BKPSRAM=y
CONFIG_STM32H7_DMA1=y
CONFIG_STM32H7_DMA2=y
CONFIG_STM32H7_DMACAPABLE=y
CONFIG_STM32H7_DTCMEXCLUDE=y
CONFIG_STM32H7_DTCM_PROCFS=y
CONFIG_STM32H7_FLOWCONTROL_BROKEN=y
CONFIG_STM32H7_I2C1=y
CONFIG_STM32H7_I2C_DYNTIMEO=y
@ -215,8 +214,8 @@ CONFIG_UART7_RXBUFSIZE=600
CONFIG_UART7_TXBUFSIZE=1500
CONFIG_UART8_BAUD=57600
CONFIG_UART8_RXBUFSIZE=600
CONFIG_UART8_TXBUFSIZE=1500
CONFIG_UART8_SERIAL_CONSOLE=y
CONFIG_UART8_TXBUFSIZE=1500
CONFIG_USART2_BAUD=57600
CONFIG_USART2_IFLOWCONTROL=y
CONFIG_USART2_OFLOWCONTROL=y

View File

@ -199,8 +199,11 @@ SECTIONS
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
.sram4 (NOLOAD) :
.sram4_reserve (NOLOAD) :
{
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > SRAM4