From 1fc1a81d8fc574001d120dff8516e92369bce1d1 Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Wed, 26 Oct 2022 09:49:45 +0200 Subject: [PATCH] UCANS32K146 Add support for 2nd PWM --- boards/nxp/ucans32k146/src/board_config.h | 4 ++-- boards/nxp/ucans32k146/src/timer_config.cpp | 13 ++++++++++++- .../src/px4/nxp/s32k1xx/include/px4_arch/io_timer.h | 4 ++-- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/boards/nxp/ucans32k146/src/board_config.h b/boards/nxp/ucans32k146/src/board_config.h index 3e97c8d76b..ea591a9f03 100644 --- a/boards/nxp/ucans32k146/src/board_config.h +++ b/boards/nxp/ucans32k146/src/board_config.h @@ -99,14 +99,14 @@ __BEGIN_DECLS /* Timer I/O PWM and capture * - * ?? PWM outputs are configured. + * 2 PWM outputs are configured. * ?? Timer inputs are configured. * * Pins: * Defined in board.h */ -#define DIRECT_PWM_OUTPUT_CHANNELS 1 +#define DIRECT_PWM_OUTPUT_CHANNELS 2 #define BOARD_HAS_LED_PWM 1 diff --git a/boards/nxp/ucans32k146/src/timer_config.cpp b/boards/nxp/ucans32k146/src/timer_config.cpp index 104936e7a6..7106489b39 100644 --- a/boards/nxp/ucans32k146/src/timer_config.cpp +++ b/boards/nxp/ucans32k146/src/timer_config.cpp @@ -105,11 +105,13 @@ #define rPWMLOAD(t) REG(t,S32K1XX_FTM_PWMLOAD_OFFSET) constexpr io_timers_t io_timers[MAX_IO_TIMERS] = { + initIOTimer(Timer::FTM1), initIOTimer(Timer::FTM2), }; constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = { initIOTimerChannel(io_timers, {Timer::FTM2, Timer::Channel1}, {GPIO::PortA, GPIO::Pin0}), + initIOTimerChannel(io_timers, {Timer::FTM1, Timer::Channel1}, {GPIO::PortA, GPIO::Pin1}), }; constexpr io_timers_channel_mapping_t io_timers_channel_mapping = @@ -154,17 +156,26 @@ void ucans32k_timer_initialize(void) regval |= FTM_SC_CLKS_FTM; _REG(S32K1XX_FTM0_SC) = regval; + regval = _REG(S32K1XX_FTM1_SC); + regval &= ~(FTM_SC_CLKS_MASK); + regval |= FTM_SC_CLKS_FTM; + _REG(S32K1XX_FTM1_SC) = regval; + regval = _REG(S32K1XX_FTM2_SC); regval &= ~(FTM_SC_CLKS_MASK); regval |= FTM_SC_CLKS_FTM; _REG(S32K1XX_FTM2_SC) = regval; - /* Enabled System Clock Gating Control for FTM0, and FTM2 */ + /* Enabled System Clock Gating Control for FTM0, FTM1 and FTM2 */ regval = _REG(S32K1XX_PCC_FTM0); regval |= PCC_CGC; _REG(S32K1XX_PCC_FTM0) = regval; + regval = _REG(S32K1XX_PCC_FTM1); + regval |= PCC_CGC; + _REG(S32K1XX_PCC_FTM1) = regval; + regval = _REG(S32K1XX_PCC_FTM2); regval |= PCC_CGC; _REG(S32K1XX_PCC_FTM2) = regval; diff --git a/platforms/nuttx/src/px4/nxp/s32k1xx/include/px4_arch/io_timer.h b/platforms/nuttx/src/px4/nxp/s32k1xx/include/px4_arch/io_timer.h index 71a026b5c5..c62ee30e58 100644 --- a/platforms/nuttx/src/px4/nxp/s32k1xx/include/px4_arch/io_timer.h +++ b/platforms/nuttx/src/px4/nxp/s32k1xx/include/px4_arch/io_timer.h @@ -45,8 +45,8 @@ #pragma once __BEGIN_DECLS /* configuration limits */ -#define MAX_IO_TIMERS 1 -#define MAX_TIMER_IO_CHANNELS 1 +#define MAX_IO_TIMERS 2 +#define MAX_TIMER_IO_CHANNELS 2 #define MAX_LED_TIMERS 1 #define MAX_TIMER_LED_CHANNELS 3