forked from Archive/PX4-Autopilot
Add LPC43 SD/MMC header file
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4896 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
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commit
1cfaf7bb07
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/************************************************************************************
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* arch/arm/src/lpc43xx/lpc43_adc.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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#define LPC43_ADC_CR_OFFSET 0x0000 /* A/D Control Register */
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#define LPC43_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */
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#define LPC43_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */
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#define LPC43_ADC_DR_OFFSET(n) (0x0010+((n) << 2))
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#define LPC43_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */
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#define LPC43_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */
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#define LPC43_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */
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#define LPC43_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */
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#define LPC43_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */
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#define LPC43_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */
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#define LPC43_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */
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#define LPC43_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */
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#define LPC43_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */
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/* Register addresses ***************************************************************/
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#define LPC43_ADC0_CR (LPC43_ADC0_BASE+LPC43_ADC_CR_OFFSET)
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#define LPC43_ADC0_GDR (LPC43_ADC0_BASE+LPC43_ADC_GDR_OFFSET)
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#define LPC43_ADC0_INTEN (LPC43_ADC0_BASE+LPC43_ADC_INTEN_OFFSET)
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#define LPC43_ADC0_DR(n) (LPC43_ADC0_BASE+LPC43_ADC_DR_OFFSET(n))
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#define LPC43_ADC0_DR0 (LPC43_ADC0_BASE+LPC43_ADC_DR0_OFFSET)
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#define LPC43_ADC0_DR1 (LPC43_ADC0_BASE+LPC43_ADC_DR1_OFFSET)
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#define LPC43_ADC0_DR2 (LPC43_ADC0_BASE+LPC43_ADC_DR2_OFFSET)
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#define LPC43_ADC0_DR3 (LPC43_ADC0_BASE+LPC43_ADC_DR3_OFFSET)
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#define LPC43_ADC0_DR4 (LPC43_ADC0_BASE+LPC43_ADC_DR4_OFFSET)
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#define LPC43_ADC0_DR5 (LPC43_ADC0_BASE+LPC43_ADC_DR5_OFFSET)
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#define LPC43_ADC0_DR6 (LPC43_ADC0_BASE+LPC43_ADC_DR6_OFFSET)
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#define LPC43_ADC0_DR7 (LPC43_ADC0_BASE+LPC43_ADC_DR7_OFFSET)
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#define LPC43_ADC0_STAT (LPC43_ADC0_BASE+LPC43_ADC_STAT_OFFSET)
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#define LPC43_ADC1_CR (LPC43_ADC1_BASE+LPC43_ADC_CR_OFFSET)
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#define LPC43_ADC1_GDR (LPC43_ADC1_BASE+LPC43_ADC_GDR_OFFSET)
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#define LPC43_ADC1_INTEN (LPC43_ADC1_BASE+LPC43_ADC_INTEN_OFFSET)
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#define LPC43_ADC1_DR(n) (LPC43_ADC1_BASE+LPC43_ADC_DR_OFFSET(n))
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#define LPC43_ADC1_DR0 (LPC43_ADC1_BASE+LPC43_ADC_DR0_OFFSET)
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#define LPC43_ADC1_DR1 (LPC43_ADC1_BASE+LPC43_ADC_DR1_OFFSET)
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#define LPC43_ADC1_DR2 (LPC43_ADC1_BASE+LPC43_ADC_DR2_OFFSET)
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#define LPC43_ADC1_DR3 (LPC43_ADC1_BASE+LPC43_ADC_DR3_OFFSET)
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#define LPC43_ADC1_DR4 (LPC43_ADC1_BASE+LPC43_ADC_DR4_OFFSET)
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#define LPC43_ADC1_DR5 (LPC43_ADC1_BASE+LPC43_ADC_DR5_OFFSET)
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#define LPC43_ADC1_DR6 (LPC43_ADC1_BASE+LPC43_ADC_DR6_OFFSET)
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#define LPC43_ADC1_DR7 (LPC43_ADC1_BASE+LPC43_ADC_DR7_OFFSET)
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#define LPC43_ADC1_STAT (LPC43_ADC1_BASE+LPC43_ADC_STAT_OFFSET)
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/* Register bit definitions *********************************************************/
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/* A/D Control Register */
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#define ADC_CR_SEL_SHIFT (0) /* Bits 0-7: Selects pins to be sampled */
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#define ADC_CR_SEL_MASK (0xff << ADC_CR_SEL_MASK)
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#define ADC_CR_CLKDIV_SHIFT (8) /* Bits 8-15: APB clock (PCLK_ADC0) divisor */
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#define ADC_CR_CLKDIV_MASK (0xff << ADC_CR_CLKDIV_SHIFT)
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#define ADC_CR_BURST (1 << 16) /* Bit 16: A/D Repeated conversions */
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#define ADC_CR_CLKS_SHIFT (17) /* Bits 17-19: Number of clocks in conversion */
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#define ADC_CR_CLKS_MASK (7 << ADC_CR_CLKS_SHIFT)
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# define ADC_CR_CLKS_11 (0 << ADC_CR_CLKS_SHIFT) /* 11 clocks / 10 bits */
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# define ADC_CR_CLKS_10 (1 << ADC_CR_CLKS_SHIFT) /* 10 clocks / 9 bits */
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# define ADC_CR_CLKS_9 (2 << ADC_CR_CLKS_SHIFT) /* 9 clocks / 8 bits */
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# define ADC_CR_CLKS_8 (3 << ADC_CR_CLKS_SHIFT) /* 8 clocks / 7 bits */
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# define ADC_CR_CLKS_7 (4 << ADC_CR_CLKS_SHIFT) /* 7 clocks / 6 bits */
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# define ADC_CR_CLKS_6 (5 << ADC_CR_CLKS_SHIFT) /* 6 clocks / 5 bits */
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# define ADC_CR_CLKS_5 (6 << ADC_CR_CLKS_SHIFT) /* 5 clocks / 4 bits */
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# define ADC_CR_CLKS_4 (7 << ADC_CR_CLKS_SHIFT) /* 4 clocks / 3 bits */
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/* Bit 20: Reserved */
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#define ADC_CR_PDN (1 << 21) /* Bit 21: A/D converter power-down mode */
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/* Bits 22-23: Reserved */
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#define ADC_CR_START_SHIFT (24) /* Bits 24-26: Control A/D conversion start */
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#define ADC_CR_START_MASK (7 << ADC_CR_START_SHIFT)
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# define ADC_CR_START_NOSTART (0 << ADC_CR_START_SHIFT) /* No start */
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# define ADC_CR_START_NOW (1 << ADC_CR_START_SHIFT) /* Start now */
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# define ADC_CR_START_CTOUT15 (2 << ADC_CR_START_SHIFT) /* Start when edge on CTOUT_15 */
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# define ADC_CR_START_CTOUT8 (3 << ADC_CR_START_SHIFT) /* Start when edge on CTOUT_8 */
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# define ADC_CR_START_ADCTRIG0 (4 << ADC_CR_START_SHIFT) /* Start when edge on ADCTRIG0 */
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# define ADC_CR_START_ADCTRIG1 (5 << ADC_CR_START_SHIFT) /* Start when edge on ADCTRIG1 */
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# define ADC_CR_START_MCPWM (6 << ADC_CR_START_SHIFT) /* Start when edge on MCPWM */
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#define ADC_CR_EDGE (1 << 27) /* Bit 27: Start on falling edge */
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/* Bits 28-31: Reserved */
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/* A/D Global Data Register */
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/* Bits 0-3: Reserved */
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#define ADC_GDR_VVREF_SHIFT (6) /* Bits 6-15: Result of conversion (DONE==1) */
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#define ADC_GDR_VVREF_MASK (0x03ff << ADC_GDR_VVREF_SHIFT)
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/* Bits 16-23: Reserved */
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#define ADC_GDR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */
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#define ADC_GDR_CHAN_MASK (3 << ADC_GDR_CHN_SHIFT)
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/* Bits 27-29: Reserved */
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#define ADC_GDR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/
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#define ADC_GDR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/
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/* A/D Interrupt Enable Register */
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#define ADC_INTEN_CHAN(n) (1 << (n))
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#define ADC_INTEN_CHAN0 (1 << 0) /* Bit 0: Enable ADC chan 0 complete intterrupt */
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#define ADC_INTEN_CHAN1 (1 << 1) /* Bit 1: Enable ADC chan 1 complete interrupt */
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#define ADC_INTEN_CHAN2 (1 << 2) /* Bit 2: Enable ADC chan 2 complete interrupt */
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#define ADC_INTEN_CHAN3 (1 << 3) /* Bit 3: Enable ADC chan 3 complete interrupt */
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#define ADC_INTEN_CHAN4 (1 << 4) /* Bit 4: Enable ADC chan 4 complete interrupt */
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#define ADC_INTEN_CHAN5 (1 << 5) /* Bit 5: Enable ADC chan 5 complete interrupt */
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#define ADC_INTEN_CHAN6 (1 << 6) /* Bit 6: Enable ADC chan 6 complete interrupt */
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#define ADC_INTEN_CHAN7 (1 << 7) /* Bit 7: Enable ADC chan 7 complete interrupt */
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#define ADC_INTEN_GLOBAL (1 << 8) /* Bit 8: Only the global DONE generates interrupt */
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/* Bits 9-31: Reserved */
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/* Channel 0-7 A/D Data Register */
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/* Bits 0-3: Reserved */
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#define ADC_DR_VVREF_SHIFT (6) /* Bits 6-15: Result of conversion (DONE==1) */
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#define ADC_DR_VVREF_MASK (0x03ff << ADC_DR_VVREF_SHIFT)
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/* Bits 16-29: Reserved */
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#define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/
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#define ADC_DR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/
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/* A/D Status Register */
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#define ADC_STAT_DONE(n) (1 << (n))
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#define ADC_STAT_DONE0 (1 << 0) /* Bit 0: A/D chan 0 DONE */
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#define ADC_STAT_DONE1 (1 << 1) /* Bit 1: A/D chan 1 DONE */
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#define ADC_STAT_DONE2 (1 << 2) /* Bit 2: A/D chan 2 DONE */
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#define ADC_STAT_DONE3 (1 << 3) /* Bit 3: A/D chan 3 DONE */
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#define ADC_STAT_DONE4 (1 << 4) /* Bit 4: A/D chan 4 DONE */
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#define ADC_STAT_DONE5 (1 << 5) /* Bit 5: A/D chan 5 DONE */
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#define ADC_STAT_DONE6 (1 << 6) /* Bit 6: A/D chan 6 DONE */
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#define ADC_STAT_DONE7 (1 << 7) /* Bit 7: A/D chan 7 DONE */
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#define ADC_STAT_OVERRUN(n) ((1 << (n)) + 8)
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#define ADC_STAT_OVERRUN0 (1 << 8) /* Bit 8: A/D chan 0 OVERRUN */
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#define ADC_STAT_OVERRUN1 (1 << 9) /* Bit 9: A/D chan 1 OVERRUN */
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#define ADC_STAT_OVERRUN2 (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */
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#define ADC_STAT_OVERRUN3 (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */
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#define ADC_STAT_OVERRUN4 (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */
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#define ADC_STAT_OVERRUN5 (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */
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#define ADC_STAT_OVERRUN6 (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */
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#define ADC_STAT_OVERRUN7 (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */
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#define ADC_STAT_INT (1 << 16) /* Bit 15: A/D interrupt */
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/* Bits 17-31: Reserved */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H */
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/************************************************************************************
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* arch/arm/src/lpc43xx/lpc43_adc.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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#define LPC43_ADC_CR_OFFSET 0x0000 /* A/D Control Register */
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#define LPC43_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */
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#define LPC43_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */
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#define LPC43_ADC_DR_OFFSET(n) (0x0010+((n) << 2))
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#define LPC43_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */
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#define LPC43_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */
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#define LPC43_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */
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#define LPC43_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */
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#define LPC43_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */
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#define LPC43_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */
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#define LPC43_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */
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#define LPC43_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */
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#define LPC43_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */
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/* Register addresses ***************************************************************/
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#define LPC43_ADC0_CR (LPC43_ADC0_BASE+LPC43_ADC_CR_OFFSET)
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#define LPC43_ADC0_GDR (LPC43_ADC0_BASE+LPC43_ADC_GDR_OFFSET)
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#define LPC43_ADC0_INTEN (LPC43_ADC0_BASE+LPC43_ADC_INTEN_OFFSET)
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#define LPC43_ADC0_DR(n) (LPC43_ADC0_BASE+LPC43_ADC_DR_OFFSET(n))
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#define LPC43_ADC0_DR0 (LPC43_ADC0_BASE+LPC43_ADC_DR0_OFFSET)
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#define LPC43_ADC0_DR1 (LPC43_ADC0_BASE+LPC43_ADC_DR1_OFFSET)
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#define LPC43_ADC0_DR2 (LPC43_ADC0_BASE+LPC43_ADC_DR2_OFFSET)
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#define LPC43_ADC0_DR3 (LPC43_ADC0_BASE+LPC43_ADC_DR3_OFFSET)
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#define LPC43_ADC0_DR4 (LPC43_ADC0_BASE+LPC43_ADC_DR4_OFFSET)
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#define LPC43_ADC0_DR5 (LPC43_ADC0_BASE+LPC43_ADC_DR5_OFFSET)
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#define LPC43_ADC0_DR6 (LPC43_ADC0_BASE+LPC43_ADC_DR6_OFFSET)
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#define LPC43_ADC0_DR7 (LPC43_ADC0_BASE+LPC43_ADC_DR7_OFFSET)
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#define LPC43_ADC0_STAT (LPC43_ADC0_BASE+LPC43_ADC_STAT_OFFSET)
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#define LPC43_ADC1_CR (LPC43_ADC1_BASE+LPC43_ADC_CR_OFFSET)
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#define LPC43_ADC1_GDR (LPC43_ADC1_BASE+LPC43_ADC_GDR_OFFSET)
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#define LPC43_ADC1_INTEN (LPC43_ADC1_BASE+LPC43_ADC_INTEN_OFFSET)
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#define LPC43_ADC1_DR(n) (LPC43_ADC1_BASE+LPC43_ADC_DR_OFFSET(n))
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#define LPC43_ADC1_DR0 (LPC43_ADC1_BASE+LPC43_ADC_DR0_OFFSET)
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#define LPC43_ADC1_DR1 (LPC43_ADC1_BASE+LPC43_ADC_DR1_OFFSET)
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#define LPC43_ADC1_DR2 (LPC43_ADC1_BASE+LPC43_ADC_DR2_OFFSET)
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#define LPC43_ADC1_DR3 (LPC43_ADC1_BASE+LPC43_ADC_DR3_OFFSET)
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#define LPC43_ADC1_DR4 (LPC43_ADC1_BASE+LPC43_ADC_DR4_OFFSET)
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#define LPC43_ADC1_DR5 (LPC43_ADC1_BASE+LPC43_ADC_DR5_OFFSET)
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#define LPC43_ADC1_DR6 (LPC43_ADC1_BASE+LPC43_ADC_DR6_OFFSET)
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#define LPC43_ADC1_DR7 (LPC43_ADC1_BASE+LPC43_ADC_DR7_OFFSET)
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#define LPC43_ADC1_STAT (LPC43_ADC1_BASE+LPC43_ADC_STAT_OFFSET)
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/* Register bit definitions *********************************************************/
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/* A/D Control Register */
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#define ADC_CR_SEL_SHIFT (0) /* Bits 0-7: Selects pins to be sampled */
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#define ADC_CR_SEL_MASK (0xff << ADC_CR_SEL_MASK)
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#define ADC_CR_CLKDIV_SHIFT (8) /* Bits 8-15: APB clock (PCLK_ADC0) divisor */
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#define ADC_CR_CLKDIV_MASK (0xff << ADC_CR_CLKDIV_SHIFT)
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#define ADC_CR_BURST (1 << 16) /* Bit 16: A/D Repeated conversions */
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#define ADC_CR_CLKS_SHIFT (17) /* Bits 17-19: Number of clocks in conversion */
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#define ADC_CR_CLKS_MASK (7 << ADC_CR_CLKS_SHIFT)
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# define ADC_CR_CLKS_11 (0 << ADC_CR_CLKS_SHIFT) /* 11 clocks / 10 bits */
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# define ADC_CR_CLKS_10 (1 << ADC_CR_CLKS_SHIFT) /* 10 clocks / 9 bits */
|
||||
# define ADC_CR_CLKS_9 (2 << ADC_CR_CLKS_SHIFT) /* 9 clocks / 8 bits */
|
||||
# define ADC_CR_CLKS_8 (3 << ADC_CR_CLKS_SHIFT) /* 8 clocks / 7 bits */
|
||||
# define ADC_CR_CLKS_7 (4 << ADC_CR_CLKS_SHIFT) /* 7 clocks / 6 bits */
|
||||
# define ADC_CR_CLKS_6 (5 << ADC_CR_CLKS_SHIFT) /* 6 clocks / 5 bits */
|
||||
# define ADC_CR_CLKS_5 (6 << ADC_CR_CLKS_SHIFT) /* 5 clocks / 4 bits */
|
||||
# define ADC_CR_CLKS_4 (7 << ADC_CR_CLKS_SHIFT) /* 4 clocks / 3 bits */
|
||||
/* Bit 20: Reserved */
|
||||
#define ADC_CR_PDN (1 << 21) /* Bit 21: A/D converter power-down mode */
|
||||
/* Bits 22-23: Reserved */
|
||||
#define ADC_CR_START_SHIFT (24) /* Bits 24-26: Control A/D conversion start */
|
||||
#define ADC_CR_START_MASK (7 << ADC_CR_START_SHIFT)
|
||||
# define ADC_CR_START_NOSTART (0 << ADC_CR_START_SHIFT) /* No start */
|
||||
# define ADC_CR_START_NOW (1 << ADC_CR_START_SHIFT) /* Start now */
|
||||
# define ADC_CR_START_CTOUT15 (2 << ADC_CR_START_SHIFT) /* Start when edge on CTOUT_15 */
|
||||
# define ADC_CR_START_CTOUT8 (3 << ADC_CR_START_SHIFT) /* Start when edge on CTOUT_8 */
|
||||
# define ADC_CR_START_ADCTRIG0 (4 << ADC_CR_START_SHIFT) /* Start when edge on ADCTRIG0 */
|
||||
# define ADC_CR_START_ADCTRIG1 (5 << ADC_CR_START_SHIFT) /* Start when edge on ADCTRIG1 */
|
||||
# define ADC_CR_START_MCPWM (6 << ADC_CR_START_SHIFT) /* Start when edge on MCPWM */
|
||||
#define ADC_CR_EDGE (1 << 27) /* Bit 27: Start on falling edge */
|
||||
/* Bits 28-31: Reserved */
|
||||
/* A/D Global Data Register */
|
||||
/* Bits 0-3: Reserved */
|
||||
#define ADC_GDR_VVREF_SHIFT (6) /* Bits 6-15: Result of conversion (DONE==1) */
|
||||
#define ADC_GDR_VVREF_MASK (0x03ff << ADC_GDR_VVREF_SHIFT)
|
||||
/* Bits 16-23: Reserved */
|
||||
#define ADC_GDR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */
|
||||
#define ADC_GDR_CHAN_MASK (3 << ADC_GDR_CHN_SHIFT)
|
||||
/* Bits 27-29: Reserved */
|
||||
#define ADC_GDR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/
|
||||
#define ADC_GDR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/
|
||||
|
||||
/* A/D Interrupt Enable Register */
|
||||
|
||||
#define ADC_INTEN_CHAN(n) (1 << (n))
|
||||
#define ADC_INTEN_CHAN0 (1 << 0) /* Bit 0: Enable ADC chan 0 complete intterrupt */
|
||||
#define ADC_INTEN_CHAN1 (1 << 1) /* Bit 1: Enable ADC chan 1 complete interrupt */
|
||||
#define ADC_INTEN_CHAN2 (1 << 2) /* Bit 2: Enable ADC chan 2 complete interrupt */
|
||||
#define ADC_INTEN_CHAN3 (1 << 3) /* Bit 3: Enable ADC chan 3 complete interrupt */
|
||||
#define ADC_INTEN_CHAN4 (1 << 4) /* Bit 4: Enable ADC chan 4 complete interrupt */
|
||||
#define ADC_INTEN_CHAN5 (1 << 5) /* Bit 5: Enable ADC chan 5 complete interrupt */
|
||||
#define ADC_INTEN_CHAN6 (1 << 6) /* Bit 6: Enable ADC chan 6 complete interrupt */
|
||||
#define ADC_INTEN_CHAN7 (1 << 7) /* Bit 7: Enable ADC chan 7 complete interrupt */
|
||||
#define ADC_INTEN_GLOBAL (1 << 8) /* Bit 8: Only the global DONE generates interrupt */
|
||||
/* Bits 9-31: Reserved */
|
||||
/* Channel 0-7 A/D Data Register */
|
||||
/* Bits 0-3: Reserved */
|
||||
#define ADC_DR_VVREF_SHIFT (6) /* Bits 6-15: Result of conversion (DONE==1) */
|
||||
#define ADC_DR_VVREF_MASK (0x03ff << ADC_DR_VVREF_SHIFT)
|
||||
/* Bits 16-29: Reserved */
|
||||
#define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/
|
||||
#define ADC_DR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/
|
||||
|
||||
/* A/D Status Register */
|
||||
|
||||
#define ADC_STAT_DONE(n) (1 << (n))
|
||||
#define ADC_STAT_DONE0 (1 << 0) /* Bit 0: A/D chan 0 DONE */
|
||||
#define ADC_STAT_DONE1 (1 << 1) /* Bit 1: A/D chan 1 DONE */
|
||||
#define ADC_STAT_DONE2 (1 << 2) /* Bit 2: A/D chan 2 DONE */
|
||||
#define ADC_STAT_DONE3 (1 << 3) /* Bit 3: A/D chan 3 DONE */
|
||||
#define ADC_STAT_DONE4 (1 << 4) /* Bit 4: A/D chan 4 DONE */
|
||||
#define ADC_STAT_DONE5 (1 << 5) /* Bit 5: A/D chan 5 DONE */
|
||||
#define ADC_STAT_DONE6 (1 << 6) /* Bit 6: A/D chan 6 DONE */
|
||||
#define ADC_STAT_DONE7 (1 << 7) /* Bit 7: A/D chan 7 DONE */
|
||||
#define ADC_STAT_OVERRUN(n) ((1 << (n)) + 8)
|
||||
#define ADC_STAT_OVERRUN0 (1 << 8) /* Bit 8: A/D chan 0 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN1 (1 << 9) /* Bit 9: A/D chan 1 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN2 (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN3 (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN4 (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN5 (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN6 (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN7 (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */
|
||||
#define ADC_STAT_INT (1 << 16) /* Bit 15: A/D interrupt */
|
||||
/* Bits 17-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H */
|
||||
|
|
|
|||
|
|
@ -1,205 +1,205 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_i2c.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */
|
||||
#define LPC43_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */
|
||||
#define LPC43_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */
|
||||
#define LPC43_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */
|
||||
#define LPC43_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */
|
||||
#define LPC43_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */
|
||||
#define LPC43_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */
|
||||
#define LPC43_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */
|
||||
#define LPC43_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */
|
||||
#define LPC43_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */
|
||||
#define LPC43_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */
|
||||
#define LPC43_I2C_BUFR_OFFSET 0x002c /* Data buffer register */
|
||||
#define LPC43_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */
|
||||
#define LPC43_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */
|
||||
#define LPC43_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */
|
||||
#define LPC43_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_I2C0_CONSET (LPC43_I2C0_BASE+LPC43_I2C_CONSET_OFFSET)
|
||||
#define LPC43_I2C0_STAT (LPC43_I2C0_BASE+LPC43_I2C_STAT_OFFSET)
|
||||
#define LPC43_I2C0_DAT (LPC43_I2C0_BASE+LPC43_I2C_DAT_OFFSET)
|
||||
#define LPC43_I2C0_ADR0 (LPC43_I2C0_BASE+LPC43_I2C_ADR0_OFFSET)
|
||||
#define LPC43_I2C0_SCLH (LPC43_I2C0_BASE+LPC43_I2C_SCLH_OFFSET)
|
||||
#define LPC43_I2C0_SCLL (LPC43_I2C0_BASE+LPC43_I2C_SCLL_OFFSET)
|
||||
#define LPC43_I2C0_CONCLR (LPC43_I2C0_BASE+LPC43_I2C_CONCLR_OFFSET)
|
||||
#define LPC43_I2C0_MMCTRL (LPC43_I2C0_BASE+LPC43_I2C_MMCTRL_OFFSET)
|
||||
#define LPC43_I2C0_ADR1 (LPC43_I2C0_BASE+LPC43_I2C_ADR1_OFFSET)
|
||||
#define LPC43_I2C0_ADR2 (LPC43_I2C0_BASE+LPC43_I2C_ADR2_OFFSET)
|
||||
#define LPC43_I2C0_ADR3 (LPC43_I2C0_BASE+LPC43_I2C_ADR3_OFFSET)
|
||||
#define LPC43_I2C0_BUFR (LPC43_I2C0_BASE+LPC43_I2C_BUFR_OFFSET)
|
||||
#define LPC43_I2C0_MASK0 (LPC43_I2C0_BASE+LPC43_I2C_MASK0_OFFSET)
|
||||
#define LPC43_I2C0_MASK1 (LPC43_I2C0_BASE+LPC43_I2C_MASK1_OFFSET)
|
||||
#define LPC43_I2C0_MASK2 (LPC43_I2C0_BASE+LPC43_I2C_MASK2_OFFSET)
|
||||
#define LPC43_I2C0_MASK3 (LPC43_I2C0_BASE+LPC43_I2C_MASK3_OFFSET)
|
||||
|
||||
#define LPC43_I2C1_CONSET (LPC43_I2C1_BASE+LPC43_I2C_CONSET_OFFSET)
|
||||
#define LPC43_I2C1_STAT (LPC43_I2C1_BASE+LPC43_I2C_STAT_OFFSET)
|
||||
#define LPC43_I2C1_DAT (LPC43_I2C1_BASE+LPC43_I2C_DAT_OFFSET)
|
||||
#define LPC43_I2C1_ADR0 (LPC43_I2C1_BASE+LPC43_I2C_ADR0_OFFSET)
|
||||
#define LPC43_I2C1_SCLH (LPC43_I2C1_BASE+LPC43_I2C_SCLH_OFFSET)
|
||||
#define LPC43_I2C1_SCLL (LPC43_I2C1_BASE+LPC43_I2C_SCLL_OFFSET)
|
||||
#define LPC43_I2C1_CONCLR (LPC43_I2C1_BASE+LPC43_I2C_CONCLR_OFFSET)
|
||||
#define LPC43_I2C1_MMCTRL (LPC43_I2C1_BASE+LPC43_I2C_MMCTRL_OFFSET)
|
||||
#define LPC43_I2C1_ADR1 (LPC43_I2C1_BASE+LPC43_I2C_ADR1_OFFSET)
|
||||
#define LPC43_I2C1_ADR2 (LPC43_I2C1_BASE+LPC43_I2C_ADR2_OFFSET)
|
||||
#define LPC43_I2C1_ADR3 (LPC43_I2C1_BASE+LPC43_I2C_ADR3_OFFSET)
|
||||
#define LPC43_I2C1_BUFR (LPC43_I2C1_BASE+LPC43_I2C_BUFR_OFFSET)
|
||||
#define LPC43_I2C1_MASK0 (LPC43_I2C1_BASE+LPC43_I2C_MASK0_OFFSET)
|
||||
#define LPC43_I2C1_MASK1 (LPC43_I2C1_BASE+LPC43_I2C_MASK1_OFFSET)
|
||||
#define LPC43_I2C1_MASK2 (LPC43_I2C1_BASE+LPC43_I2C_MASK2_OFFSET)
|
||||
#define LPC43_I2C1_MASK3 (LPC43_I2C1_BASE+LPC43_I2C_MASK3_OFFSET)
|
||||
|
||||
#define LPC43_I2C2_CONSET (LPC43_I2C2_BASE+LPC43_I2C_CONSET_OFFSET)
|
||||
#define LPC43_I2C2_STAT (LPC43_I2C2_BASE+LPC43_I2C_STAT_OFFSET)
|
||||
#define LPC43_I2C2_DAT (LPC43_I2C2_BASE+LPC43_I2C_DAT_OFFSET)
|
||||
#define LPC43_I2C2_ADR0 (LPC43_I2C2_BASE+LPC43_I2C_ADR0_OFFSET)
|
||||
#define LPC43_I2C2_SCLH (LPC43_I2C2_BASE+LPC43_I2C_SCLH_OFFSET)
|
||||
#define LPC43_I2C2_SCLL (LPC43_I2C2_BASE+LPC43_I2C_SCLL_OFFSET)
|
||||
#define LPC43_I2C2_CONCLR (LPC43_I2C2_BASE+LPC43_I2C_CONCLR_OFFSET)
|
||||
#define LPC43_I2C2_MMCTRL (LPC43_I2C2_BASE+LPC43_I2C_MMCTRL_OFFSET)
|
||||
#define LPC43_I2C2_ADR1 (LPC43_I2C2_BASE+LPC43_I2C_ADR1_OFFSET)
|
||||
#define LPC43_I2C2_ADR2 (LPC43_I2C2_BASE+LPC43_I2C_ADR2_OFFSET)
|
||||
#define LPC43_I2C2_ADR3 (LPC43_I2C2_BASE+LPC43_I2C_ADR3_OFFSET)
|
||||
#define LPC43_I2C2_BUFR (LPC43_I2C2_BASE+LPC43_I2C_BUFR_OFFSET)
|
||||
#define LPC43_I2C2_MASK0 (LPC43_I2C2_BASE+LPC43_I2C_MASK0_OFFSET)
|
||||
#define LPC43_I2C2_MASK1 (LPC43_I2C2_BASE+LPC43_I2C_MASK1_OFFSET)
|
||||
#define LPC43_I2C2_MASK2 (LPC43_I2C2_BASE+LPC43_I2C_MASK2_OFFSET)
|
||||
#define LPC43_I2C2_MASK3 (LPC43_I2C2_BASE+LPC43_I2C_MASK3_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* I2C Control Set Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */
|
||||
#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */
|
||||
#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */
|
||||
#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */
|
||||
#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* I2C Control Clear Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */
|
||||
#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */
|
||||
/* Bit 4: Reserved */
|
||||
#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */
|
||||
#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* I2C Status Register
|
||||
*
|
||||
* See tables 997-1002 in the "LPC43xx User Manual" (UM10503), Rev. 1.2, 8 June
|
||||
* 2012, NXP for definitions of status codes.
|
||||
*/
|
||||
|
||||
#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status
|
||||
* Bits 0-2 always zero */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Data Register */
|
||||
|
||||
#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Monitor mode control register */
|
||||
|
||||
#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */
|
||||
#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */
|
||||
#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */
|
||||
/* Bits 3-31: Reserved */
|
||||
/* Data buffer register */
|
||||
|
||||
#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Slave address registers:
|
||||
*
|
||||
* I2C Slave Address Register 0
|
||||
* I2C Slave Address Register 1
|
||||
* I2C Slave Address Register 2
|
||||
* I2C Slave Address Register 3
|
||||
*/
|
||||
|
||||
#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */
|
||||
#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */
|
||||
#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Slave address mask registers:
|
||||
*
|
||||
* I2C Slave address mask register 0
|
||||
* I2C Slave address mask register 1
|
||||
* I2C Slave address mask register 2
|
||||
* I2C Slave address mask register 3
|
||||
*/
|
||||
/* Bit 0: Reserved */
|
||||
#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */
|
||||
#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SCH Duty Cycle Register High Half Word */
|
||||
|
||||
#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* SCL Duty Cycle Register Low Half Word */
|
||||
|
||||
#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_i2c.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */
|
||||
#define LPC43_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */
|
||||
#define LPC43_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */
|
||||
#define LPC43_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */
|
||||
#define LPC43_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */
|
||||
#define LPC43_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */
|
||||
#define LPC43_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */
|
||||
#define LPC43_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */
|
||||
#define LPC43_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */
|
||||
#define LPC43_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */
|
||||
#define LPC43_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */
|
||||
#define LPC43_I2C_BUFR_OFFSET 0x002c /* Data buffer register */
|
||||
#define LPC43_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */
|
||||
#define LPC43_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */
|
||||
#define LPC43_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */
|
||||
#define LPC43_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_I2C0_CONSET (LPC43_I2C0_BASE+LPC43_I2C_CONSET_OFFSET)
|
||||
#define LPC43_I2C0_STAT (LPC43_I2C0_BASE+LPC43_I2C_STAT_OFFSET)
|
||||
#define LPC43_I2C0_DAT (LPC43_I2C0_BASE+LPC43_I2C_DAT_OFFSET)
|
||||
#define LPC43_I2C0_ADR0 (LPC43_I2C0_BASE+LPC43_I2C_ADR0_OFFSET)
|
||||
#define LPC43_I2C0_SCLH (LPC43_I2C0_BASE+LPC43_I2C_SCLH_OFFSET)
|
||||
#define LPC43_I2C0_SCLL (LPC43_I2C0_BASE+LPC43_I2C_SCLL_OFFSET)
|
||||
#define LPC43_I2C0_CONCLR (LPC43_I2C0_BASE+LPC43_I2C_CONCLR_OFFSET)
|
||||
#define LPC43_I2C0_MMCTRL (LPC43_I2C0_BASE+LPC43_I2C_MMCTRL_OFFSET)
|
||||
#define LPC43_I2C0_ADR1 (LPC43_I2C0_BASE+LPC43_I2C_ADR1_OFFSET)
|
||||
#define LPC43_I2C0_ADR2 (LPC43_I2C0_BASE+LPC43_I2C_ADR2_OFFSET)
|
||||
#define LPC43_I2C0_ADR3 (LPC43_I2C0_BASE+LPC43_I2C_ADR3_OFFSET)
|
||||
#define LPC43_I2C0_BUFR (LPC43_I2C0_BASE+LPC43_I2C_BUFR_OFFSET)
|
||||
#define LPC43_I2C0_MASK0 (LPC43_I2C0_BASE+LPC43_I2C_MASK0_OFFSET)
|
||||
#define LPC43_I2C0_MASK1 (LPC43_I2C0_BASE+LPC43_I2C_MASK1_OFFSET)
|
||||
#define LPC43_I2C0_MASK2 (LPC43_I2C0_BASE+LPC43_I2C_MASK2_OFFSET)
|
||||
#define LPC43_I2C0_MASK3 (LPC43_I2C0_BASE+LPC43_I2C_MASK3_OFFSET)
|
||||
|
||||
#define LPC43_I2C1_CONSET (LPC43_I2C1_BASE+LPC43_I2C_CONSET_OFFSET)
|
||||
#define LPC43_I2C1_STAT (LPC43_I2C1_BASE+LPC43_I2C_STAT_OFFSET)
|
||||
#define LPC43_I2C1_DAT (LPC43_I2C1_BASE+LPC43_I2C_DAT_OFFSET)
|
||||
#define LPC43_I2C1_ADR0 (LPC43_I2C1_BASE+LPC43_I2C_ADR0_OFFSET)
|
||||
#define LPC43_I2C1_SCLH (LPC43_I2C1_BASE+LPC43_I2C_SCLH_OFFSET)
|
||||
#define LPC43_I2C1_SCLL (LPC43_I2C1_BASE+LPC43_I2C_SCLL_OFFSET)
|
||||
#define LPC43_I2C1_CONCLR (LPC43_I2C1_BASE+LPC43_I2C_CONCLR_OFFSET)
|
||||
#define LPC43_I2C1_MMCTRL (LPC43_I2C1_BASE+LPC43_I2C_MMCTRL_OFFSET)
|
||||
#define LPC43_I2C1_ADR1 (LPC43_I2C1_BASE+LPC43_I2C_ADR1_OFFSET)
|
||||
#define LPC43_I2C1_ADR2 (LPC43_I2C1_BASE+LPC43_I2C_ADR2_OFFSET)
|
||||
#define LPC43_I2C1_ADR3 (LPC43_I2C1_BASE+LPC43_I2C_ADR3_OFFSET)
|
||||
#define LPC43_I2C1_BUFR (LPC43_I2C1_BASE+LPC43_I2C_BUFR_OFFSET)
|
||||
#define LPC43_I2C1_MASK0 (LPC43_I2C1_BASE+LPC43_I2C_MASK0_OFFSET)
|
||||
#define LPC43_I2C1_MASK1 (LPC43_I2C1_BASE+LPC43_I2C_MASK1_OFFSET)
|
||||
#define LPC43_I2C1_MASK2 (LPC43_I2C1_BASE+LPC43_I2C_MASK2_OFFSET)
|
||||
#define LPC43_I2C1_MASK3 (LPC43_I2C1_BASE+LPC43_I2C_MASK3_OFFSET)
|
||||
|
||||
#define LPC43_I2C2_CONSET (LPC43_I2C2_BASE+LPC43_I2C_CONSET_OFFSET)
|
||||
#define LPC43_I2C2_STAT (LPC43_I2C2_BASE+LPC43_I2C_STAT_OFFSET)
|
||||
#define LPC43_I2C2_DAT (LPC43_I2C2_BASE+LPC43_I2C_DAT_OFFSET)
|
||||
#define LPC43_I2C2_ADR0 (LPC43_I2C2_BASE+LPC43_I2C_ADR0_OFFSET)
|
||||
#define LPC43_I2C2_SCLH (LPC43_I2C2_BASE+LPC43_I2C_SCLH_OFFSET)
|
||||
#define LPC43_I2C2_SCLL (LPC43_I2C2_BASE+LPC43_I2C_SCLL_OFFSET)
|
||||
#define LPC43_I2C2_CONCLR (LPC43_I2C2_BASE+LPC43_I2C_CONCLR_OFFSET)
|
||||
#define LPC43_I2C2_MMCTRL (LPC43_I2C2_BASE+LPC43_I2C_MMCTRL_OFFSET)
|
||||
#define LPC43_I2C2_ADR1 (LPC43_I2C2_BASE+LPC43_I2C_ADR1_OFFSET)
|
||||
#define LPC43_I2C2_ADR2 (LPC43_I2C2_BASE+LPC43_I2C_ADR2_OFFSET)
|
||||
#define LPC43_I2C2_ADR3 (LPC43_I2C2_BASE+LPC43_I2C_ADR3_OFFSET)
|
||||
#define LPC43_I2C2_BUFR (LPC43_I2C2_BASE+LPC43_I2C_BUFR_OFFSET)
|
||||
#define LPC43_I2C2_MASK0 (LPC43_I2C2_BASE+LPC43_I2C_MASK0_OFFSET)
|
||||
#define LPC43_I2C2_MASK1 (LPC43_I2C2_BASE+LPC43_I2C_MASK1_OFFSET)
|
||||
#define LPC43_I2C2_MASK2 (LPC43_I2C2_BASE+LPC43_I2C_MASK2_OFFSET)
|
||||
#define LPC43_I2C2_MASK3 (LPC43_I2C2_BASE+LPC43_I2C_MASK3_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* I2C Control Set Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */
|
||||
#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */
|
||||
#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */
|
||||
#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */
|
||||
#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* I2C Control Clear Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */
|
||||
#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */
|
||||
/* Bit 4: Reserved */
|
||||
#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */
|
||||
#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* I2C Status Register
|
||||
*
|
||||
* See tables 997-1002 in the "LPC43xx User Manual" (UM10503), Rev. 1.2, 8 June
|
||||
* 2012, NXP for definitions of status codes.
|
||||
*/
|
||||
|
||||
#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status
|
||||
* Bits 0-2 always zero */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Data Register */
|
||||
|
||||
#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Monitor mode control register */
|
||||
|
||||
#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */
|
||||
#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */
|
||||
#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */
|
||||
/* Bits 3-31: Reserved */
|
||||
/* Data buffer register */
|
||||
|
||||
#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Slave address registers:
|
||||
*
|
||||
* I2C Slave Address Register 0
|
||||
* I2C Slave Address Register 1
|
||||
* I2C Slave Address Register 2
|
||||
* I2C Slave Address Register 3
|
||||
*/
|
||||
|
||||
#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */
|
||||
#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */
|
||||
#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Slave address mask registers:
|
||||
*
|
||||
* I2C Slave address mask register 0
|
||||
* I2C Slave address mask register 1
|
||||
* I2C Slave address mask register 2
|
||||
* I2C Slave address mask register 3
|
||||
*/
|
||||
/* Bit 0: Reserved */
|
||||
#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */
|
||||
#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SCH Duty Cycle Register High Half Word */
|
||||
|
||||
#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* SCL Duty Cycle Register Low Half Word */
|
||||
|
||||
#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H */
|
||||
|
|
|
|||
|
|
@ -1,202 +1,202 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_i2s
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_I2S_DAO_OFFSET 0x0000 /* Digital Audio Output Register */
|
||||
#define LPC43_I2S_DAI_OFFSET 0x0004 /* Digital Audio Input Register */
|
||||
#define LPC43_I2S_TXFIFO_OFFSET 0x0008 /* Transmit FIFO */
|
||||
#define LPC43_I2S_RXFIFO_OFFSET 0x000c /* Receive FIFO */
|
||||
#define LPC43_I2S_STATE_OFFSET 0x0010 /* Status Feedback Register */
|
||||
#define LPC43_I2S_DMA1_OFFSET 0x0014 /* DMA Configuration Register 1 */
|
||||
#define LPC43_I2S_DMA2_OFFSET 0x0018 /* DMA Configuration Register 2 */
|
||||
#define LPC43_I2S_IRQ_OFFSET 0x001c /* Interrupt Request Control Register */
|
||||
#define LPC43_I2S_TXRATE_OFFSET 0x0020 /* Transmit MCLK divider */
|
||||
#define LPC43_I2S_RXRATE_OFFSET 0x0024 /* Receive MCLK divider */
|
||||
#define LPC43_I2S_TXBITRATE_OFFSET 0x0028 /* Transmit bit rate divider */
|
||||
#define LPC43_I2S_RXBITRATE_OFFSET 0x002c /* Receive bit rate divider */
|
||||
#define LPC43_I2S_TXMODE_OFFSET 0x0030 /* Transmit mode control */
|
||||
#define LPC43_I2S_RXMODE_OFFSET 0x0034 /* Receive mode control */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_I2S0_DAO (LPC43_I2S0_BASE+LPC43_I2S_DAO_OFFSET)
|
||||
#define LPC43_I2S0_DAI (LPC43_I2S0_BASE+LPC43_I2S_DAI_OFFSET)
|
||||
#define LPC43_I2S0_TXFIFO (LPC43_I2S0_BASE+LPC43_I2S_TXFIFO_OFFSET)
|
||||
#define LPC43_I2S0_RXFIFO (LPC43_I2S0_BASE+LPC43_I2S_RXFIFO_OFFSET)
|
||||
#define LPC43_I2S0_STATE (LPC43_I2S0_BASE+LPC43_I2S_STATE_OFFSET)
|
||||
#define LPC43_I2S0_DMA1 (LPC43_I2S0_BASE+LPC43_I2S_DMA1_OFFSET)
|
||||
#define LPC43_I2S0_DMA2 (LPC43_I2S0_BASE+LPC43_I2S_DMA2_OFFSET)
|
||||
#define LPC43_I2S0_IRQ (LPC43_I2S0_BASE+LPC43_I2S_IRQ_OFFSET)
|
||||
#define LPC43_I2S0_TXRATE (LPC43_I2S0_BASE+LPC43_I2S_TXRATE_OFFSET)
|
||||
#define LPC43_I2S0_RXRATE (LPC43_I2S0_BASE+LPC43_I2S_RXRATE_OFFSET)
|
||||
#define LPC43_I2S0_TXBITRATE (LPC43_I2S0_BASE+LPC43_I2S_TXBITRATE_OFFSET)
|
||||
#define LPC43_I2S0_RXBITRATE (LPC43_I2S0_BASE+LPC43_I2S_RXBITRATE_OFFSET)
|
||||
#define LPC43_I2S0_TXMODE (LPC43_I2S0_BASE+LPC43_I2S_TXMODE_OFFSET)
|
||||
#define LPC43_I2S0_RXMODE (LPC43_I2S0_BASE+LPC43_I2S_RXMODE_OFFSET)
|
||||
|
||||
#define LPC43_I2S1_DAO (LPC43_I2S1_BASE+LPC43_I2S_DAO_OFFSET)
|
||||
#define LPC43_I2S1_DAI (LPC43_I2S1_BASE+LPC43_I2S_DAI_OFFSET)
|
||||
#define LPC43_I2S1_TXFIFO (LPC43_I2S1_BASE+LPC43_I2S_TXFIFO_OFFSET)
|
||||
#define LPC43_I2S1_RXFIFO (LPC43_I2S1_BASE+LPC43_I2S_RXFIFO_OFFSET)
|
||||
#define LPC43_I2S1_STATE (LPC43_I2S1_BASE+LPC43_I2S_STATE_OFFSET)
|
||||
#define LPC43_I2S1_DMA1 (LPC43_I2S1_BASE+LPC43_I2S_DMA1_OFFSET)
|
||||
#define LPC43_I2S1_DMA2 (LPC43_I2S1_BASE+LPC43_I2S_DMA2_OFFSET)
|
||||
#define LPC43_I2S1_IRQ (LPC43_I2S1_BASE+LPC43_I2S_IRQ_OFFSET)
|
||||
#define LPC43_I2S1_TXRATE (LPC43_I2S1_BASE+LPC43_I2S_TXRATE_OFFSET)
|
||||
#define LPC43_I2S1_RXRATE (LPC43_I2S1_BASE+LPC43_I2S_RXRATE_OFFSET)
|
||||
#define LPC43_I2S1_TXBITRATE (LPC43_I2S1_BASE+LPC43_I2S_TXBITRATE_OFFSET)
|
||||
#define LPC43_I2S1_RXBITRATE (LPC43_I2S1_BASE+LPC43_I2S_RXBITRATE_OFFSET)
|
||||
#define LPC43_I2S1_TXMODE (LPC43_I2S1_BASE+LPC43_I2S_TXMODE_OFFSET)
|
||||
#define LPC43_I2S1_RXMODE (LPC43_I2S1_BASE+LPC43_I2S_RXMODE_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Digital Audio Output Register */
|
||||
|
||||
#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
|
||||
#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT)
|
||||
# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT)
|
||||
# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT)
|
||||
# define I2S_DAO_WDWID_32BITS (3 << I2S_DAO_WDWID_SHIFT)
|
||||
#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */
|
||||
#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
|
||||
#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
|
||||
#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */
|
||||
#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
|
||||
#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT)
|
||||
#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Digital Audio Input Register */
|
||||
|
||||
#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
|
||||
#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT)
|
||||
# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT)
|
||||
# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT)
|
||||
# define I2S_DAI_WDWID_32BITS (3 << I2S_DAI_WDWID_SHIFT)
|
||||
#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */
|
||||
#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
|
||||
#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
|
||||
#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */
|
||||
#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
|
||||
#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
|
||||
/* Bits 15-31: Reserved */
|
||||
/* Transmit FIFO: 8 × 32-bit transmit FIFO */
|
||||
/* Receive FIFO: 8 × 32-bit receive FIFO */
|
||||
|
||||
/* Status Feedback Register */
|
||||
|
||||
#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */
|
||||
#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */
|
||||
#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */
|
||||
#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */
|
||||
#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
/* DMA Configuration Register 1 and 2 */
|
||||
|
||||
#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */
|
||||
#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */
|
||||
/* Bits 2-7: Reserved */
|
||||
#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */
|
||||
#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */
|
||||
#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
/* Interrupt Request Control Register */
|
||||
|
||||
#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */
|
||||
#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */
|
||||
/* Bits 2-7: Reserved */
|
||||
#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */
|
||||
#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */
|
||||
#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
/* Transmit and Receive MCLK divider */
|
||||
|
||||
#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */
|
||||
#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT)
|
||||
#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */
|
||||
#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Transmit and received bit rate divider */
|
||||
|
||||
#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */
|
||||
#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT)
|
||||
/* Bits 6-31: Reserved */
|
||||
/* Transmit and Receive mode control */
|
||||
|
||||
#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */
|
||||
#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT)
|
||||
# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */
|
||||
# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */
|
||||
# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */
|
||||
#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */
|
||||
#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_i2s
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_I2S_DAO_OFFSET 0x0000 /* Digital Audio Output Register */
|
||||
#define LPC43_I2S_DAI_OFFSET 0x0004 /* Digital Audio Input Register */
|
||||
#define LPC43_I2S_TXFIFO_OFFSET 0x0008 /* Transmit FIFO */
|
||||
#define LPC43_I2S_RXFIFO_OFFSET 0x000c /* Receive FIFO */
|
||||
#define LPC43_I2S_STATE_OFFSET 0x0010 /* Status Feedback Register */
|
||||
#define LPC43_I2S_DMA1_OFFSET 0x0014 /* DMA Configuration Register 1 */
|
||||
#define LPC43_I2S_DMA2_OFFSET 0x0018 /* DMA Configuration Register 2 */
|
||||
#define LPC43_I2S_IRQ_OFFSET 0x001c /* Interrupt Request Control Register */
|
||||
#define LPC43_I2S_TXRATE_OFFSET 0x0020 /* Transmit MCLK divider */
|
||||
#define LPC43_I2S_RXRATE_OFFSET 0x0024 /* Receive MCLK divider */
|
||||
#define LPC43_I2S_TXBITRATE_OFFSET 0x0028 /* Transmit bit rate divider */
|
||||
#define LPC43_I2S_RXBITRATE_OFFSET 0x002c /* Receive bit rate divider */
|
||||
#define LPC43_I2S_TXMODE_OFFSET 0x0030 /* Transmit mode control */
|
||||
#define LPC43_I2S_RXMODE_OFFSET 0x0034 /* Receive mode control */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_I2S0_DAO (LPC43_I2S0_BASE+LPC43_I2S_DAO_OFFSET)
|
||||
#define LPC43_I2S0_DAI (LPC43_I2S0_BASE+LPC43_I2S_DAI_OFFSET)
|
||||
#define LPC43_I2S0_TXFIFO (LPC43_I2S0_BASE+LPC43_I2S_TXFIFO_OFFSET)
|
||||
#define LPC43_I2S0_RXFIFO (LPC43_I2S0_BASE+LPC43_I2S_RXFIFO_OFFSET)
|
||||
#define LPC43_I2S0_STATE (LPC43_I2S0_BASE+LPC43_I2S_STATE_OFFSET)
|
||||
#define LPC43_I2S0_DMA1 (LPC43_I2S0_BASE+LPC43_I2S_DMA1_OFFSET)
|
||||
#define LPC43_I2S0_DMA2 (LPC43_I2S0_BASE+LPC43_I2S_DMA2_OFFSET)
|
||||
#define LPC43_I2S0_IRQ (LPC43_I2S0_BASE+LPC43_I2S_IRQ_OFFSET)
|
||||
#define LPC43_I2S0_TXRATE (LPC43_I2S0_BASE+LPC43_I2S_TXRATE_OFFSET)
|
||||
#define LPC43_I2S0_RXRATE (LPC43_I2S0_BASE+LPC43_I2S_RXRATE_OFFSET)
|
||||
#define LPC43_I2S0_TXBITRATE (LPC43_I2S0_BASE+LPC43_I2S_TXBITRATE_OFFSET)
|
||||
#define LPC43_I2S0_RXBITRATE (LPC43_I2S0_BASE+LPC43_I2S_RXBITRATE_OFFSET)
|
||||
#define LPC43_I2S0_TXMODE (LPC43_I2S0_BASE+LPC43_I2S_TXMODE_OFFSET)
|
||||
#define LPC43_I2S0_RXMODE (LPC43_I2S0_BASE+LPC43_I2S_RXMODE_OFFSET)
|
||||
|
||||
#define LPC43_I2S1_DAO (LPC43_I2S1_BASE+LPC43_I2S_DAO_OFFSET)
|
||||
#define LPC43_I2S1_DAI (LPC43_I2S1_BASE+LPC43_I2S_DAI_OFFSET)
|
||||
#define LPC43_I2S1_TXFIFO (LPC43_I2S1_BASE+LPC43_I2S_TXFIFO_OFFSET)
|
||||
#define LPC43_I2S1_RXFIFO (LPC43_I2S1_BASE+LPC43_I2S_RXFIFO_OFFSET)
|
||||
#define LPC43_I2S1_STATE (LPC43_I2S1_BASE+LPC43_I2S_STATE_OFFSET)
|
||||
#define LPC43_I2S1_DMA1 (LPC43_I2S1_BASE+LPC43_I2S_DMA1_OFFSET)
|
||||
#define LPC43_I2S1_DMA2 (LPC43_I2S1_BASE+LPC43_I2S_DMA2_OFFSET)
|
||||
#define LPC43_I2S1_IRQ (LPC43_I2S1_BASE+LPC43_I2S_IRQ_OFFSET)
|
||||
#define LPC43_I2S1_TXRATE (LPC43_I2S1_BASE+LPC43_I2S_TXRATE_OFFSET)
|
||||
#define LPC43_I2S1_RXRATE (LPC43_I2S1_BASE+LPC43_I2S_RXRATE_OFFSET)
|
||||
#define LPC43_I2S1_TXBITRATE (LPC43_I2S1_BASE+LPC43_I2S_TXBITRATE_OFFSET)
|
||||
#define LPC43_I2S1_RXBITRATE (LPC43_I2S1_BASE+LPC43_I2S_RXBITRATE_OFFSET)
|
||||
#define LPC43_I2S1_TXMODE (LPC43_I2S1_BASE+LPC43_I2S_TXMODE_OFFSET)
|
||||
#define LPC43_I2S1_RXMODE (LPC43_I2S1_BASE+LPC43_I2S_RXMODE_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Digital Audio Output Register */
|
||||
|
||||
#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
|
||||
#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT)
|
||||
# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT)
|
||||
# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT)
|
||||
# define I2S_DAO_WDWID_32BITS (3 << I2S_DAO_WDWID_SHIFT)
|
||||
#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */
|
||||
#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
|
||||
#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
|
||||
#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */
|
||||
#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
|
||||
#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT)
|
||||
#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Digital Audio Input Register */
|
||||
|
||||
#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
|
||||
#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT)
|
||||
# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT)
|
||||
# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT)
|
||||
# define I2S_DAI_WDWID_32BITS (3 << I2S_DAI_WDWID_SHIFT)
|
||||
#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */
|
||||
#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
|
||||
#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
|
||||
#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */
|
||||
#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
|
||||
#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
|
||||
/* Bits 15-31: Reserved */
|
||||
/* Transmit FIFO: 8 × 32-bit transmit FIFO */
|
||||
/* Receive FIFO: 8 × 32-bit receive FIFO */
|
||||
|
||||
/* Status Feedback Register */
|
||||
|
||||
#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */
|
||||
#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */
|
||||
#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */
|
||||
#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */
|
||||
#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
/* DMA Configuration Register 1 and 2 */
|
||||
|
||||
#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */
|
||||
#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */
|
||||
/* Bits 2-7: Reserved */
|
||||
#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */
|
||||
#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */
|
||||
#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
/* Interrupt Request Control Register */
|
||||
|
||||
#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */
|
||||
#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */
|
||||
/* Bits 2-7: Reserved */
|
||||
#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */
|
||||
#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */
|
||||
#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
/* Transmit and Receive MCLK divider */
|
||||
|
||||
#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */
|
||||
#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT)
|
||||
#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */
|
||||
#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Transmit and received bit rate divider */
|
||||
|
||||
#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */
|
||||
#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT)
|
||||
/* Bits 6-31: Reserved */
|
||||
/* Transmit and Receive mode control */
|
||||
|
||||
#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */
|
||||
#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT)
|
||||
# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */
|
||||
# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */
|
||||
# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */
|
||||
#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */
|
||||
#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H */
|
||||
|
|
|
|||
|
|
@ -1,274 +1,274 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_mcpwm.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */
|
||||
#define LPC43_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */
|
||||
#define LPC43_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */
|
||||
#define LPC43_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */
|
||||
#define LPC43_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */
|
||||
#define LPC43_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */
|
||||
#define LPC43_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */
|
||||
#define LPC43_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */
|
||||
#define LPC43_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */
|
||||
#define LPC43_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */
|
||||
#define LPC43_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */
|
||||
#define LPC43_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */
|
||||
#define LPC43_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */
|
||||
#define LPC43_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */
|
||||
#define LPC43_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */
|
||||
#define LPC43_MCPWM_DT_OFFSET 0x003c /* Dead time register */
|
||||
#define LPC43_MCPWM_MCCP_OFFSET 0x0040 /* Communication Pattern register */
|
||||
#define LPC43_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */
|
||||
#define LPC43_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */
|
||||
#define LPC43_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */
|
||||
#define LPC43_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */
|
||||
#define LPC43_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */
|
||||
#define LPC43_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */
|
||||
#define LPC43_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */
|
||||
#define LPC43_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */
|
||||
#define LPC43_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */
|
||||
#define LPC43_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */
|
||||
#define LPC43_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */
|
||||
#define LPC43_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */
|
||||
#define LPC43_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_MCPWM_CON (LPC43_MCPWM_BASE+LPC43_MCPWM_CON_OFFSET)
|
||||
#define LPC43_MCPWM_CONSET (LPC43_MCPWM_BASE+LPC43_MCPWM_CONSET_OFFSET)
|
||||
#define LPC43_MCPWM_CONCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_CONCLR_OFFSET)
|
||||
#define LPC43_MCPWM_CAPCON (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCON_OFFSET)
|
||||
#define LPC43_MCPWM_CAPCONSET (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCONSET_OFFSET)
|
||||
#define LPC43_MCPWM_CAPCONCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCONCLR_OFFSET)
|
||||
#define LPC43_MCPWM_TC0 (LPC43_MCPWM_BASE+LPC43_MCPWM_TC0_OFFSET)
|
||||
#define LPC43_MCPWM_TC1 (LPC43_MCPWM_BASE+LPC43_MCPWM_TC1_OFFSET)
|
||||
#define LPC43_MCPWM_TC2 (LPC43_MCPWM_BASE+LPC43_MCPWM_TC2_OFFSET)
|
||||
#define LPC43_MCPWM_LIM0 (LPC43_MCPWM_BASE+LPC43_MCPWM_LIM0_OFFSET)
|
||||
#define LPC43_MCPWM_LIM1 (LPC43_MCPWM_BASE+LPC43_MCPWM_LIM1_OFFSET)
|
||||
#define LPC43_MCPWM_LIM2 (LPC43_MCPWM_BASE+LPC43_MCPWM_LIM2_OFFSET)
|
||||
#define LPC43_MCPWM_MAT0 (LPC43_MCPWM_BASE+LPC43_MCPWM_MAT0_OFFSET)
|
||||
#define LPC43_MCPWM_MAT1 (LPC43_MCPWM_BASE+LPC43_MCPWM_MAT1_OFFSET)
|
||||
#define LPC43_MCPWM_MAT2 (LPC43_MCPWM_BASE+LPC43_MCPWM_MAT2_OFFSET)
|
||||
#define LPC43_MCPWM_DT (LPC43_MCPWM_BASE+LPC43_MCPWM_DT_OFFSET)
|
||||
#define LPC43_MCPWM_MCCP (LPC43_MCPWM_BASE+LPC43_MCPWM_MCCP_OFFSET)
|
||||
#define LPC43_MCPWM_CAP0 (LPC43_MCPWM_BASE+LPC43_MCPWM_CAP0_OFFSET)
|
||||
#define LPC43_MCPWM_CAP1 (LPC43_MCPWM_BASE+LPC43_MCPWM_CAP1_OFFSET)
|
||||
#define LPC43_MCPWM_CAP2 (LPC43_MCPWM_BASE+LPC43_MCPWM_CAP2_OFFSET)
|
||||
#define LPC43_MCPWM_INTEN (LPC43_MCPWM_BASE+LPC43_MCPWM_INTEN_OFFSET)
|
||||
#define LPC43_MCPWM_INTENSET (LPC43_MCPWM_BASE+LPC43_MCPWM_INTENSET_OFFSET)
|
||||
#define LPC43_MCPWM_INTENCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_INTENCLR_OFFSET)
|
||||
#define LPC43_MCPWM_CNTCON (LPC43_MCPWM_BASE+LPC43_MCPWM_CNTCON_OFFSET)
|
||||
#define LPC43_MCPWM_CNTCONSET (LPC43_MCPWM_BASE+LPC43_MCPWM_CNTCONSET_OFFSET)
|
||||
#define LPC43_MCPWM_CNTCONCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_CNTCONCLR_OFFSET)
|
||||
#define LPC43_MCPWM_INTF (LPC43_MCPWM_BASE+LPC43_MCPWM_INTF_OFFSET)
|
||||
#define LPC43_MCPWM_INTFSET (LPC43_MCPWM_BASE+LPC43_MCPWM_INTFSET_OFFSET)
|
||||
#define LPC43_MCPWM_INTFCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_INTFCLR_OFFSET)
|
||||
#define LPC43_MCPWM_CAPCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCLR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* There are no bit field definitions for the following registers because they support
|
||||
* 32-bit values:
|
||||
*
|
||||
* - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1),
|
||||
* and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for
|
||||
* channels 0, 1, 2 (no bit field definitions)
|
||||
*
|
||||
* - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit
|
||||
* register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field
|
||||
* definitions)
|
||||
*
|
||||
* - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match
|
||||
* register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field
|
||||
* definitions).
|
||||
*
|
||||
* - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and
|
||||
* Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for
|
||||
* channels 0, 1, 2 (no bit field definitions)
|
||||
*/
|
||||
|
||||
/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control
|
||||
* clear address (CONCLR) common regiser bit definitions.
|
||||
*/
|
||||
|
||||
#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */
|
||||
#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */
|
||||
#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */
|
||||
#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */
|
||||
#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */
|
||||
/* Bits 5-7: Reserved */
|
||||
#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */
|
||||
#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */
|
||||
#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */
|
||||
#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */
|
||||
#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */
|
||||
#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */
|
||||
#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */
|
||||
#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */
|
||||
#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */
|
||||
/* Bits 21-28: Reserved */
|
||||
#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */
|
||||
#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */
|
||||
#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */
|
||||
|
||||
/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET),
|
||||
* and Event Control clear address (CAPCONCLR) common register bit defintions
|
||||
*/
|
||||
|
||||
#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */
|
||||
#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */
|
||||
#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */
|
||||
/* Bits 21-31: Reserved
|
||||
/* Dead time register */
|
||||
|
||||
#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */
|
||||
#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT)
|
||||
#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */
|
||||
#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT)
|
||||
#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */
|
||||
#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT)
|
||||
/* Bits 30-31: reserved */
|
||||
/* Communication Pattern register */
|
||||
|
||||
#define MCPWM_MCCP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */
|
||||
/* Bits 6-31: reserved */
|
||||
|
||||
/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET),
|
||||
* Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF),
|
||||
* Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR)
|
||||
* common bit field definitions
|
||||
*/
|
||||
|
||||
#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */
|
||||
#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */
|
||||
#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */
|
||||
/* Bit 3: Reserved */
|
||||
#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */
|
||||
#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */
|
||||
#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */
|
||||
/* Bit 7: Reserved */
|
||||
#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */
|
||||
#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */
|
||||
#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */
|
||||
/* Bits 11-14: Reserved */
|
||||
#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and
|
||||
* Count Control clear address (CNTCONCLR) common register bit definitions.
|
||||
*/
|
||||
|
||||
#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */
|
||||
/* Bits 18-28: Reserved */
|
||||
#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */
|
||||
#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */
|
||||
#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */
|
||||
|
||||
/* Capture clear address */
|
||||
|
||||
#define MCPWM_CAPCLR_CLR0 (1 << 0) /* Bit 0: Clear CAP0 register */
|
||||
#define MCPWM_CAPCLR_CLR1 (1 << 1) /* Bit 1: Clear CAP1 register */
|
||||
#define MCPWM_CAPCLR_CLR2 (1 << 2) /* Bit 2: Clear CAP2 register */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_mcpwm.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */
|
||||
#define LPC43_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */
|
||||
#define LPC43_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */
|
||||
#define LPC43_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */
|
||||
#define LPC43_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */
|
||||
#define LPC43_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */
|
||||
#define LPC43_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */
|
||||
#define LPC43_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */
|
||||
#define LPC43_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */
|
||||
#define LPC43_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */
|
||||
#define LPC43_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */
|
||||
#define LPC43_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */
|
||||
#define LPC43_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */
|
||||
#define LPC43_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */
|
||||
#define LPC43_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */
|
||||
#define LPC43_MCPWM_DT_OFFSET 0x003c /* Dead time register */
|
||||
#define LPC43_MCPWM_MCCP_OFFSET 0x0040 /* Communication Pattern register */
|
||||
#define LPC43_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */
|
||||
#define LPC43_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */
|
||||
#define LPC43_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */
|
||||
#define LPC43_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */
|
||||
#define LPC43_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */
|
||||
#define LPC43_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */
|
||||
#define LPC43_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */
|
||||
#define LPC43_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */
|
||||
#define LPC43_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */
|
||||
#define LPC43_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */
|
||||
#define LPC43_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */
|
||||
#define LPC43_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */
|
||||
#define LPC43_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_MCPWM_CON (LPC43_MCPWM_BASE+LPC43_MCPWM_CON_OFFSET)
|
||||
#define LPC43_MCPWM_CONSET (LPC43_MCPWM_BASE+LPC43_MCPWM_CONSET_OFFSET)
|
||||
#define LPC43_MCPWM_CONCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_CONCLR_OFFSET)
|
||||
#define LPC43_MCPWM_CAPCON (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCON_OFFSET)
|
||||
#define LPC43_MCPWM_CAPCONSET (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCONSET_OFFSET)
|
||||
#define LPC43_MCPWM_CAPCONCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCONCLR_OFFSET)
|
||||
#define LPC43_MCPWM_TC0 (LPC43_MCPWM_BASE+LPC43_MCPWM_TC0_OFFSET)
|
||||
#define LPC43_MCPWM_TC1 (LPC43_MCPWM_BASE+LPC43_MCPWM_TC1_OFFSET)
|
||||
#define LPC43_MCPWM_TC2 (LPC43_MCPWM_BASE+LPC43_MCPWM_TC2_OFFSET)
|
||||
#define LPC43_MCPWM_LIM0 (LPC43_MCPWM_BASE+LPC43_MCPWM_LIM0_OFFSET)
|
||||
#define LPC43_MCPWM_LIM1 (LPC43_MCPWM_BASE+LPC43_MCPWM_LIM1_OFFSET)
|
||||
#define LPC43_MCPWM_LIM2 (LPC43_MCPWM_BASE+LPC43_MCPWM_LIM2_OFFSET)
|
||||
#define LPC43_MCPWM_MAT0 (LPC43_MCPWM_BASE+LPC43_MCPWM_MAT0_OFFSET)
|
||||
#define LPC43_MCPWM_MAT1 (LPC43_MCPWM_BASE+LPC43_MCPWM_MAT1_OFFSET)
|
||||
#define LPC43_MCPWM_MAT2 (LPC43_MCPWM_BASE+LPC43_MCPWM_MAT2_OFFSET)
|
||||
#define LPC43_MCPWM_DT (LPC43_MCPWM_BASE+LPC43_MCPWM_DT_OFFSET)
|
||||
#define LPC43_MCPWM_MCCP (LPC43_MCPWM_BASE+LPC43_MCPWM_MCCP_OFFSET)
|
||||
#define LPC43_MCPWM_CAP0 (LPC43_MCPWM_BASE+LPC43_MCPWM_CAP0_OFFSET)
|
||||
#define LPC43_MCPWM_CAP1 (LPC43_MCPWM_BASE+LPC43_MCPWM_CAP1_OFFSET)
|
||||
#define LPC43_MCPWM_CAP2 (LPC43_MCPWM_BASE+LPC43_MCPWM_CAP2_OFFSET)
|
||||
#define LPC43_MCPWM_INTEN (LPC43_MCPWM_BASE+LPC43_MCPWM_INTEN_OFFSET)
|
||||
#define LPC43_MCPWM_INTENSET (LPC43_MCPWM_BASE+LPC43_MCPWM_INTENSET_OFFSET)
|
||||
#define LPC43_MCPWM_INTENCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_INTENCLR_OFFSET)
|
||||
#define LPC43_MCPWM_CNTCON (LPC43_MCPWM_BASE+LPC43_MCPWM_CNTCON_OFFSET)
|
||||
#define LPC43_MCPWM_CNTCONSET (LPC43_MCPWM_BASE+LPC43_MCPWM_CNTCONSET_OFFSET)
|
||||
#define LPC43_MCPWM_CNTCONCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_CNTCONCLR_OFFSET)
|
||||
#define LPC43_MCPWM_INTF (LPC43_MCPWM_BASE+LPC43_MCPWM_INTF_OFFSET)
|
||||
#define LPC43_MCPWM_INTFSET (LPC43_MCPWM_BASE+LPC43_MCPWM_INTFSET_OFFSET)
|
||||
#define LPC43_MCPWM_INTFCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_INTFCLR_OFFSET)
|
||||
#define LPC43_MCPWM_CAPCLR (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCLR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* There are no bit field definitions for the following registers because they support
|
||||
* 32-bit values:
|
||||
*
|
||||
* - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1),
|
||||
* and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for
|
||||
* channels 0, 1, 2 (no bit field definitions)
|
||||
*
|
||||
* - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit
|
||||
* register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field
|
||||
* definitions)
|
||||
*
|
||||
* - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match
|
||||
* register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field
|
||||
* definitions).
|
||||
*
|
||||
* - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and
|
||||
* Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for
|
||||
* channels 0, 1, 2 (no bit field definitions)
|
||||
*/
|
||||
|
||||
/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control
|
||||
* clear address (CONCLR) common regiser bit definitions.
|
||||
*/
|
||||
|
||||
#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */
|
||||
#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */
|
||||
#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */
|
||||
#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */
|
||||
#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */
|
||||
/* Bits 5-7: Reserved */
|
||||
#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */
|
||||
#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */
|
||||
#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */
|
||||
#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */
|
||||
#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */
|
||||
#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */
|
||||
#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */
|
||||
#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */
|
||||
#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */
|
||||
/* Bits 21-28: Reserved */
|
||||
#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */
|
||||
#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */
|
||||
#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */
|
||||
|
||||
/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET),
|
||||
* and Event Control clear address (CAPCONCLR) common register bit defintions
|
||||
*/
|
||||
|
||||
#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */
|
||||
#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */
|
||||
#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */
|
||||
#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */
|
||||
#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */
|
||||
#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */
|
||||
/* Bits 21-31: Reserved
|
||||
/* Dead time register */
|
||||
|
||||
#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */
|
||||
#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT)
|
||||
#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */
|
||||
#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT)
|
||||
#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */
|
||||
#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT)
|
||||
/* Bits 30-31: reserved */
|
||||
/* Communication Pattern register */
|
||||
|
||||
#define MCPWM_MCCP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */
|
||||
#define MCPWM_MCCP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */
|
||||
/* Bits 6-31: reserved */
|
||||
|
||||
/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET),
|
||||
* Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF),
|
||||
* Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR)
|
||||
* common bit field definitions
|
||||
*/
|
||||
|
||||
#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */
|
||||
#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */
|
||||
#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */
|
||||
/* Bit 3: Reserved */
|
||||
#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */
|
||||
#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */
|
||||
#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */
|
||||
/* Bit 7: Reserved */
|
||||
#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */
|
||||
#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */
|
||||
#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */
|
||||
/* Bits 11-14: Reserved */
|
||||
#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and
|
||||
* Count Control clear address (CNTCONCLR) common register bit definitions.
|
||||
*/
|
||||
|
||||
#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */
|
||||
#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */
|
||||
#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */
|
||||
#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */
|
||||
/* Bits 18-28: Reserved */
|
||||
#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */
|
||||
#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */
|
||||
#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */
|
||||
|
||||
/* Capture clear address */
|
||||
|
||||
#define MCPWM_CAPCLR_CLR0 (1 << 0) /* Bit 0: Clear CAP0 register */
|
||||
#define MCPWM_CAPCLR_CLR1 (1 << 1) /* Bit 1: Clear CAP1 register */
|
||||
#define MCPWM_CAPCLR_CLR2 (1 << 2) /* Bit 2: Clear CAP2 register */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H */
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@
|
|||
#define LPC43_SCT_BASE (LPC43_AHBPERIPH_BASE + 0x00000000)
|
||||
#define LPC43_DMA_BASE (LPC43_AHBPERIPH_BASE + 0x00002000)
|
||||
#define LPC43_SPIFI_PERIPH_BASE (LPC43_AHBPERIPH_BASE + 0x00003000)
|
||||
#define LPC43_MMCSD_BASE (LPC43_AHBPERIPH_BASE + 0x00004000)
|
||||
#define LPC43_SDMMC_BASE (LPC43_AHBPERIPH_BASE + 0x00004000)
|
||||
#define LPC43_EMC_BASE (LPC43_AHBPERIPH_BASE + 0x00005000)
|
||||
#define LPC43_USB0_BASE (LPC43_AHBPERIPH_BASE + 0x00006000)
|
||||
#define LPC43_USB1_BASE (LPC43_AHBPERIPH_BASE + 0x00007000)
|
||||
|
|
|
|||
|
|
@ -1,211 +1,211 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_qei.h
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* Control registers */
|
||||
|
||||
#define LPC43_QEI_CON_OFFSET 0x0000 /* Control register */
|
||||
#define LPC43_QEI_STAT_OFFSET 0x0004 /* Encoder status register */
|
||||
#define LPC43_QEI_CONF_OFFSET 0x0008 /* Configuration register */
|
||||
|
||||
/* Position, index, and timer registers */
|
||||
|
||||
#define LPC43_QEI_POS_OFFSET 0x000c /* Position register */
|
||||
#define LPC43_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */
|
||||
#define LPC43_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */
|
||||
#define LPC43_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */
|
||||
#define LPC43_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */
|
||||
#define LPC43_QEI_INXCNT_OFFSET 0x0020 /* Index count register */
|
||||
#define LPC43_QEI_INXCMP0_OFFSET 0x0024 /* Index compare register 0 */
|
||||
#define LPC43_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */
|
||||
#define LPC43_QEI_TIME_OFFSET 0x002c /* Velocity timer register */
|
||||
#define LPC43_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */
|
||||
#define LPC43_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */
|
||||
#define LPC43_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */
|
||||
#define LPC43_QEI_FLTRPHA_OFFSET 0x003c /* Input digital filter register phase A */
|
||||
#define LPC43_QEI_FLTRPHB_OFFSET 0x0040 /* Input digital filter register phase B */
|
||||
#define LPC43_QEI_FLTRINX_OFFSET 0x0044 /* Input digital filter register index */
|
||||
#define LPC43_QEI_WINDOW_OFFSET 0x0048 /* Index acceptance window register */
|
||||
#define LPC43_QEI_INXCMP1_OFFSET 0x004c /* Index compare register 1 */
|
||||
#define LPC43_QEI_INXCMP2_OFFSET 0x0050 /* Index compare register 2 */
|
||||
|
||||
/* Interrupt registers */
|
||||
|
||||
#define LPC43_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */
|
||||
#define LPC43_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */
|
||||
#define LPC43_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */
|
||||
#define LPC43_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */
|
||||
#define LPC43_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */
|
||||
#define LPC43_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
/* Control registers */
|
||||
|
||||
#define LPC43_QEI_CON (LPC43_QEI_BASE+LPC43_QEI_CON_OFFSET)
|
||||
#define LPC43_QEI_STAT (LPC43_QEI_BASE+LPC43_QEI_STAT_OFFSET)
|
||||
#define LPC43_QEI_CONF (LPC43_QEI_BASE+LPC43_QEI_CONF_OFFSET)
|
||||
|
||||
/* Position, index, and timer registers */
|
||||
|
||||
#define LPC43_QEI_POS (LPC43_QEI_BASE+LPC43_QEI_POS_OFFSET)
|
||||
#define LPC43_QEI_MAXPOS (LPC43_QEI_BASE+LPC43_QEI_MAXPOS_OFFSET)
|
||||
#define LPC43_QEI_CMPOS0 (LPC43_QEI_BASE+LPC43_QEI_CMPOS0_OFFSET)
|
||||
#define LPC43_QEI_CMPOS1 (LPC43_QEI_BASE+LPC43_QEI_CMPOS1_OFFSET)
|
||||
#define LPC43_QEI_CMPOS2 (LPC43_QEI_BASE+LPC43_QEI_CMPOS2_OFFSET)
|
||||
#define LPC43_QEI_INXCNT (LPC43_QEI_BASE+LPC43_QEI_INXCNT_OFFSET)
|
||||
#define LPC43_QEI_INXCMP0 (LPC43_QEI_BASE+LPC43_QEI_INXCMP0_OFFSET)
|
||||
#define LPC43_QEI_LOAD (LPC43_QEI_BASE+LPC43_QEI_LOAD_OFFSET)
|
||||
#define LPC43_QEI_TIME (LPC43_QEI_BASE+LPC43_QEI_TIME_OFFSET)
|
||||
#define LPC43_QEI_VEL (LPC43_QEI_BASE+LPC43_QEI_VEL_OFFSET)
|
||||
#define LPC43_QEI_CAP (LPC43_QEI_BASE+LPC43_QEI_CAP_OFFSET)
|
||||
#define LPC43_QEI_VELCOMP (LPC43_QEI_BASE+LPC43_QEI_VELCOMP_OFFSET)
|
||||
#define LPC43_QEI_FLTRPHA (LPC43_QEI_BASE+LPC43_QEI_FLTRPHA_OFFSET)
|
||||
#define LPC43_QEI_FLTRPHB (LPC43_QEI_BASE+LPC43_QEI_FLTRPHB_OFFSET)
|
||||
#define LPC43_QEI_FLTRINX (LPC43_QEI_BASE+LPC43_QEI_FLTRINX_OFFSET)
|
||||
#define LPC43_QEI_WINDOW (LPC43_QEI_BASE+LPC43_QEI_WINDOW_OFFSET)
|
||||
#define LPC43_QEI_INXCMP1 (LPC43_QEI_BASE+LPC43_QEI_INXCMP1_OFFSET)
|
||||
#define LPC43_QEI_INXCMP2 (LPC43_QEI_BASE+LPC43_QEI_INXCMP2_OFFSET)
|
||||
|
||||
/* Interrupt registers */
|
||||
|
||||
#define LPC43_QEI_IEC (LPC43_QEI_BASE+LPC43_QEI_IEC_OFFSET)
|
||||
#define LPC43_QEI_IES (LPC43_QEI_BASE+LPC43_QEI_IES_OFFSET)
|
||||
#define LPC43_QEI_INTSTAT (LPC43_QEI_BASE+LPC43_QEI_INTSTAT_OFFSET)
|
||||
#define LPC43_QEI_IE (LPC43_QEI_BASE+LPC43_QEI_IE_OFFSET)
|
||||
#define LPC43_QEI_CLR (LPC43_QEI_BASE+LPC43_QEI_CLR_OFFSET)
|
||||
#define LPC43_QEI_SET (LPC43_QEI_BASE+LPC43_QEI_SET_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* The following registers hold 32-bit integer values and have no bit fields defined
|
||||
* in this section:
|
||||
*
|
||||
* Position register (POS)
|
||||
* Maximum position register (MAXPOS)
|
||||
* Position compare register 0 (CMPOS0)
|
||||
* Position compare register 1 (CMPOS1)
|
||||
* Position compare register 2 (CMPOS2)
|
||||
* Index count register (INXCNT)
|
||||
* Index compare register 0 (INXCMP0)
|
||||
* Index compare register 1 (INXCMP1)
|
||||
* Index compare register 2 (INXCMP2)
|
||||
* Velocity timer reload register (LOAD)
|
||||
* Velocity timer register (TIME)
|
||||
* Velocity counter register (VEL)
|
||||
* Velocity capture register (CAP)
|
||||
* Velocity compare register (VELCOMP)
|
||||
* Digital filter registers (FLTRPHA, FLTRPHB)
|
||||
* Digital filter index register (FLTINX)
|
||||
* Index acceptance window register (WINDOW)
|
||||
*/
|
||||
|
||||
/* Control registers */
|
||||
/* Control register */
|
||||
|
||||
#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */
|
||||
#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */
|
||||
#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */
|
||||
#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */
|
||||
/* Bits 4-31: reserved */
|
||||
/* Encoder status register */
|
||||
|
||||
#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */
|
||||
/* Bits 1-31: reserved */
|
||||
/* Configuration register */
|
||||
|
||||
#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */
|
||||
#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */
|
||||
#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */
|
||||
#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */
|
||||
#define QEI_CONF_CRESPI (1 << 4) /* Bit 4: Reset position counter on index */
|
||||
/* Bits 1-15: reserved */
|
||||
#define QEI_CONF_INXGATE_SHIFT (16) /* Bits 16-19: Index gating configuration */
|
||||
#define QEI_CONF_INXGATE_MASK (15 << QEI_CONF_INXGATE_SHIFT)
|
||||
# define QEI_CONF_INXGATE_A1B0 (1 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=1 Phb=0 */
|
||||
# define QEI_CONF_INXGATE_A1B1 (2 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=1 Phb=1 */
|
||||
# define QEI_CONF_INXGATE_A0B1 (4 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=0 Phb=1 */
|
||||
# define QEI_CONF_INXGATE_A0B0 (8 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=0 Phb=0 */
|
||||
/* Bits 4-31: reserved */
|
||||
|
||||
/* Interrupt registers */
|
||||
/* Interrupt enable clear register (IEC), Interrupt enable set register (IES),
|
||||
* Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt
|
||||
* status clear register (CLR), and Interrupt status set register (SET) common
|
||||
* bit definitions.
|
||||
*/
|
||||
|
||||
#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */
|
||||
#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */
|
||||
#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */
|
||||
#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */
|
||||
#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */
|
||||
#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */
|
||||
#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */
|
||||
#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */
|
||||
#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */
|
||||
#define QEI_INT_REV0 (1 << 9) /* Bit 9: Index 0 compare equal to current index count */
|
||||
#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Position 0 and revolution count interrupt */
|
||||
#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */
|
||||
#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */
|
||||
#define QEI_INT_REV1 (1 << 13) /* Bit 13: Index 1 compare equal to current index count */
|
||||
#define QEI_INT_REV2 (1 << 14) /* Bit 14: Index 2 compare equal to current index count */
|
||||
#define QEI_INT_MAXPOS (1 << 15) /* Bit 15: Current position count goes through MAXPOS */
|
||||
/* Bits 16-31: reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_qei.h
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* Control registers */
|
||||
|
||||
#define LPC43_QEI_CON_OFFSET 0x0000 /* Control register */
|
||||
#define LPC43_QEI_STAT_OFFSET 0x0004 /* Encoder status register */
|
||||
#define LPC43_QEI_CONF_OFFSET 0x0008 /* Configuration register */
|
||||
|
||||
/* Position, index, and timer registers */
|
||||
|
||||
#define LPC43_QEI_POS_OFFSET 0x000c /* Position register */
|
||||
#define LPC43_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */
|
||||
#define LPC43_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */
|
||||
#define LPC43_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */
|
||||
#define LPC43_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */
|
||||
#define LPC43_QEI_INXCNT_OFFSET 0x0020 /* Index count register */
|
||||
#define LPC43_QEI_INXCMP0_OFFSET 0x0024 /* Index compare register 0 */
|
||||
#define LPC43_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */
|
||||
#define LPC43_QEI_TIME_OFFSET 0x002c /* Velocity timer register */
|
||||
#define LPC43_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */
|
||||
#define LPC43_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */
|
||||
#define LPC43_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */
|
||||
#define LPC43_QEI_FLTRPHA_OFFSET 0x003c /* Input digital filter register phase A */
|
||||
#define LPC43_QEI_FLTRPHB_OFFSET 0x0040 /* Input digital filter register phase B */
|
||||
#define LPC43_QEI_FLTRINX_OFFSET 0x0044 /* Input digital filter register index */
|
||||
#define LPC43_QEI_WINDOW_OFFSET 0x0048 /* Index acceptance window register */
|
||||
#define LPC43_QEI_INXCMP1_OFFSET 0x004c /* Index compare register 1 */
|
||||
#define LPC43_QEI_INXCMP2_OFFSET 0x0050 /* Index compare register 2 */
|
||||
|
||||
/* Interrupt registers */
|
||||
|
||||
#define LPC43_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */
|
||||
#define LPC43_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */
|
||||
#define LPC43_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */
|
||||
#define LPC43_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */
|
||||
#define LPC43_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */
|
||||
#define LPC43_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
/* Control registers */
|
||||
|
||||
#define LPC43_QEI_CON (LPC43_QEI_BASE+LPC43_QEI_CON_OFFSET)
|
||||
#define LPC43_QEI_STAT (LPC43_QEI_BASE+LPC43_QEI_STAT_OFFSET)
|
||||
#define LPC43_QEI_CONF (LPC43_QEI_BASE+LPC43_QEI_CONF_OFFSET)
|
||||
|
||||
/* Position, index, and timer registers */
|
||||
|
||||
#define LPC43_QEI_POS (LPC43_QEI_BASE+LPC43_QEI_POS_OFFSET)
|
||||
#define LPC43_QEI_MAXPOS (LPC43_QEI_BASE+LPC43_QEI_MAXPOS_OFFSET)
|
||||
#define LPC43_QEI_CMPOS0 (LPC43_QEI_BASE+LPC43_QEI_CMPOS0_OFFSET)
|
||||
#define LPC43_QEI_CMPOS1 (LPC43_QEI_BASE+LPC43_QEI_CMPOS1_OFFSET)
|
||||
#define LPC43_QEI_CMPOS2 (LPC43_QEI_BASE+LPC43_QEI_CMPOS2_OFFSET)
|
||||
#define LPC43_QEI_INXCNT (LPC43_QEI_BASE+LPC43_QEI_INXCNT_OFFSET)
|
||||
#define LPC43_QEI_INXCMP0 (LPC43_QEI_BASE+LPC43_QEI_INXCMP0_OFFSET)
|
||||
#define LPC43_QEI_LOAD (LPC43_QEI_BASE+LPC43_QEI_LOAD_OFFSET)
|
||||
#define LPC43_QEI_TIME (LPC43_QEI_BASE+LPC43_QEI_TIME_OFFSET)
|
||||
#define LPC43_QEI_VEL (LPC43_QEI_BASE+LPC43_QEI_VEL_OFFSET)
|
||||
#define LPC43_QEI_CAP (LPC43_QEI_BASE+LPC43_QEI_CAP_OFFSET)
|
||||
#define LPC43_QEI_VELCOMP (LPC43_QEI_BASE+LPC43_QEI_VELCOMP_OFFSET)
|
||||
#define LPC43_QEI_FLTRPHA (LPC43_QEI_BASE+LPC43_QEI_FLTRPHA_OFFSET)
|
||||
#define LPC43_QEI_FLTRPHB (LPC43_QEI_BASE+LPC43_QEI_FLTRPHB_OFFSET)
|
||||
#define LPC43_QEI_FLTRINX (LPC43_QEI_BASE+LPC43_QEI_FLTRINX_OFFSET)
|
||||
#define LPC43_QEI_WINDOW (LPC43_QEI_BASE+LPC43_QEI_WINDOW_OFFSET)
|
||||
#define LPC43_QEI_INXCMP1 (LPC43_QEI_BASE+LPC43_QEI_INXCMP1_OFFSET)
|
||||
#define LPC43_QEI_INXCMP2 (LPC43_QEI_BASE+LPC43_QEI_INXCMP2_OFFSET)
|
||||
|
||||
/* Interrupt registers */
|
||||
|
||||
#define LPC43_QEI_IEC (LPC43_QEI_BASE+LPC43_QEI_IEC_OFFSET)
|
||||
#define LPC43_QEI_IES (LPC43_QEI_BASE+LPC43_QEI_IES_OFFSET)
|
||||
#define LPC43_QEI_INTSTAT (LPC43_QEI_BASE+LPC43_QEI_INTSTAT_OFFSET)
|
||||
#define LPC43_QEI_IE (LPC43_QEI_BASE+LPC43_QEI_IE_OFFSET)
|
||||
#define LPC43_QEI_CLR (LPC43_QEI_BASE+LPC43_QEI_CLR_OFFSET)
|
||||
#define LPC43_QEI_SET (LPC43_QEI_BASE+LPC43_QEI_SET_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* The following registers hold 32-bit integer values and have no bit fields defined
|
||||
* in this section:
|
||||
*
|
||||
* Position register (POS)
|
||||
* Maximum position register (MAXPOS)
|
||||
* Position compare register 0 (CMPOS0)
|
||||
* Position compare register 1 (CMPOS1)
|
||||
* Position compare register 2 (CMPOS2)
|
||||
* Index count register (INXCNT)
|
||||
* Index compare register 0 (INXCMP0)
|
||||
* Index compare register 1 (INXCMP1)
|
||||
* Index compare register 2 (INXCMP2)
|
||||
* Velocity timer reload register (LOAD)
|
||||
* Velocity timer register (TIME)
|
||||
* Velocity counter register (VEL)
|
||||
* Velocity capture register (CAP)
|
||||
* Velocity compare register (VELCOMP)
|
||||
* Digital filter registers (FLTRPHA, FLTRPHB)
|
||||
* Digital filter index register (FLTINX)
|
||||
* Index acceptance window register (WINDOW)
|
||||
*/
|
||||
|
||||
/* Control registers */
|
||||
/* Control register */
|
||||
|
||||
#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */
|
||||
#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */
|
||||
#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */
|
||||
#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */
|
||||
/* Bits 4-31: reserved */
|
||||
/* Encoder status register */
|
||||
|
||||
#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */
|
||||
/* Bits 1-31: reserved */
|
||||
/* Configuration register */
|
||||
|
||||
#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */
|
||||
#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */
|
||||
#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */
|
||||
#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */
|
||||
#define QEI_CONF_CRESPI (1 << 4) /* Bit 4: Reset position counter on index */
|
||||
/* Bits 1-15: reserved */
|
||||
#define QEI_CONF_INXGATE_SHIFT (16) /* Bits 16-19: Index gating configuration */
|
||||
#define QEI_CONF_INXGATE_MASK (15 << QEI_CONF_INXGATE_SHIFT)
|
||||
# define QEI_CONF_INXGATE_A1B0 (1 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=1 Phb=0 */
|
||||
# define QEI_CONF_INXGATE_A1B1 (2 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=1 Phb=1 */
|
||||
# define QEI_CONF_INXGATE_A0B1 (4 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=0 Phb=1 */
|
||||
# define QEI_CONF_INXGATE_A0B0 (8 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=0 Phb=0 */
|
||||
/* Bits 4-31: reserved */
|
||||
|
||||
/* Interrupt registers */
|
||||
/* Interrupt enable clear register (IEC), Interrupt enable set register (IES),
|
||||
* Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt
|
||||
* status clear register (CLR), and Interrupt status set register (SET) common
|
||||
* bit definitions.
|
||||
*/
|
||||
|
||||
#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */
|
||||
#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */
|
||||
#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */
|
||||
#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */
|
||||
#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */
|
||||
#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */
|
||||
#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */
|
||||
#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */
|
||||
#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */
|
||||
#define QEI_INT_REV0 (1 << 9) /* Bit 9: Index 0 compare equal to current index count */
|
||||
#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Position 0 and revolution count interrupt */
|
||||
#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */
|
||||
#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */
|
||||
#define QEI_INT_REV1 (1 << 13) /* Bit 13: Index 1 compare equal to current index count */
|
||||
#define QEI_INT_REV2 (1 << 14) /* Bit 14: Index 2 compare equal to current index count */
|
||||
#define QEI_INT_MAXPOS (1 << 15) /* Bit 15: Current position count goes through MAXPOS */
|
||||
/* Bits 16-31: reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H */
|
||||
|
|
|
|||
|
|
@ -1,89 +1,89 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_rit.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */
|
||||
#define LPC43_RIT_MASK_OFFSET 0x0004 /* Mask register */
|
||||
#define LPC43_RIT_CTRL_OFFSET 0x0008 /* Control register */
|
||||
#define LPC43_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_RIT_COMPVAL (LPC43_RIT_BASE+LPC43_RIT_COMPVAL_OFFSET)
|
||||
#define LPC43_RIT_MASK (LPC43_RIT_BASE+LPC43_RIT_MASK_OFFSET)
|
||||
#define LPC43_RIT_CTRL (LPC43_RIT_BASE+LPC43_RIT_CTRL_OFFSET)
|
||||
#define LPC43_RIT_COUNTER (LPC43_RIT_BASE+LPC43_RIT_COUNTER_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Compare register (Bits 0-31: value compared to the counter) */
|
||||
|
||||
/* Mask register (Bits 0-31: 32-bit mask value) */
|
||||
|
||||
/* Control register */
|
||||
|
||||
#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */
|
||||
#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */
|
||||
#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */
|
||||
#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* 32-bit counter (Bits 0-31: 32-bit up counter) */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_rit.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */
|
||||
#define LPC43_RIT_MASK_OFFSET 0x0004 /* Mask register */
|
||||
#define LPC43_RIT_CTRL_OFFSET 0x0008 /* Control register */
|
||||
#define LPC43_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_RIT_COMPVAL (LPC43_RIT_BASE+LPC43_RIT_COMPVAL_OFFSET)
|
||||
#define LPC43_RIT_MASK (LPC43_RIT_BASE+LPC43_RIT_MASK_OFFSET)
|
||||
#define LPC43_RIT_CTRL (LPC43_RIT_BASE+LPC43_RIT_CTRL_OFFSET)
|
||||
#define LPC43_RIT_COUNTER (LPC43_RIT_BASE+LPC43_RIT_COUNTER_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Compare register (Bits 0-31: value compared to the counter) */
|
||||
|
||||
/* Mask register (Bits 0-31: 32-bit mask value) */
|
||||
|
||||
/* Control register */
|
||||
|
||||
#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */
|
||||
#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */
|
||||
#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */
|
||||
#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* 32-bit counter (Bits 0-31: 32-bit up counter) */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H */
|
||||
|
|
|
|||
|
|
@ -1,230 +1,230 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_rtc.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* Miscellaneous registers */
|
||||
|
||||
#define LPC43_RTC_ILR_OFFSET 0x0000 /* Interrupt Location Register */
|
||||
#define LPC43_RTC_CCR_OFFSET 0x0008 /* Clock Control Register */
|
||||
#define LPC43_RTC_CIIR_OFFSET 0x000c /* Counter Increment Interrupt Register */
|
||||
#define LPC43_RTC_AMR_OFFSET 0x0010 /* Alarm Mask Register */
|
||||
|
||||
/* Consolidated time registers */
|
||||
|
||||
#define LPC43_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */
|
||||
#define LPC43_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */
|
||||
#define LPC43_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */
|
||||
|
||||
/* Time counter registers */
|
||||
|
||||
#define LPC43_RTC_SEC_OFFSET 0x0020 /* Seconds Counter */
|
||||
#define LPC43_RTC_MIN_OFFSET 0x0024 /* Minutes Register */
|
||||
#define LPC43_RTC_HOUR_OFFSET 0x0028 /* Hours Register */
|
||||
#define LPC43_RTC_DOM_OFFSET 0x002c /* Day of Month Register */
|
||||
#define LPC43_RTC_DOW_OFFSET 0x0030 /* Day of Week Register */
|
||||
#define LPC43_RTC_DOY_OFFSET 0x0034 /* Day of Year Register */
|
||||
#define LPC43_RTC_MONTH_OFFSET 0x0038 /* Months Register */
|
||||
#define LPC43_RTC_YEAR_OFFSET 0x003c /* Years Register */
|
||||
#define LPC43_RTC_CALIB_OFFSET 0x0040 /* Calibration Value Register */
|
||||
|
||||
/* Alarm register group */
|
||||
|
||||
#define LPC43_RTC_ASEC_OFFSET 0x0060 /* Alarm value for Seconds */
|
||||
#define LPC43_RTC_AMIN_OFFSET 0x0064 /* Alarm value for Minutes */
|
||||
#define LPC43_RTC_AHOUR_OFFSET 0x0068 /* Alarm value for Hours */
|
||||
#define LPC43_RTC_ADOM_OFFSET 0x006c /* Alarm value for Day of Month */
|
||||
#define LPC43_RTC_ADOW_OFFSET 0x0070 /* Alarm value for Day of Week */
|
||||
#define LPC43_RTC_ADOY_OFFSET 0x0074 /* Alarm value for Day of Year */
|
||||
#define LPC43_RTC_AMON_OFFSET 0x0078 /* Alarm value for Months */
|
||||
#define LPC43_RTC_AYEAR_OFFSET 0x007c /* Alarm value for Year */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
/* Miscellaneous registers */
|
||||
|
||||
#define LPC43_RTC_ILR (LPC43_RTC_BASE+LPC43_RTC_ILR_OFFSET)
|
||||
#define LPC43_RTC_CCR (LPC43_RTC_BASE+LPC43_RTC_CCR_OFFSET)
|
||||
#define LPC43_RTC_CIIR (LPC43_RTC_BASE+LPC43_RTC_CIIR_OFFSET)
|
||||
#define LPC43_RTC_AMR (LPC43_RTC_BASE+LPC43_RTC_AMR_OFFSET)
|
||||
|
||||
/* Consolidated time registers */
|
||||
|
||||
#define LPC43_RTC_CTIME0 (LPC43_RTC_BASE+LPC43_RTC_CTIME0_OFFSET)
|
||||
#define LPC43_RTC_CTIME1 (LPC43_RTC_BASE+LPC43_RTC_CTIME1_OFFSET)
|
||||
#define LPC43_RTC_CTIME2 (LPC43_RTC_BASE+LPC43_RTC_CTIME2_OFFSET)
|
||||
|
||||
/* Time counter registers */
|
||||
|
||||
#define LPC43_RTC_SEC (LPC43_RTC_BASE+LPC43_RTC_SEC_OFFSET)
|
||||
#define LPC43_RTC_MIN (LPC43_RTC_BASE+LPC43_RTC_MIN_OFFSET)
|
||||
#define LPC43_RTC_HOUR (LPC43_RTC_BASE+LPC43_RTC_HOUR_OFFSET)
|
||||
#define LPC43_RTC_DOM (LPC43_RTC_BASE+LPC43_RTC_DOM_OFFSET)
|
||||
#define LPC43_RTC_DOW (LPC43_RTC_BASE+LPC43_RTC_DOW_OFFSET)
|
||||
#define LPC43_RTC_DOY (LPC43_RTC_BASE+LPC43_RTC_DOY_OFFSET)
|
||||
#define LPC43_RTC_MONTH (LPC43_RTC_BASE+LPC43_RTC_MONTH_OFFSET)
|
||||
#define LPC43_RTC_YEAR (LPC43_RTC_BASE+LPC43_RTC_YEAR_OFFSET)
|
||||
#define LPC43_RTC_CALIB (LPC43_RTC_BASE+LPC43_RTC_CALIB_OFFSET)
|
||||
|
||||
/* Alarm register group */
|
||||
|
||||
#define LPC43_RTC_ASEC (LPC43_RTC_BASE+LPC43_RTC_ASEC_OFFSET)
|
||||
#define LPC43_RTC_AMIN (LPC43_RTC_BASE+LPC43_RTC_AMIN_OFFSET)
|
||||
#define LPC43_RTC_AHOUR (LPC43_RTC_BASE+LPC43_RTC_AHOUR_OFFSET)
|
||||
#define LPC43_RTC_ADOM (LPC43_RTC_BASE+LPC43_RTC_ADOM_OFFSET)
|
||||
#define LPC43_RTC_ADOW (LPC43_RTC_BASE+LPC43_RTC_ADOW_OFFSET)
|
||||
#define LPC43_RTC_ADOY (LPC43_RTC_BASE+LPC43_RTC_ADOY_OFFSET)
|
||||
#define LPC43_RTC_AMON (LPC43_RTC_BASE+LPC43_RTC_AMON_OFFSET)
|
||||
#define LPC43_RTC_AYEAR (LPC43_RTC_BASE+LPC43_RTC_AYEAR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Miscellaneous registers */
|
||||
/* Interrupt Location Register */
|
||||
|
||||
#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */
|
||||
#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* Clock Control Register */
|
||||
|
||||
#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */
|
||||
#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */
|
||||
/* Bits 2-3: Internal test mode controls */
|
||||
#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */
|
||||
/* Bits 5-31: Reserved */
|
||||
/* Counter Increment Interrupt Register */
|
||||
|
||||
#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */
|
||||
#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */
|
||||
#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */
|
||||
#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */
|
||||
#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */
|
||||
#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */
|
||||
#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */
|
||||
#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Alarm Mask Register */
|
||||
|
||||
#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */
|
||||
#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */
|
||||
#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */
|
||||
#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */
|
||||
#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */
|
||||
#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */
|
||||
#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */
|
||||
#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Consolidated time registers */
|
||||
/* Consolidated Time Register 0 */
|
||||
|
||||
#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */
|
||||
#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT)
|
||||
/* Bits 6-7: Reserved */
|
||||
#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */
|
||||
#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT)
|
||||
/* Bits 14-15: Reserved */
|
||||
#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */
|
||||
#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT)
|
||||
/* Bits 21-23: Reserved */
|
||||
#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */
|
||||
#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT)
|
||||
/* Bits 27-31: Reserved */
|
||||
/* Consolidated Time Register 1 */
|
||||
|
||||
#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */
|
||||
#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT)
|
||||
/* Bits 5-7: Reserved */
|
||||
#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */
|
||||
#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */
|
||||
#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT)
|
||||
/* Bits 28-31: Reserved */
|
||||
/* Consolidated Time Register 2 */
|
||||
|
||||
#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */
|
||||
#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Time counter registers */
|
||||
|
||||
#define RTC_SEC_MASK (0x003f)
|
||||
#define RTC_MIN_MASK (0x003f)
|
||||
#define RTC_HOUR_MASK (0x001f)
|
||||
#define RTC_DOM_MASK (0x001f)
|
||||
#define RTC_DOW_MASK (0x0007)
|
||||
#define RTC_DOY_MASK (0x01ff)
|
||||
#define RTC_MONTH_MASK (0x000f)
|
||||
#define RTC_YEAR_MASK (0x0fff)
|
||||
|
||||
/* Calibration Value Register */
|
||||
|
||||
#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */
|
||||
#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT)
|
||||
#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */
|
||||
/* Bits 18-31: Reserved */
|
||||
/* Alarm register group */
|
||||
|
||||
#define RTC_ASEC_MASK (0x003f)
|
||||
#define RTC_AMIN_MASK (0x003f)
|
||||
#define RTC_AHOUR_MASK (0x001f)
|
||||
#define RTC_ADOM_MASK (0x001f)
|
||||
#define RTC_ADOW_MASK (0x0007)
|
||||
#define RTC_ADOY_MASK (0x01ff)
|
||||
#define RTC_AMON_MASK (0x000f)
|
||||
#define RTC_AYEAR_MASK (0x0fff)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_rtc.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* Miscellaneous registers */
|
||||
|
||||
#define LPC43_RTC_ILR_OFFSET 0x0000 /* Interrupt Location Register */
|
||||
#define LPC43_RTC_CCR_OFFSET 0x0008 /* Clock Control Register */
|
||||
#define LPC43_RTC_CIIR_OFFSET 0x000c /* Counter Increment Interrupt Register */
|
||||
#define LPC43_RTC_AMR_OFFSET 0x0010 /* Alarm Mask Register */
|
||||
|
||||
/* Consolidated time registers */
|
||||
|
||||
#define LPC43_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */
|
||||
#define LPC43_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */
|
||||
#define LPC43_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */
|
||||
|
||||
/* Time counter registers */
|
||||
|
||||
#define LPC43_RTC_SEC_OFFSET 0x0020 /* Seconds Counter */
|
||||
#define LPC43_RTC_MIN_OFFSET 0x0024 /* Minutes Register */
|
||||
#define LPC43_RTC_HOUR_OFFSET 0x0028 /* Hours Register */
|
||||
#define LPC43_RTC_DOM_OFFSET 0x002c /* Day of Month Register */
|
||||
#define LPC43_RTC_DOW_OFFSET 0x0030 /* Day of Week Register */
|
||||
#define LPC43_RTC_DOY_OFFSET 0x0034 /* Day of Year Register */
|
||||
#define LPC43_RTC_MONTH_OFFSET 0x0038 /* Months Register */
|
||||
#define LPC43_RTC_YEAR_OFFSET 0x003c /* Years Register */
|
||||
#define LPC43_RTC_CALIB_OFFSET 0x0040 /* Calibration Value Register */
|
||||
|
||||
/* Alarm register group */
|
||||
|
||||
#define LPC43_RTC_ASEC_OFFSET 0x0060 /* Alarm value for Seconds */
|
||||
#define LPC43_RTC_AMIN_OFFSET 0x0064 /* Alarm value for Minutes */
|
||||
#define LPC43_RTC_AHOUR_OFFSET 0x0068 /* Alarm value for Hours */
|
||||
#define LPC43_RTC_ADOM_OFFSET 0x006c /* Alarm value for Day of Month */
|
||||
#define LPC43_RTC_ADOW_OFFSET 0x0070 /* Alarm value for Day of Week */
|
||||
#define LPC43_RTC_ADOY_OFFSET 0x0074 /* Alarm value for Day of Year */
|
||||
#define LPC43_RTC_AMON_OFFSET 0x0078 /* Alarm value for Months */
|
||||
#define LPC43_RTC_AYEAR_OFFSET 0x007c /* Alarm value for Year */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
/* Miscellaneous registers */
|
||||
|
||||
#define LPC43_RTC_ILR (LPC43_RTC_BASE+LPC43_RTC_ILR_OFFSET)
|
||||
#define LPC43_RTC_CCR (LPC43_RTC_BASE+LPC43_RTC_CCR_OFFSET)
|
||||
#define LPC43_RTC_CIIR (LPC43_RTC_BASE+LPC43_RTC_CIIR_OFFSET)
|
||||
#define LPC43_RTC_AMR (LPC43_RTC_BASE+LPC43_RTC_AMR_OFFSET)
|
||||
|
||||
/* Consolidated time registers */
|
||||
|
||||
#define LPC43_RTC_CTIME0 (LPC43_RTC_BASE+LPC43_RTC_CTIME0_OFFSET)
|
||||
#define LPC43_RTC_CTIME1 (LPC43_RTC_BASE+LPC43_RTC_CTIME1_OFFSET)
|
||||
#define LPC43_RTC_CTIME2 (LPC43_RTC_BASE+LPC43_RTC_CTIME2_OFFSET)
|
||||
|
||||
/* Time counter registers */
|
||||
|
||||
#define LPC43_RTC_SEC (LPC43_RTC_BASE+LPC43_RTC_SEC_OFFSET)
|
||||
#define LPC43_RTC_MIN (LPC43_RTC_BASE+LPC43_RTC_MIN_OFFSET)
|
||||
#define LPC43_RTC_HOUR (LPC43_RTC_BASE+LPC43_RTC_HOUR_OFFSET)
|
||||
#define LPC43_RTC_DOM (LPC43_RTC_BASE+LPC43_RTC_DOM_OFFSET)
|
||||
#define LPC43_RTC_DOW (LPC43_RTC_BASE+LPC43_RTC_DOW_OFFSET)
|
||||
#define LPC43_RTC_DOY (LPC43_RTC_BASE+LPC43_RTC_DOY_OFFSET)
|
||||
#define LPC43_RTC_MONTH (LPC43_RTC_BASE+LPC43_RTC_MONTH_OFFSET)
|
||||
#define LPC43_RTC_YEAR (LPC43_RTC_BASE+LPC43_RTC_YEAR_OFFSET)
|
||||
#define LPC43_RTC_CALIB (LPC43_RTC_BASE+LPC43_RTC_CALIB_OFFSET)
|
||||
|
||||
/* Alarm register group */
|
||||
|
||||
#define LPC43_RTC_ASEC (LPC43_RTC_BASE+LPC43_RTC_ASEC_OFFSET)
|
||||
#define LPC43_RTC_AMIN (LPC43_RTC_BASE+LPC43_RTC_AMIN_OFFSET)
|
||||
#define LPC43_RTC_AHOUR (LPC43_RTC_BASE+LPC43_RTC_AHOUR_OFFSET)
|
||||
#define LPC43_RTC_ADOM (LPC43_RTC_BASE+LPC43_RTC_ADOM_OFFSET)
|
||||
#define LPC43_RTC_ADOW (LPC43_RTC_BASE+LPC43_RTC_ADOW_OFFSET)
|
||||
#define LPC43_RTC_ADOY (LPC43_RTC_BASE+LPC43_RTC_ADOY_OFFSET)
|
||||
#define LPC43_RTC_AMON (LPC43_RTC_BASE+LPC43_RTC_AMON_OFFSET)
|
||||
#define LPC43_RTC_AYEAR (LPC43_RTC_BASE+LPC43_RTC_AYEAR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Miscellaneous registers */
|
||||
/* Interrupt Location Register */
|
||||
|
||||
#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */
|
||||
#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* Clock Control Register */
|
||||
|
||||
#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */
|
||||
#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */
|
||||
/* Bits 2-3: Internal test mode controls */
|
||||
#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */
|
||||
/* Bits 5-31: Reserved */
|
||||
/* Counter Increment Interrupt Register */
|
||||
|
||||
#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */
|
||||
#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */
|
||||
#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */
|
||||
#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */
|
||||
#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */
|
||||
#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */
|
||||
#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */
|
||||
#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Alarm Mask Register */
|
||||
|
||||
#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */
|
||||
#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */
|
||||
#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */
|
||||
#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */
|
||||
#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */
|
||||
#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */
|
||||
#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */
|
||||
#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Consolidated time registers */
|
||||
/* Consolidated Time Register 0 */
|
||||
|
||||
#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */
|
||||
#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT)
|
||||
/* Bits 6-7: Reserved */
|
||||
#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */
|
||||
#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT)
|
||||
/* Bits 14-15: Reserved */
|
||||
#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */
|
||||
#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT)
|
||||
/* Bits 21-23: Reserved */
|
||||
#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */
|
||||
#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT)
|
||||
/* Bits 27-31: Reserved */
|
||||
/* Consolidated Time Register 1 */
|
||||
|
||||
#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */
|
||||
#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT)
|
||||
/* Bits 5-7: Reserved */
|
||||
#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */
|
||||
#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */
|
||||
#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT)
|
||||
/* Bits 28-31: Reserved */
|
||||
/* Consolidated Time Register 2 */
|
||||
|
||||
#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */
|
||||
#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Time counter registers */
|
||||
|
||||
#define RTC_SEC_MASK (0x003f)
|
||||
#define RTC_MIN_MASK (0x003f)
|
||||
#define RTC_HOUR_MASK (0x001f)
|
||||
#define RTC_DOM_MASK (0x001f)
|
||||
#define RTC_DOW_MASK (0x0007)
|
||||
#define RTC_DOY_MASK (0x01ff)
|
||||
#define RTC_MONTH_MASK (0x000f)
|
||||
#define RTC_YEAR_MASK (0x0fff)
|
||||
|
||||
/* Calibration Value Register */
|
||||
|
||||
#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */
|
||||
#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT)
|
||||
#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */
|
||||
/* Bits 18-31: Reserved */
|
||||
/* Alarm register group */
|
||||
|
||||
#define RTC_ASEC_MASK (0x003f)
|
||||
#define RTC_AMIN_MASK (0x003f)
|
||||
#define RTC_AHOUR_MASK (0x001f)
|
||||
#define RTC_ADOM_MASK (0x001f)
|
||||
#define RTC_ADOW_MASK (0x0007)
|
||||
#define RTC_ADOY_MASK (0x01ff)
|
||||
#define RTC_AMON_MASK (0x000f)
|
||||
#define RTC_AYEAR_MASK (0x0fff)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,390 @@
|
|||
/************************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_sdmmc.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SDMMC_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SDMMC_H
|
||||
|
||||
/************************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************************/
|
||||
|
||||
/* MCI register offsets (with respect to the MCI base) ******************************************/
|
||||
|
||||
#define LPC43_SDMMC_CTRL_OFFSET 0x0000 /* Control register */
|
||||
#define LPC43_SDMMC_PWREN_OFFSET 0x0004 /* Reserved */
|
||||
#define LPC43_SDMMC_CLKDIV_OFFSET 0x0008 /* Clock-divider register */
|
||||
#define LPC43_SDMMC_CLKSRC_OFFSET 0x000c /* Clock-source register */
|
||||
#define LPC43_SDMMC_CLKENA_OFFSET 0x0010 /* Clock-enable register */
|
||||
#define LPC43_SDMMC_TMOUT_OFFSET 0x0014 /* Time-out register */
|
||||
#define LPC43_SDMMC_CTYPE_OFFSET 0x0018 /* Card-type register */
|
||||
#define LPC43_SDMMC_BLKSIZ_OFFSET 0x001c /* Block-size register */
|
||||
#define LPC43_SDMMC_BYTCNT_OFFSET 0x0020 /* Byte-count register */
|
||||
#define LPC43_SDMMC_INTMASK_OFFSET 0x0024 /* Interrupt-mask register */
|
||||
#define LPC43_SDMMC_CMDARG_OFFSET 0x0028 /* Command-argument register */
|
||||
#define LPC43_SDMMC_CMD_OFFSET 0x002c /* Command register */
|
||||
#define LPC43_SDMMC_RESP0_OFFSET 0x0030 /* Response-0 register */
|
||||
#define LPC43_SDMMC_RESP1_OFFSET 0x0034 /* Response-1register */
|
||||
#define LPC43_SDMMC_RESP2_OFFSET 0x0038 /* Response-2 register */
|
||||
#define LPC43_SDMMC_RESP3_OFFSET 0x003c /* Response-3 register */
|
||||
#define LPC43_SDMMC_MINTSTS_OFFSET 0x0040 /* Masked interrupt-status register */
|
||||
#define LPC43_SDMMC_RINTSTS_OFFSET 0x0044 /* Raw interrupt-status register */
|
||||
#define LPC43_SDMMC_STATUS_OFFSET 0x0048 /* Status register */
|
||||
#define LPC43_SDMMC_FIFOTH_OFFSET 0x004c /* FIFO threshold register */
|
||||
#define LPC43_SDMMC_CDETECT_OFFSET 0x0050 /* Card-detect register value */
|
||||
#define LPC43_SDMMC_WRTPRT_OFFSET 0x0054 /* Write-protect register */
|
||||
/* 0x58: Reserved */
|
||||
#define LPC43_SDMMC_TCBCNT_OFFSET 0x005c /* Transferred CIU card byte count */
|
||||
#define LPC43_SDMMC_TBBCNT_OFFSET 0x0060 /* Transferred cpu/DMA to/from BIU-FIFO byte count */
|
||||
#define LPC43_SDMMC_DEBNCE_OFFSET 0x0064 /* Debounce count register */
|
||||
/* 0x0068-0x0074: Reserved */
|
||||
#define LPC43_SDMMC_RSTN_OFFSET 0x0078 /* Hardware Reset */
|
||||
#define LPC43_SDMMC_BMOD_OFFSET 0x0080 /* Bus Mode Register */
|
||||
#define LPC43_SDMMC_PLDMND_OFFSET 0x0084 /* Poll Demand Register */
|
||||
#define LPC43_SDMMC_DBADDR_OFFSET 0x0088 /* Descriptor List Base Address Register */
|
||||
#define LPC43_SDMMC_IDSTS_OFFSET 0x008c /* Internal DMAC Status Register */
|
||||
#define LPC43_SDMMC_IDINTEN_OFFSET 0x0090 /* Internal DMAC Interrupt Enable Register */
|
||||
#define LPC43_SDMMC_DSCADDR_OFFSET 0x0094 /* Current Host Descriptor Address Register */
|
||||
#define LPC43_SDMMC_BUFADDR_OFFSET 0x0098 /* Current Buffer Descriptor Address Register */
|
||||
/* 0x009c-0x00ff: Reserved */
|
||||
#define LPC43_SDMMC_DATA_OFFSET 0x0100 /* Data FIFO read/write (>=) */
|
||||
|
||||
/* MCI register (virtual) addresses *************************************************************/
|
||||
|
||||
#define LPC43_SDMMC_CTRL (LPC43_SDMMC_BASE+LPC43_SDMMC_CTRL_OFFSET)
|
||||
#define LPC43_SDMMC_PWREN (LPC43_SDMMC_BASE+LPC43_SDMMC_PWREN_OFFSET)
|
||||
#define LPC43_SDMMC_CLKDIV (LPC43_SDMMC_BASE+LPC43_SDMMC_CLKDIV_OFFSET)
|
||||
#define LPC43_SDMMC_CLKSRC (LPC43_SDMMC_BASE+LPC43_SDMMC_CLKSRC_OFFSET)
|
||||
#define LPC43_SDMMC_CLKENA (LPC43_SDMMC_BASE+LPC43_SDMMC_CLKENA_OFFSET)
|
||||
#define LPC43_SDMMC_TMOUT (LPC43_SDMMC_BASE+LPC43_SDMMC_TMOUT_OFFSET)
|
||||
#define LPC43_SDMMC_CTYPE (LPC43_SDMMC_BASE+LPC43_SDMMC_CTYPE_OFFSET)
|
||||
#define LPC43_SDMMC_BLKSIZ (LPC43_SDMMC_BASE+LPC43_SDMMC_BLKSIZ_OFFSET)
|
||||
#define LPC43_SDMMC_BYTCNT (LPC43_SDMMC_BASE+LPC43_SDMMC_BYTCNT_OFFSET)
|
||||
#define LPC43_SDMMC_INTMASK (LPC43_SDMMC_BASE+LPC43_SDMMC_INTMASK_OFFSET)
|
||||
#define LPC43_SDMMC_CMDARG (LPC43_SDMMC_BASE+LPC43_SDMMC_CMDARG_OFFSET)
|
||||
#define LPC43_SDMMC_CMD (LPC43_SDMMC_BASE+LPC43_SDMMC_CMD_OFFSET)
|
||||
#define LPC43_SDMMC_RESP0 (LPC43_SDMMC_BASE+LPC43_SDMMC_RESP0_OFFSET)
|
||||
#define LPC43_SDMMC_RESP1 (LPC43_SDMMC_BASE+LPC43_SDMMC_RESP1_OFFSET)
|
||||
#define LPC43_SDMMC_RESP2 (LPC43_SDMMC_BASE+LPC43_SDMMC_RESP2_OFFSET)
|
||||
#define LPC43_SDMMC_RESP3 (LPC43_SDMMC_BASE+LPC43_SDMMC_RESP3_OFFSET)
|
||||
#define LPC43_SDMMC_MINTSTS (LPC43_SDMMC_BASE+LPC43_SDMMC_MINTSTS_OFFSET)
|
||||
#define LPC43_SDMMC_RINTSTS (LPC43_SDMMC_BASE+LPC43_SDMMC_RINTSTS_OFFSET)
|
||||
#define LPC43_SDMMC_STATUS (LPC43_SDMMC_BASE+LPC43_SDMMC_STATUS_OFFSET)
|
||||
#define LPC43_SDMMC_FIFOTH (LPC43_SDMMC_BASE+LPC43_SDMMC_FIFOTH_OFFSET)
|
||||
#define LPC43_SDMMC_CDETECT (LPC43_SDMMC_BASE+LPC43_SDMMC_CDETECT_OFFSET)
|
||||
#define LPC43_SDMMC_WRTPRT (LPC43_SDMMC_BASE+LPC43_SDMMC_WRTPRT_OFFSET)
|
||||
#define LPC43_SDMMC_TCBCNT (LPC43_SDMMC_BASE+LPC43_SDMMC_TCBCNT_OFFSET)
|
||||
#define LPC43_SDMMC_TBBCNT (LPC43_SDMMC_BASE+LPC43_SDMMC_TBBCNT_OFFSET)
|
||||
#define LPC43_SDMMC_TBBCNT (LPC43_SDMMC_BASE+LPC43_SDMMC_TBBCNT_OFFSET)
|
||||
#define LPC43_SDMMC_DEBNCE (LPC43_SDMMC_BASE+LPC43_SDMMC_DEBNCE_OFFSET)
|
||||
#define LPC43_SDMMC_DEBNCE (LPC43_SDMMC_BASE+LPC43_SDMMC_DEBNCE_OFFSET)
|
||||
#define LPC43_SDMMC_RSTN (LPC43_SDMMC_BASE+LPC43_SDMMC_RSTN_OFFSET)
|
||||
#define LPC43_SDMMC_BMOD (LPC43_SDMMC_BASE+LPC43_SDMMC_BMOD_OFFSET)
|
||||
#define LPC43_SDMMC_PLDMND (LPC43_SDMMC_BASE+LPC43_SDMMC_PLDMND_OFFSET)
|
||||
#define LPC43_SDMMC_DBADDR (LPC43_SDMMC_BASE+LPC43_SDMMC_DBADDR_OFFSET)
|
||||
#define LPC43_SDMMC_IDSTS (LPC43_SDMMC_BASE+LPC43_SDMMC_IDSTS_OFFSET)
|
||||
#define LPC43_SDMMC_IDINTEN (LPC43_SDMMC_BASE+LPC43_SDMMC_IDINTEN_OFFSET)
|
||||
#define LPC43_SDMMC_DSCADDR (LPC43_SDMMC_BASE+LPC43_SDMMC_DSCADDR_OFFSET)
|
||||
#define LPC43_SDMMC_BUFADDR (LPC43_SDMMC_BASE+LPC43_SDMMC_BUFADDR_OFFSET)
|
||||
#define LPC43_SDMMC_DATA (LPC43_SDMMC_BASE+LPC43_SDMMC_DATA_OFFSET)
|
||||
|
||||
/* MCI register bit definitions *****************************************************************/
|
||||
|
||||
/* Control register CTRL */
|
||||
|
||||
#define SDMMC_CTRL_CNTLRRESET (1 << 0) /* Bit 0: Reset Module controller */
|
||||
#define SDMMC_CTRL_FIFORESET (1 << 1) /* Bit 1: Reset to data FIFO To reset FIFO pointers */
|
||||
#define SDMMC_CTRL_DMARESET (1 << 2) /* Bit 2: Reset internal DMA interface control logic */
|
||||
/* Bit 3: Reserved */
|
||||
#define SDMMC_CTRL_INTENABLE (1 << 4) /* Bit 4: Enable interrupts */
|
||||
/* Bit 5: Reserved */
|
||||
#define SDMMC_CTRL_READWAIT (1 << 6) /* Bit 6: Assert read wait */
|
||||
#define SDMMC_CTRL_SENDIRQRESP (1 << 7) /* Bit 7: Send auto IRQ response */
|
||||
#define SDMMC_CTRL_ABORTREAD (1 << 8) /* Bit 8: Reset data state-machine (suspend sequence) */
|
||||
#define SDMMC_CTRL_SENDCCSD (1 << 9) /* Bit 9: Send CCSD to CE-ATA device */
|
||||
#define SDMMC_CTRL_AUTOSTOP (1 << 10) /* Bit 10: Send STOP after CCSD to CE-ATA device */
|
||||
#define SDMMC_CTRL_CEATAINT (1 << 11) /* Bit 11: CE-ATA device interrupts enabled */
|
||||
/* Bits 12-15: Reserved */
|
||||
#define SDMMC_CTRL_CDVA0 (1 << 16) /* Bit 16: Controls SD_VOLT0 pin */
|
||||
#define SDMMC_CTRL_CDVA0 (1 << 17) /* Bit 17: Controls SD_VOLT1 pin */
|
||||
#define SDMMC_CTRL_CDVA0 (1 << 18) /* Bit 18: Controls SD_VOLT2 pin */
|
||||
/* Bits 19-23: Reserved */
|
||||
#define SDMMC_CTRL_INTDMA (1 << 25) /* Bit 24: SD/MMC DMA use */
|
||||
/* Bits 26-31: Reserved */
|
||||
/* Power Enable Register (PWREN) */
|
||||
|
||||
#define SDMMC_PWREN (1 << 0) /* Bit 0: Power on/off switch */
|
||||
/* Bits 1-31: Reserved */
|
||||
/* Clock divider register CLKDIV */
|
||||
|
||||
#define SDMMC_CLKDIV0_SHIFT (0) /* Bits 0-7: Clock divider 0 value */
|
||||
#define SDMMC_CLKDIV0_MASK (255 << SDMMC_CLKDIV0_SHIFT)
|
||||
#define SDMMC_CLKDIV1_SHIFT (8) /* Bits 8-15: Clock divider 1 value */
|
||||
#define SDMMC_CLKDIV1_MASK (255 << SDMMC_CLKDIV1_SHIFT)
|
||||
#define SDMMC_CLKDIV2_SHIFT (16) /* Bits 16-23: Clock divider 2 value */
|
||||
#define SDMMC_CLKDIV2_MASK (255 << SDMMC_CLKDIV2_SHIFT)
|
||||
#define SDMMC_CLKDIV3_SHIFT (24) /* Bits 24-31: Clock divider 3 value */
|
||||
#define SDMMC_CLKDIV3_MASK (255 << SDMMC_CLKDIV3_SHIFT)
|
||||
|
||||
/* Clock source register CLKSRC */
|
||||
|
||||
#define SDMMC_CLKSRC_SHIFT (0) /* Bits 0-1: Clock divider source for SD card */
|
||||
#define SDMMC_CLKSRC_MASK (3 << SDMMC_CLKSRC_SHIFT)
|
||||
# define SDMMC_CLKSRC_CLKDIV0 (0 << SDMMC_CLKSRC_SHIFT) /* Clock divider 0 */
|
||||
# define SDMMC_CLKSRC_CLKDIV1 (1 << SDMMC_CLKSRC_SHIFT) /* Clock divider 1 */
|
||||
# define SDMMC_CLKSRC_CLKDIV2 (2 << SDMMC_CLKSRC_SHIFT) /* Clock divider 2 */
|
||||
# define SDMMC_CLKSRC_CLKDIV3 (3 << SDMMC_CLKSRC_SHIFT) /* Clock divider 3 */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* Clock enable register CLKENA */
|
||||
|
||||
#define SDMMC_CLKENA_EMABLE (1 << 0) /* Bit 0: Clock enable */
|
||||
/* Bits 1-15: Reserved */
|
||||
#define SDMMC_CLKENA_LOWPOWER (1 << 16) /* Bit 16: Low-power mode */
|
||||
/* Bits 17-31: Reserved */
|
||||
/*Timeout register TMOUT */
|
||||
|
||||
#define SDMMC_TMOUT_RESPONSE_SHIFT (0) /* Bits 0-7: Response timeout value */
|
||||
#define SDMMC_TMOUT_RESPONSE_MASK (255 << SDMMC_TMOUT_RESPONSE_SHIFT)
|
||||
#define SDMMC_TMOUT_DATA_SHIFT (8) /* Bits 8-31: Data Read Timeout value */
|
||||
#define SDMMC_TMOUT_DATA_MASK (0x00ffffff << SDMMC_TMOUT_DATA_SHIFT)
|
||||
|
||||
/* Card type register CTYPE */
|
||||
|
||||
#define SDMMC_CTYPE_WIDTH4 (1 << 0) /* Bit 0: 4-bit mode */
|
||||
/* Bits 1-15: Reserved */
|
||||
#define SDMMC_CTYPE_WIDTH8 (1 << 16) /* Bit 16: 8-bit mode */
|
||||
/* Bits 17-31: Reserved */
|
||||
/* Blocksize register BLKSIZ */
|
||||
|
||||
#define SDMMC_BLKSIZ_SHIFT (0) /* Bits 0-15: Block size */
|
||||
#define SDMMC_BLKSIZ_MASK (0xffff << SDMMC_BLKSIZ_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Interrupt mask register INTMASK
|
||||
* Masked interrupt status register MINTSTS
|
||||
* Raw interrupt status register RINTSTS
|
||||
*/
|
||||
|
||||
#define SDMMC_INT_CDET (1 << 0) /* Bit 0: Card detect */
|
||||
#define SDMMC_INT_RE (1 << 1) /* Bit 1: Response error */
|
||||
#define SDMMC_INT_CDONE (1 << 2) /* Bit 2: Command done */
|
||||
#define SDMMC_INT_DTO (1 << 3) /* Bit 3: Data transfer over */
|
||||
#define SDMMC_INT_TXDR (1 << 4) /* Bit 4: Transmit FIFO data request */
|
||||
#define SDMMC_INT_RXDR (1 << 5) /* Bit 5: Receive FIFO data request */
|
||||
#define SDMMC_INT_RCRC (1 << 6) /* Bit 6: Response CRC error */
|
||||
#define SDMMC_INT_DCRC (1 << 7) /* Bit 7: Data CRC error */
|
||||
#define SDMMC_INT_RTO (1 << 8) /* Bit 8: Response timeout */
|
||||
#define SDMMC_INT_DRTO (1 << 9) /* Bit 9: Data read timeout */
|
||||
#define SDMMC_INT_HTO (1 << 10) /* Bit 10: Data starvation-by-cpu timeout */
|
||||
#define SDMMC_INT_FRUN (1 << 11) /* Bit 11: FIFO underrun/overrun error */
|
||||
#define SDMMC_INT_HLE (1 << 12) /* Bit 12: Hardware locked write error */
|
||||
#define SDMMC_INT_SBE (1 << 13) /* Bit 13: Start-bit error */
|
||||
#define SDMMC_INT_ACD (1 << 14) /* Bit 14: Auto command done */
|
||||
#define SDMMC_INT_EBE (1 << 15) /* Bit 15: End-bit error (read)/Write no CRC */
|
||||
#define SDMMC_INT_SDIO (1 << 16) /* Bit 16: Mask SDIO interrupt */
|
||||
/* Bits 17-31: Reserved */
|
||||
#define SDMMC_INT_ALL (0x1ffff)
|
||||
|
||||
/* Command register CMD */
|
||||
|
||||
#define SDMMC_CMD_CMDINDEX_SHIFT (0) /* Bits 0-5: 5:0 Command index */
|
||||
#define SDMMC_CMD_CMDINDEX_MASK (63 << SDMMC_CMD_CMDINDEX_SHIFT)
|
||||
#define SDMMC_CMD_RESPONSE (1 << 6) /* Bit 6: Response expected from card */
|
||||
#define SDMMC_CMD_LONGRESP (1 << 7) /* Bit 7: Long response expected from card */
|
||||
#define SDMMC_CMD_RESPCRC (1 << 8) /* Bit 8: Check response CRC */
|
||||
#define SDMMC_CMD_DATAXFREXPTD (1 << 9) /* Bit 9: Data transfer expected (read/write) */
|
||||
#define SDMMC_CMD_WRITE (1 << 10) /* Bit 10: Write to card */
|
||||
#define SDMMC_CMD_XFRMODE (1 << 11) /* Bit 11: Stream data transfer command */
|
||||
#define SDMMC_CMD_AUTOSTOP (1 << 12) /* Bit 12: Send stop command at end of data transfer */
|
||||
#define SDMMC_CMD_WAITPREV (1 << 13) /* Bit 13: Wait previous transfer complete before sending */
|
||||
#define SDMMC_CMD_STOPABORT (1 << 14) /* Bit 14: Stop current data transfer */
|
||||
#define SDMMC_CMD_SENDINIT (1 << 15) /* Bit 15: Send initialization sequence before command */
|
||||
/* Bits 16-20: Reserved */
|
||||
#define SDMMC_CMD_UPDCLOCK (1 << 21) /* Bit 21: Update clock register value (no command) */
|
||||
#define SDMMC_CMD_READCEATA (1 << 22) /* Bit 22: Performing read access on CE-ATA device */
|
||||
#define SDMMC_CMD_CCSEXPTD (1 << 23) /* Bit 23: Expect command completion from CE-ATA device */
|
||||
#define SDMMC_CMD_ENABOOT (1 << 24) /* Bit 24: Enable Boot */
|
||||
#define SDMMC_CMD_BACKEXPTED (1 << 25) /* Bit 25: Expect Boot Acknowledge */
|
||||
#define SDMMC_CMD_DISBOOT (1 << 26) /* Bit 26: Disable Boot */
|
||||
#define SDMMC_CMD_BOOTMODE (1 << 27) /* Bit 27: Boot Mode */
|
||||
#define SDMMC_CMD_VSWITCH (1 << 28) /* Bit 28: Voltage switch bit */
|
||||
/* Bits 29-30: Reserved */
|
||||
#define SDMMC_CMD_STARTCMD (1 << 31) /* Bit 31: Start command */
|
||||
|
||||
/* Status register STATUS */
|
||||
|
||||
#define SDMMC_STATUS_RXWMARK (1 << 0) /* Bit 0: FIFO reached Receive watermark level */
|
||||
#define SDMMC_STATUS_TXWMARK (1 << 1) /* Bit 1: FIFO reached Transmit watermark level */
|
||||
#define SDMMC_STATUS_FIFOEMPTY (1 << 2) /* Bit 2: FIFO is empty */
|
||||
#define SDMMC_STATUS_FIFOFULL (1 << 3) /* Bit 3: FIFO is full */
|
||||
#define SDMMC_STATUS_FSMSTATE_SHIFT (4) /* Bits 4-7: 7:4 Command FSM states */
|
||||
#define SDMMC_STATUS_FSMSTATE_MASK (15 << SDMMC_STATUS_FSMSTATE_SHIFT)
|
||||
# define SDMMC_STATUS_FSMSTATE_IDLE (0 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Idle */
|
||||
# define SDMMC_STATUS_FSMSTATE_INIT (1 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Send init sequence */
|
||||
# define SDMMC_STATUS_FSMSTATE_TXSTART (2 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd start bit */
|
||||
# define SDMMC_STATUS_FSMSTATE_TXTXBIT (3 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd tx bit */
|
||||
# define SDMMC_STATUS_FSMSTATE_TXCMDARG (4 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd index + arg */
|
||||
# define SDMMC_STATUS_FSMSTATE_TXCMDCRC (5 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd crc7 */
|
||||
# define SDMMC_STATUS_FSMSTATE_TXEND (6 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd end bit */
|
||||
# define SDMMC_STATUS_FSMSTATE_RXSTART (7 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp start bit */
|
||||
# define SDMMC_STATUS_FSMSTATE_RXIRQ (8 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp IRQ response */
|
||||
# define SDMMC_STATUS_FSMSTATE_RXTXBIT (9 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp tx bit */
|
||||
# define SDMMC_STATUS_FSMSTATE_RXCMD (10 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp cmd idx */
|
||||
# define SDMMC_STATUS_FSMSTATE_RXRESP (11 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp data */
|
||||
# define SDMMC_STATUS_FSMSTATE_RXRESPCRC (12 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp crc7 */
|
||||
# define SDMMC_STATUS_FSMSTATE_RXEND (13 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp end bit */
|
||||
# define SDMMC_STATUS_FSMSTATE_WAITNCC (14 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Cmd path wait NCC */
|
||||
# define SDMMC_STATUS_FSMSTATE_WAITTURN (15 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Wait; CMD-to-resp turnaround */
|
||||
#define SDMMC_STATUS_DAT3 (1 << 8) /* Bit 8: DAT3=1: Card present */
|
||||
#define SDMMC_STATUS_DATABUSY (1 << 9) /* Bit 9: Card data busy */
|
||||
#define SDMMC_STATUS_MCBUSY (1 << 10) /* Bit 10: Data transmit/receive state machine busy */
|
||||
#define SDMMC_STATUS_RESPINDEX_SHIFT (11) /* Bits 11-16: Index of previous response */
|
||||
#define SDMMC_STATUS_RESPINDEX_MASK (63 << SDMMC_STATUS_RESPINDEX_SHIFT)
|
||||
#define SDMMC_STATUS_FIFOCOUNT_SHIFT (17) /* Bits 17-29: FIFO count */
|
||||
#define SDMMC_STATUS_FIFOCOUNT_MASK (0x1fff << SDMMC_STATUS_FIFOCOUNT_SHIFT)
|
||||
#define SDMMC_STATUS_DMAACK (1 << 30) /* Bit 30: DMA acknowledge signal state */
|
||||
#define SDMMC_STATUS_DMAREQ (1 << 31) /* Bit 31: DMA request signal state */
|
||||
|
||||
/* FIFO threshold register FIFOTH */
|
||||
|
||||
#define SDMMC_FIFOTH_TXWMARK_SHIFT (0) /* Bits 0-11: FIFO threshold level when transmitting */
|
||||
#define SDMMC_FIFOTH_TXWMARK_MASK (0xfff << SDMMC_FIFOTH_TXWMARK_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define SDMMC_FIFOTH_RXWMARK_SHIFT (16) /* Bits 16-27: FIFO threshold level when receiving */
|
||||
#define SDMMC_FIFOTH_RXWMARK_MASK (0xfff << SDMMC_FIFOTH_RXWMARK_SHIFT)
|
||||
#define SDMMC_FIFOTH_DMABURST_SHIFT (28) /* Bits 28-30: Burst size for multiple transaction */
|
||||
#define SDMMC_FIFOTH_DMABURST_MASK (7 << SDMMC_FIFOTH_DMABURST_SHIFT)
|
||||
# define SDMMC_FIFOTH_DMABURST_1XFR (0 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 1 transfer */
|
||||
# define SDMMC_FIFOTH_DMABURST_4XFRS (1 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 4 transfers */
|
||||
# define SDMMC_FIFOTH_DMABURST_8XFRS (2 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 8 transfers */
|
||||
# define SDMMC_FIFOTH_DMABURST_16XFRS (3 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 16 transfers */
|
||||
# define SDMMC_FIFOTH_DMABURST_32XFRS (4 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 32 transfers */
|
||||
# define SDMMC_FIFOTH_DMABURST_64XFRS (5 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 64 transfers */
|
||||
# define SDMMC_FIFOTH_DMABURST_128XFRS (6 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 128 transfers */
|
||||
# define SDMMC_FIFOTH_DMABURST_256XFRS (7 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 256 transfers */
|
||||
/* Bit 31: Reserved */
|
||||
/* Card detect register CDETECT */
|
||||
|
||||
#define SDMMC_CDETECT_NOTPRESENT (1 << 0) /* Bit 0: Card detect */
|
||||
/* Bit 1-31: Reserved */
|
||||
/* Write protect register WRTPRT */
|
||||
|
||||
#define SDMMC_WRTPRT_PROTECTED (1 << 0) /* Bit 0: Write protect */
|
||||
/* Bit 1-31: Reserved */
|
||||
/* Debounce count register */
|
||||
|
||||
#define SDMMC_DEBNCE_MASK 0x00ffffff /* Bits 0-23: Debounce count */
|
||||
/* Bit 24-31: Reserved */
|
||||
|
||||
/* Hardware Reset */
|
||||
#define SDMMC_RSTN (1 << 0) /* Bit 0: Hardware reset */
|
||||
/* Bit 1-31: Reserved */
|
||||
|
||||
/* Bus Mode Register */
|
||||
|
||||
#define SDMMC_BMOD_SWR (1 << 0) /* Bit 0: Software Reset */
|
||||
#define SDMMC_BMOD_FB (1 << 1) /* Bit 1: Fixed Burst */
|
||||
#define SDMMC_BMOD_DSL_SHIFT (2) /* Bits 2-6: Descriptor Skip Length */
|
||||
#define SDMMC_BMOD_DSL_MASK (31 << SDMMC_BMOD_DSL_SHIFT)
|
||||
#define SDMMC_BMOD_DE (1 << 7) /* Bit 7: SD/MMC DMA Enable */
|
||||
#define SDMMC_BMOD_PBL_SHIFT (8) /* Bits 8-10: Programmable Burst Length */
|
||||
#define SDMMC_BMOD_PBL_MASK (7 << SDMMC_BMOD_PBL_SHIFT)
|
||||
# define SDMMC_BMOD_PBL_1XFRS (0 << SDMMC_BMOD_PBL_SHIFT) /* 1 transfer */
|
||||
# define SDMMC_BMOD_PBL_4XFRS (1 << SDMMC_BMOD_PBL_SHIFT) /* 4 transfers */
|
||||
# define SDMMC_BMOD_PBL_8XFRS (2 << SDMMC_BMOD_PBL_SHIFT) /* 8 transfers */
|
||||
# define SDMMC_BMOD_PBL_16XFRS (3 << SDMMC_BMOD_PBL_SHIFT) /* 16 transfers */
|
||||
# define SDMMC_BMOD_PBL_32XFRS (4 << SDMMC_BMOD_PBL_SHIFT) /* 32 transfers */
|
||||
# define SDMMC_BMOD_PBL_64XFRS (5 << SDMMC_BMOD_PBL_SHIFT) /* 64 transfers */
|
||||
# define SDMMC_BMOD_PBL_128XFRS (6 << SDMMC_BMOD_PBL_SHIFT) /* 128 transfers */
|
||||
# define SDMMC_BMOD_PBL_256XFRS (7 << SDMMC_BMOD_PBL_SHIFT) /* 256 transfers */
|
||||
/* Bits 11-31: Reserved */
|
||||
/* Internal DMAC Status Register */
|
||||
|
||||
#define SDMMC_IDSTS_TI (1 << 0) /* Bit 0: Transmit Interrupt */
|
||||
#define SDMMC_IDSTS_RI (1 << 1) /* Bit 1: Receive Interrupt */
|
||||
#define SDMMC_IDSTS_FBE (1 << 2) /* Bit 2: Fatal Bus Error Interrupt */
|
||||
/* Bit 3: Reserved */
|
||||
#define SDMMC_IDSTS_DU (1 << 4) /* Bit 4: Descriptor Unavailable Interrupt */
|
||||
#define SDMMC_IDSTS_CES (1 << 5) /* Bit 5: Card Error Summary */
|
||||
/* Bits 6-7: Reserved */
|
||||
#define SDMMC_IDSTS_NIS (1 << 8) /* Bit 8: Normal Interrupt Summary */
|
||||
#define SDMMC_IDSTS_AIS (1 << 9) /* Bit 9: Abnormal Interrupt Summary */
|
||||
#define SDMMC_IDSTS_EB_SHIFT (10) /* Bits 10-12: Error Bits */
|
||||
#define SDMMC_IDSTS_EB_MASK (7 << SDMMC_IDSTS_EB_SHIFT)
|
||||
# define SDMMC_IDSTS_EB_TXHABORT (1 << SDMMC_IDSTS_EB_SHIFT) /* Host Abort received during transmission */
|
||||
# define SDMMC_IDSTS_EB_RXHABORT (2 << SDMMC_IDSTS_EB_SHIFT) /* Host Abort received during reception */
|
||||
#define SDMMC_IDSTS_FSM_SHIFT (13) /* Bits 13-16: DMAC state machine present state */
|
||||
#define SDMMC_IDSTS_FSM_MASK (15 << SDMMC_IDSTS_FSM_SHIFT)
|
||||
# define SDMMC_IDSTS_FSM_DMAIDLE (0 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_IDLE*/
|
||||
# define SDMMC_IDSTS_FSM_DMASUSP (1 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_SUSPEND */
|
||||
# define SDMMC_IDSTS_FSM_DESCRD (2 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_RD */
|
||||
# define SDMMC_IDSTS_FSM_DESCCHK (3 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_CHK */
|
||||
# define SDMMC_IDSTS_FSM_DMARDREQW (4 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_RD_REQ_WAIT */
|
||||
# define SDMMC_IDSTS_FSM_DMAWRREQW (5 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_WR_REQ_WAIT */
|
||||
# define SDMMC_IDSTS_FSM_DMARD (6 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_RD */
|
||||
# define SDMMC_IDSTS_FSM_DMAWR (7 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_WR */
|
||||
# define SDMMC_IDSTS_FSM_DMACLOSE (8 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_CLOSE */
|
||||
/* Bits 17-31: Reserved */
|
||||
/* Internal DMAC Interrupt Enable Register */
|
||||
|
||||
#define SDMMC_IDINTEN_
|
||||
#define SDMMC_IDINTEN_TI (1 << 0) /* Bit 0: Transmit Interrupt */
|
||||
#define SDMMC_IDINTEN_RI (1 << 1) /* Bit 1: Receive Interrupt */
|
||||
#define SDMMC_IDINTEN_FBE (1 << 2) /* Bit 2: Fatal Bus Error Interrupt */
|
||||
/* Bit 3: Reserved */
|
||||
#define SDMMC_IDINTEN_DU (1 << 4) /* Bit 4: Descriptor Unavailable Interrupt */
|
||||
#define SDMMC_IDINTEN_CES (1 << 5) /* Bit 5: Card Error Summary */
|
||||
/* Bits 6-7: Reserved */
|
||||
#define SDMMC_IDINTEN_NIS (1 << 8) /* Bit 8: Normal Interrupt Summary */
|
||||
#define SDMMC_IDINTEN_AIS (1 << 9) /* Bit 9: Abnormal Interrupt Summary */
|
||||
/* Bits 10-31: Reserved */
|
||||
|
||||
/************************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************************/
|
||||
|
||||
/************************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************************/
|
||||
|
||||
/************************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SDMMC_H */
|
||||
|
|
@ -1,138 +1,138 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_spi.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_SPI_CR_OFFSET 0x0000 /* Control Register */
|
||||
#define LPC43_SPI_SR_OFFSET 0x0004 /* SPI Status Register */
|
||||
#define LPC43_SPI_DR_OFFSET 0x0008 /* SPI Data Register */
|
||||
#define LPC43_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */
|
||||
#define LPC43_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */
|
||||
#define LPC43_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */
|
||||
#define LPC43_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_SPI_CR (LPC43_SPI_BASE+LPC43_SPI_CR_OFFSET)
|
||||
#define LPC43_SPI_SR (LPC43_SPI_BASE+LPC43_SPI_SR_OFFSET)
|
||||
#define LPC43_SPI_DR (LPC43_SPI_BASE+LPC43_SPI_DR_OFFSET)
|
||||
#define LPC43_SPI_CCR (LPC43_SPI_BASE+LPC43_SPI_CCR_OFFSET)
|
||||
#define LPC43_TCR_CCR (LPC43_SPI_BASE+LPC43_SPI_TCR_OFFSET)
|
||||
#define LPC43_TSR_CCR (LPC43_SPI_BASE+LPC43_SPI_TSR_OFFSET)
|
||||
#define LPC43_SPI_INT (LPC43_SPI_BASE+LPC43_SPI_INT_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Control Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */
|
||||
#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */
|
||||
#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */
|
||||
#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */
|
||||
#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */
|
||||
#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */
|
||||
#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */
|
||||
#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT)
|
||||
# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */
|
||||
# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */
|
||||
# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */
|
||||
# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */
|
||||
# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */
|
||||
# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */
|
||||
# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */
|
||||
# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */
|
||||
# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* SPI Status Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */
|
||||
#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */
|
||||
#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */
|
||||
#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */
|
||||
#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Data Register */
|
||||
|
||||
#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */
|
||||
#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Clock Counter Register */
|
||||
|
||||
#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Test Control Register */
|
||||
/* Bit 0: Reserved */
|
||||
#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */
|
||||
#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Test Status Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */
|
||||
#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */
|
||||
#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */
|
||||
#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */
|
||||
#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Interrupt Register */
|
||||
|
||||
#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_spi.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_SPI_CR_OFFSET 0x0000 /* Control Register */
|
||||
#define LPC43_SPI_SR_OFFSET 0x0004 /* SPI Status Register */
|
||||
#define LPC43_SPI_DR_OFFSET 0x0008 /* SPI Data Register */
|
||||
#define LPC43_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */
|
||||
#define LPC43_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */
|
||||
#define LPC43_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */
|
||||
#define LPC43_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_SPI_CR (LPC43_SPI_BASE+LPC43_SPI_CR_OFFSET)
|
||||
#define LPC43_SPI_SR (LPC43_SPI_BASE+LPC43_SPI_SR_OFFSET)
|
||||
#define LPC43_SPI_DR (LPC43_SPI_BASE+LPC43_SPI_DR_OFFSET)
|
||||
#define LPC43_SPI_CCR (LPC43_SPI_BASE+LPC43_SPI_CCR_OFFSET)
|
||||
#define LPC43_TCR_CCR (LPC43_SPI_BASE+LPC43_SPI_TCR_OFFSET)
|
||||
#define LPC43_TSR_CCR (LPC43_SPI_BASE+LPC43_SPI_TSR_OFFSET)
|
||||
#define LPC43_SPI_INT (LPC43_SPI_BASE+LPC43_SPI_INT_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Control Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */
|
||||
#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */
|
||||
#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */
|
||||
#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */
|
||||
#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */
|
||||
#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */
|
||||
#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */
|
||||
#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT)
|
||||
# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */
|
||||
# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */
|
||||
# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */
|
||||
# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */
|
||||
# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */
|
||||
# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */
|
||||
# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */
|
||||
# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */
|
||||
# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* SPI Status Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */
|
||||
#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */
|
||||
#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */
|
||||
#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */
|
||||
#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Data Register */
|
||||
|
||||
#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */
|
||||
#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Clock Counter Register */
|
||||
|
||||
#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Test Control Register */
|
||||
/* Bit 0: Reserved */
|
||||
#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */
|
||||
#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Test Status Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */
|
||||
#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */
|
||||
#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */
|
||||
#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */
|
||||
#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SPI Interrupt Register */
|
||||
|
||||
#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H */
|
||||
|
|
|
|||
|
|
@ -1,171 +1,171 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_ssp.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* 8 frame FIFOs for both transmit and receive */
|
||||
|
||||
#define LPC43_SSP_FIFOSZ 8
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */
|
||||
#define LPC43_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */
|
||||
#define LPC43_SSP_DR_OFFSET 0x0008 /* Data Register */
|
||||
#define LPC43_SSP_SR_OFFSET 0x000c /* Status Register */
|
||||
#define LPC43_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */
|
||||
#define LPC43_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set and Clear Register */
|
||||
#define LPC43_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */
|
||||
#define LPC43_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */
|
||||
#define LPC43_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */
|
||||
#define LPC43_SSP_DMACR_OFFSET 0x0024 /* DMA Control Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_SSP0_CR0 (LPC43_SSP0_BASE+LPC43_SSP_CR0_OFFSET)
|
||||
#define LPC43_SSP0_CR1 (LPC43_SSP0_BASE+LPC43_SSP_CR1_OFFSET)
|
||||
#define LPC43_SSP0_DR (LPC43_SSP0_BASE+LPC43_SSP_DR_OFFSET)
|
||||
#define LPC43_SSP0_SR (LPC43_SSP0_BASE+LPC43_SSP_SR_OFFSET)
|
||||
#define LPC43_SSP0_CPSR (LPC43_SSP0_BASE+LPC43_SSP_CPSR_OFFSET)
|
||||
#define LPC43_SSP0_IMSC (LPC43_SSP0_BASE+LPC43_SSP_IMSC_OFFSET)
|
||||
#define LPC43_SSP0_RIS (LPC43_SSP0_BASE+LPC43_SSP_RIS_OFFSET)
|
||||
#define LPC43_SSP0_MIS (LPC43_SSP0_BASE+LPC43_SSP_MIS_OFFSET)
|
||||
#define LPC43_SSP0_ICR (LPC43_SSP0_BASE+LPC43_SSP_ICR_OFFSET)
|
||||
#define LPC43_SSP0_DMACR (LPC43_SSP0_BASE+LPC43_SSP_DMACR_OFFSET)
|
||||
|
||||
#define LPC43_SSP1_CR0 (LPC43_SSP1_BASE+LPC43_SSP_CR0_OFFSET)
|
||||
#define LPC43_SSP1_CR1 (LPC43_SSP1_BASE+LPC43_SSP_CR1_OFFSET)
|
||||
#define LPC43_SSP1_DR (LPC43_SSP1_BASE+LPC43_SSP_DR_OFFSET)
|
||||
#define LPC43_SSP1_SR (LPC43_SSP1_BASE+LPC43_SSP_SR_OFFSET)
|
||||
#define LPC43_SSP1_CPSR (LPC43_SSP1_BASE+LPC43_SSP_CPSR_OFFSET)
|
||||
#define LPC43_SSP1_IMSC (LPC43_SSP1_BASE+LPC43_SSP_IMSC_OFFSET)
|
||||
#define LPC43_SSP1_RIS (LPC43_SSP1_BASE+LPC43_SSP_RIS_OFFSET)
|
||||
#define LPC43_SSP1_MIS (LPC43_SSP1_BASE+LPC43_SSP_MIS_OFFSET)
|
||||
#define LPC43_SSP1_ICR (LPC43_SSP1_BASE+LPC43_SSP_ICR_OFFSET)
|
||||
#define LPC43_SSP1_DMACR (LPC43_SSP1_BASE+LPC43_SSP_DMACR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Control Register 0 */
|
||||
|
||||
#define SSP_CR0_DSS_SHIFT (0) /* Bits 0-3: DSS Data Size Select */
|
||||
#define SSP_CR0_DSS_MASK (15 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_10BIT (9 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_11BIT (10 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_12BIT (11 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_13BIT (12 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_14BIT (13 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_15BIT (14 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_16BIT (15 << SSP_CR0_DSS_SHIFT)
|
||||
#define SSP_CR0_FRF_SHIFT (4) /* Bits 4-5: FRF Frame Format */
|
||||
#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_UWIRE (2 << SSP_CR0_FRF_SHIFT)
|
||||
#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock Out Polarity */
|
||||
#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock Out Phase */
|
||||
#define SSP_CR0_SCR_SHIFT (8) /* Bits 8-15: Serial Clock Rate */
|
||||
#define SSP_CR0_SCR_MASK (0xff << SSP_CR0_SCR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Control Register 1 */
|
||||
|
||||
#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */
|
||||
#define SSP_CR1_SSE (1 << 1) /* Bit 1: SSP Enable */
|
||||
#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */
|
||||
#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* Data Register */
|
||||
|
||||
#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Status Register */
|
||||
|
||||
#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */
|
||||
#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */
|
||||
#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */
|
||||
#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */
|
||||
#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */
|
||||
/* Bits 5-31: Reserved */
|
||||
/* Clock Prescale Register */
|
||||
|
||||
#define SSP_CPSR_DVSR_MASK (0xff) /* Bits 0-7: clock = SSP_PCLK/DVSR */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Common format for interrupt control registers:
|
||||
*
|
||||
* Interrupt Mask Set and Clear Register (IMSC)
|
||||
* Raw Interrupt Status Register (RIS)
|
||||
* Masked Interrupt Status Register (MIS)
|
||||
* Interrupt Clear Register (ICR)
|
||||
*/
|
||||
|
||||
#define SSP_INT_ROR (1 << 0) /* Bit 0: RX FIFO overrun */
|
||||
#define SSP_INT_RT (1 << 1) /* Bit 1: RX FIFO timeout */
|
||||
#define SSP_INT_RX (1 << 2) /* Bit 2: RX FIFO at least half full (not ICR) */
|
||||
#define SSP_INT_TX (1 << 3 ) /* Bit 3: TX FIFO at least half empy (not ICR) */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* DMA Control Register */
|
||||
|
||||
#define SSP_DMACR_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */
|
||||
#define SSP_DMACR_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_ssp.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* 8 frame FIFOs for both transmit and receive */
|
||||
|
||||
#define LPC43_SSP_FIFOSZ 8
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */
|
||||
#define LPC43_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */
|
||||
#define LPC43_SSP_DR_OFFSET 0x0008 /* Data Register */
|
||||
#define LPC43_SSP_SR_OFFSET 0x000c /* Status Register */
|
||||
#define LPC43_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */
|
||||
#define LPC43_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set and Clear Register */
|
||||
#define LPC43_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */
|
||||
#define LPC43_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */
|
||||
#define LPC43_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */
|
||||
#define LPC43_SSP_DMACR_OFFSET 0x0024 /* DMA Control Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_SSP0_CR0 (LPC43_SSP0_BASE+LPC43_SSP_CR0_OFFSET)
|
||||
#define LPC43_SSP0_CR1 (LPC43_SSP0_BASE+LPC43_SSP_CR1_OFFSET)
|
||||
#define LPC43_SSP0_DR (LPC43_SSP0_BASE+LPC43_SSP_DR_OFFSET)
|
||||
#define LPC43_SSP0_SR (LPC43_SSP0_BASE+LPC43_SSP_SR_OFFSET)
|
||||
#define LPC43_SSP0_CPSR (LPC43_SSP0_BASE+LPC43_SSP_CPSR_OFFSET)
|
||||
#define LPC43_SSP0_IMSC (LPC43_SSP0_BASE+LPC43_SSP_IMSC_OFFSET)
|
||||
#define LPC43_SSP0_RIS (LPC43_SSP0_BASE+LPC43_SSP_RIS_OFFSET)
|
||||
#define LPC43_SSP0_MIS (LPC43_SSP0_BASE+LPC43_SSP_MIS_OFFSET)
|
||||
#define LPC43_SSP0_ICR (LPC43_SSP0_BASE+LPC43_SSP_ICR_OFFSET)
|
||||
#define LPC43_SSP0_DMACR (LPC43_SSP0_BASE+LPC43_SSP_DMACR_OFFSET)
|
||||
|
||||
#define LPC43_SSP1_CR0 (LPC43_SSP1_BASE+LPC43_SSP_CR0_OFFSET)
|
||||
#define LPC43_SSP1_CR1 (LPC43_SSP1_BASE+LPC43_SSP_CR1_OFFSET)
|
||||
#define LPC43_SSP1_DR (LPC43_SSP1_BASE+LPC43_SSP_DR_OFFSET)
|
||||
#define LPC43_SSP1_SR (LPC43_SSP1_BASE+LPC43_SSP_SR_OFFSET)
|
||||
#define LPC43_SSP1_CPSR (LPC43_SSP1_BASE+LPC43_SSP_CPSR_OFFSET)
|
||||
#define LPC43_SSP1_IMSC (LPC43_SSP1_BASE+LPC43_SSP_IMSC_OFFSET)
|
||||
#define LPC43_SSP1_RIS (LPC43_SSP1_BASE+LPC43_SSP_RIS_OFFSET)
|
||||
#define LPC43_SSP1_MIS (LPC43_SSP1_BASE+LPC43_SSP_MIS_OFFSET)
|
||||
#define LPC43_SSP1_ICR (LPC43_SSP1_BASE+LPC43_SSP_ICR_OFFSET)
|
||||
#define LPC43_SSP1_DMACR (LPC43_SSP1_BASE+LPC43_SSP_DMACR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Control Register 0 */
|
||||
|
||||
#define SSP_CR0_DSS_SHIFT (0) /* Bits 0-3: DSS Data Size Select */
|
||||
#define SSP_CR0_DSS_MASK (15 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_10BIT (9 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_11BIT (10 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_12BIT (11 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_13BIT (12 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_14BIT (13 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_15BIT (14 << SSP_CR0_DSS_SHIFT)
|
||||
# define SSP_CR0_DSS_16BIT (15 << SSP_CR0_DSS_SHIFT)
|
||||
#define SSP_CR0_FRF_SHIFT (4) /* Bits 4-5: FRF Frame Format */
|
||||
#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_UWIRE (2 << SSP_CR0_FRF_SHIFT)
|
||||
#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock Out Polarity */
|
||||
#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock Out Phase */
|
||||
#define SSP_CR0_SCR_SHIFT (8) /* Bits 8-15: Serial Clock Rate */
|
||||
#define SSP_CR0_SCR_MASK (0xff << SSP_CR0_SCR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Control Register 1 */
|
||||
|
||||
#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */
|
||||
#define SSP_CR1_SSE (1 << 1) /* Bit 1: SSP Enable */
|
||||
#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */
|
||||
#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* Data Register */
|
||||
|
||||
#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Status Register */
|
||||
|
||||
#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */
|
||||
#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */
|
||||
#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */
|
||||
#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */
|
||||
#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */
|
||||
/* Bits 5-31: Reserved */
|
||||
/* Clock Prescale Register */
|
||||
|
||||
#define SSP_CPSR_DVSR_MASK (0xff) /* Bits 0-7: clock = SSP_PCLK/DVSR */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Common format for interrupt control registers:
|
||||
*
|
||||
* Interrupt Mask Set and Clear Register (IMSC)
|
||||
* Raw Interrupt Status Register (RIS)
|
||||
* Masked Interrupt Status Register (MIS)
|
||||
* Interrupt Clear Register (ICR)
|
||||
*/
|
||||
|
||||
#define SSP_INT_ROR (1 << 0) /* Bit 0: RX FIFO overrun */
|
||||
#define SSP_INT_RT (1 << 1) /* Bit 1: RX FIFO timeout */
|
||||
#define SSP_INT_RX (1 << 2) /* Bit 2: RX FIFO at least half full (not ICR) */
|
||||
#define SSP_INT_TX (1 << 3 ) /* Bit 3: TX FIFO at least half empy (not ICR) */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* DMA Control Register */
|
||||
|
||||
#define SSP_DMACR_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */
|
||||
#define SSP_DMACR_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H */
|
||||
|
|
|
|||
|
|
@ -1,272 +1,272 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_timer.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lpc43_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_TMR_IR_OFFSET 0x0000 /* Interrupt Register */
|
||||
#define LPC43_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */
|
||||
#define LPC43_TMR_TC_OFFSET 0x0008 /* Timer Counter */
|
||||
#define LPC43_TMR_PR_OFFSET 0x000c /* Prescale Register */
|
||||
#define LPC43_TMR_PC_OFFSET 0x0010 /* Prescale Counter */
|
||||
#define LPC43_TMR_MCR_OFFSET 0x0014 /* Match Control Register */
|
||||
#define LPC43_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */
|
||||
#define LPC43_TMR_MR1_OFFSET 0x001c /* Match Register 1 */
|
||||
#define LPC43_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */
|
||||
#define LPC43_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */
|
||||
#define LPC43_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */
|
||||
#define LPC43_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */
|
||||
#define LPC43_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */
|
||||
#define LPC43_TMR_CR2_OFFSET 0x0034 /* Capture Register 2 */
|
||||
#define LPC43_TMR_CR3_OFFSET 0x0038 /* Capture Register 3 */
|
||||
#define LPC43_TMR_EMR_OFFSET 0x003c /* External Match Register */
|
||||
#define LPC43_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_TMR0_IR (LPC43_TMR0_BASE+LPC43_TMR_IR_OFFSET)
|
||||
#define LPC43_TMR0_TCR (LPC43_TMR0_BASE+LPC43_TMR_TCR_OFFSET)
|
||||
#define LPC43_TMR0_TC (LPC43_TMR0_BASE+LPC43_TMR_TC_OFFSET)
|
||||
#define LPC43_TMR0_PR (LPC43_TMR0_BASE+LPC43_TMR_PR_OFFSET)
|
||||
#define LPC43_TMR0_PC (LPC43_TMR0_BASE+LPC43_TMR_PC_OFFSET)
|
||||
#define LPC43_TMR0_MCR (LPC43_TMR0_BASE+LPC43_TMR_MCR_OFFSET)
|
||||
#define LPC43_TMR0_MR0 (LPC43_TMR0_BASE+LPC43_TMR_MR0_OFFSET)
|
||||
#define LPC43_TMR0_MR1 (LPC43_TMR0_BASE+LPC43_TMR_MR1_OFFSET)
|
||||
#define LPC43_TMR0_MR2 (LPC43_TMR0_BASE+LPC43_TMR_MR2_OFFSET)
|
||||
#define LPC43_TMR0_MR3 (LPC43_TMR0_BASE+LPC43_TMR_MR3_OFFSET)
|
||||
#define LPC43_TMR0_CCR (LPC43_TMR0_BASE+LPC43_TMR_CCR_OFFSET)
|
||||
#define LPC43_TMR0_CR0 (LPC43_TMR0_BASE+LPC43_TMR_CR0_OFFSET)
|
||||
#define LPC43_TMR0_CR1 (LPC43_TMR0_BASE+LPC43_TMR_CR1_OFFSET)
|
||||
#define LPC43_TMR0_CR2 (LPC43_TMR0_BASE+LPC43_TMR_CR2_OFFSET)
|
||||
#define LPC43_TMR0_CR3 (LPC43_TMR0_BASE+LPC43_TMR_CR3_OFFSET)
|
||||
#define LPC43_TMR0_EMR (LPC43_TMR0_BASE+LPC43_TMR_EMR_OFFSET)
|
||||
#define LPC43_TMR0_CTCR (LPC43_TMR0_BASE+LPC43_TMR_CTCR_OFFSET)
|
||||
|
||||
#define LPC43_TMR1_IR (LPC43_TMR1_BASE+LPC43_TMR_IR_OFFSET)
|
||||
#define LPC43_TMR1_TCR (LPC43_TMR1_BASE+LPC43_TMR_TCR_OFFSET)
|
||||
#define LPC43_TMR1_TC (LPC43_TMR1_BASE+LPC43_TMR_TC_OFFSET)
|
||||
#define LPC43_TMR1_PR (LPC43_TMR1_BASE+LPC43_TMR_PR_OFFSET)
|
||||
#define LPC43_TMR1_PC (LPC43_TMR1_BASE+LPC43_TMR_PC_OFFSET)
|
||||
#define LPC43_TMR1_MCR (LPC43_TMR1_BASE+LPC43_TMR_MCR_OFFSET)
|
||||
#define LPC43_TMR1_MR0 (LPC43_TMR1_BASE+LPC43_TMR_MR0_OFFSET)
|
||||
#define LPC43_TMR1_MR1 (LPC43_TMR1_BASE+LPC43_TMR_MR1_OFFSET)
|
||||
#define LPC43_TMR1_MR2 (LPC43_TMR1_BASE+LPC43_TMR_MR2_OFFSET)
|
||||
#define LPC43_TMR1_MR3 (LPC43_TMR1_BASE+LPC43_TMR_MR3_OFFSET)
|
||||
#define LPC43_TMR1_CCR (LPC43_TMR1_BASE+LPC43_TMR_CCR_OFFSET)
|
||||
#define LPC43_TMR1_CR0 (LPC43_TMR1_BASE+LPC43_TMR_CR0_OFFSET)
|
||||
#define LPC43_TMR1_CR1 (LPC43_TMR1_BASE+LPC43_TMR_CR1_OFFSET)
|
||||
#define LPC43_TMR1_CR2 (LPC43_TMR1_BASE+LPC43_TMR_CR2_OFFSET)
|
||||
#define LPC43_TMR1_CR3 (LPC43_TMR1_BASE+LPC43_TMR_CR3_OFFSET)
|
||||
#define LPC43_TMR1_EMR (LPC43_TMR1_BASE+LPC43_TMR_EMR_OFFSET)
|
||||
#define LPC43_TMR1_CTCR (LPC43_TMR1_BASE+LPC43_TMR_CTCR_OFFSET)
|
||||
|
||||
#define LPC43_TMR2_IR (LPC43_TMR2_BASE+LPC43_TMR_IR_OFFSET)
|
||||
#define LPC43_TMR2_TCR (LPC43_TMR2_BASE+LPC43_TMR_TCR_OFFSET)
|
||||
#define LPC43_TMR2_TC (LPC43_TMR2_BASE+LPC43_TMR_TC_OFFSET)
|
||||
#define LPC43_TMR2_PR (LPC43_TMR2_BASE+LPC43_TMR_PR_OFFSET)
|
||||
#define LPC43_TMR2_PC (LPC43_TMR2_BASE+LPC43_TMR_PC_OFFSET)
|
||||
#define LPC43_TMR2_MCR (LPC43_TMR2_BASE+LPC43_TMR_MCR_OFFSET)
|
||||
#define LPC43_TMR2_MR0 (LPC43_TMR2_BASE+LPC43_TMR_MR0_OFFSET)
|
||||
#define LPC43_TMR2_MR1 (LPC43_TMR2_BASE+LPC43_TMR_MR1_OFFSET)
|
||||
#define LPC43_TMR2_MR2 (LPC43_TMR2_BASE+LPC43_TMR_MR2_OFFSET)
|
||||
#define LPC43_TMR2_MR3 (LPC43_TMR2_BASE+LPC43_TMR_MR3_OFFSET)
|
||||
#define LPC43_TMR2_CCR (LPC43_TMR2_BASE+LPC43_TMR_CCR_OFFSET)
|
||||
#define LPC43_TMR2_CR0 (LPC43_TMR2_BASE+LPC43_TMR_CR0_OFFSET)
|
||||
#define LPC43_TMR2_CR1 (LPC43_TMR2_BASE+LPC43_TMR_CR1_OFFSET)
|
||||
#define LPC43_TMR2_CR2 (LPC43_TMR2_BASE+LPC43_TMR_CR2_OFFSET)
|
||||
#define LPC43_TMR2_CR3 (LPC43_TMR2_BASE+LPC43_TMR_CR3_OFFSET)
|
||||
#define LPC43_TMR2_EMR (LPC43_TMR2_BASE+LPC43_TMR_EMR_OFFSET)
|
||||
#define LPC43_TMR2_CTCR (LPC43_TMR2_BASE+LPC43_TMR_CTCR_OFFSET)
|
||||
|
||||
#define LPC43_TMR3_IR (LPC43_TMR3_BASE+LPC43_TMR_IR_OFFSET)
|
||||
#define LPC43_TMR3_TCR (LPC43_TMR3_BASE+LPC43_TMR_TCR_OFFSET)
|
||||
#define LPC43_TMR3_TC (LPC43_TMR3_BASE+LPC43_TMR_TC_OFFSET)
|
||||
#define LPC43_TMR3_PR (LPC43_TMR3_BASE+LPC43_TMR_PR_OFFSET)
|
||||
#define LPC43_TMR3_PC (LPC43_TMR3_BASE+LPC43_TMR_PC_OFFSET)
|
||||
#define LPC43_TMR3_MCR (LPC43_TMR3_BASE+LPC43_TMR_MCR_OFFSET)
|
||||
#define LPC43_TMR3_MR0 (LPC43_TMR3_BASE+LPC43_TMR_MR0_OFFSET)
|
||||
#define LPC43_TMR3_MR1 (LPC43_TMR3_BASE+LPC43_TMR_MR1_OFFSET)
|
||||
#define LPC43_TMR3_MR2 (LPC43_TMR3_BASE+LPC43_TMR_MR2_OFFSET)
|
||||
#define LPC43_TMR3_MR3 (LPC43_TMR3_BASE+LPC43_TMR_MR3_OFFSET)
|
||||
#define LPC43_TMR3_CCR (LPC43_TMR3_BASE+LPC43_TMR_CCR_OFFSET)
|
||||
#define LPC43_TMR3_CR0 (LPC43_TMR3_BASE+LPC43_TMR_CR0_OFFSET)
|
||||
#define LPC43_TMR3_CR1 (LPC43_TMR3_BASE+LPC43_TMR_CR1_OFFSET)
|
||||
#define LPC43_TMR3_CR2 (LPC43_TMR3_BASE+LPC43_TMR_CR2_OFFSET)
|
||||
#define LPC43_TMR3_CR3 (LPC43_TMR3_BASE+LPC43_TMR_CR3_OFFSET)
|
||||
#define LPC43_TMR3_EMR (LPC43_TMR3_BASE+LPC43_TMR_EMR_OFFSET)
|
||||
#define LPC43_TMR3_CTCR (LPC43_TMR3_BASE+LPC43_TMR_CTCR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Registers holding 32-bit numeric values (no bit field definitions):
|
||||
*
|
||||
* Timer Counter (TC)
|
||||
* Prescale Register (PR)
|
||||
* Prescale Counter (PC)
|
||||
* Match Register 0 (MR0)
|
||||
* Match Register 1 (MR1)
|
||||
* Match Register 2 (MR2)
|
||||
* Match Register 3 (MR3)
|
||||
* Capture Register 0 (CR0)
|
||||
* Capture Register 1 (CR1)
|
||||
* Capture Register 2 (CR2)
|
||||
* Capture Register 3 (CR3)
|
||||
*/
|
||||
|
||||
/* Interrupt Register */
|
||||
|
||||
#define TMR_IR_MR0 (1 << 0) /* Bit 0: Match channel 0 interrupt */
|
||||
#define TMR_IR_MR1 (1 << 1) /* Bit 1: Match channel 1 interrupt */
|
||||
#define TMR_IR_MR2 (1 << 2) /* Bit 2: Match channel 2 interrupt */
|
||||
#define TMR_IR_MR3 (1 << 3) /* Bit 3: Match channel 3 interrupt */
|
||||
#define TMR_IR_CR0 (1 << 4) /* Bit 4: Capture channel 0 interrupt */
|
||||
#define TMR_IR_CR1 (1 << 5) /* Bit 5: Capture channel 1 interrupt */
|
||||
#define TMR_IR_CR2 (1 << 6) /* Bit 6: Capture channel 2 interrupt */
|
||||
#define TMR_IR_CR3 (1 << 7) /* Bit 7: Capture channel 3 interrupt */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Timer Control Register */
|
||||
|
||||
#define TMR_TCR_EN (1 << 0) /* Bit 0: Counter Enable */
|
||||
#define TMR_TCR_RESET (1 << 1) /* Bit 1: Counter Reset */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* Match Control Register */
|
||||
|
||||
#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */
|
||||
#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */
|
||||
#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */
|
||||
#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */
|
||||
#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */
|
||||
#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */
|
||||
#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */
|
||||
#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */
|
||||
#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */
|
||||
#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */
|
||||
#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */
|
||||
#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Capture Control Register */
|
||||
|
||||
#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */
|
||||
#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg3 */
|
||||
#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */
|
||||
#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */
|
||||
#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg3 */
|
||||
#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */
|
||||
#define TMR_CCR_CAP2RE (1 << 6) /* Bit 6: Capture on CAPn.2 rising edge */
|
||||
#define TMR_CCR_CAP2FE (1 << 7) /* Bit 7: Capture on CAPn.2 falling edg3 */
|
||||
#define TMR_CCR_CAP2I (1 << 8) /* Bit 8: Interrupt on CAPn.2 */
|
||||
#define TMR_CCR_CAP3RE (1 << 9) /* Bit 9: Capture on CAPn.3 rising edge */
|
||||
#define TMR_CCR_CAP3FE (1 << 10) /* Bit 10: Capture on CAPn.3 falling edg3 */
|
||||
#define TMR_CCR_CAP3I (1 << 11) /* Bit 11: Interrupt on CAPn.3 */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* External Match Register */
|
||||
|
||||
#define TMR_EMR_NOTHING (0) /* Do Nothing */
|
||||
#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */
|
||||
#define TMR_EMR_SET (2) /* Set external match bit MATn.m */
|
||||
#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */
|
||||
|
||||
#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */
|
||||
#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */
|
||||
#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */
|
||||
#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */
|
||||
#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */
|
||||
#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy)
|
||||
# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT)
|
||||
#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */
|
||||
#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT)
|
||||
#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */
|
||||
#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT)
|
||||
#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */
|
||||
#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Count Control Register */
|
||||
|
||||
#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */
|
||||
#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT)
|
||||
# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer ModeMode: Rising PCLK edge */
|
||||
# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */
|
||||
# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */
|
||||
# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */
|
||||
#define TMR_CTCR_INSEL_SHIFT (2) /* Bits 2-3: Count Input Select */
|
||||
#define TMR_CTCR_INSEL_MASK (3 << TMR_CTCR_INSEL_SHIFT)
|
||||
# define TMR_CTCR_INSEL_CAPNp0 (0 << TMR_CTCR_INSEL_SHIFT) /* CAPn.0 for TIMERn */
|
||||
# define TMR_CTCR_INSEL_CAPNp1 (1 << TMR_CTCR_INSEL_SHIFT) /* CAPn.1 for TIMERn */
|
||||
# define TMR_CTCR_INSEL_CAPNp2 (2 << TMR_CTCR_INSEL_SHIFT) /* CAPn.2 for TIMERn */
|
||||
# define TMR_CTCR_INSEL_CAPNp3 (3 << TMR_CTCR_INSEL_SHIFT) /* CAPn.3 for TIMERn */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_timer.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "lpc43_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_TMR_IR_OFFSET 0x0000 /* Interrupt Register */
|
||||
#define LPC43_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */
|
||||
#define LPC43_TMR_TC_OFFSET 0x0008 /* Timer Counter */
|
||||
#define LPC43_TMR_PR_OFFSET 0x000c /* Prescale Register */
|
||||
#define LPC43_TMR_PC_OFFSET 0x0010 /* Prescale Counter */
|
||||
#define LPC43_TMR_MCR_OFFSET 0x0014 /* Match Control Register */
|
||||
#define LPC43_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */
|
||||
#define LPC43_TMR_MR1_OFFSET 0x001c /* Match Register 1 */
|
||||
#define LPC43_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */
|
||||
#define LPC43_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */
|
||||
#define LPC43_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */
|
||||
#define LPC43_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */
|
||||
#define LPC43_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */
|
||||
#define LPC43_TMR_CR2_OFFSET 0x0034 /* Capture Register 2 */
|
||||
#define LPC43_TMR_CR3_OFFSET 0x0038 /* Capture Register 3 */
|
||||
#define LPC43_TMR_EMR_OFFSET 0x003c /* External Match Register */
|
||||
#define LPC43_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_TMR0_IR (LPC43_TMR0_BASE+LPC43_TMR_IR_OFFSET)
|
||||
#define LPC43_TMR0_TCR (LPC43_TMR0_BASE+LPC43_TMR_TCR_OFFSET)
|
||||
#define LPC43_TMR0_TC (LPC43_TMR0_BASE+LPC43_TMR_TC_OFFSET)
|
||||
#define LPC43_TMR0_PR (LPC43_TMR0_BASE+LPC43_TMR_PR_OFFSET)
|
||||
#define LPC43_TMR0_PC (LPC43_TMR0_BASE+LPC43_TMR_PC_OFFSET)
|
||||
#define LPC43_TMR0_MCR (LPC43_TMR0_BASE+LPC43_TMR_MCR_OFFSET)
|
||||
#define LPC43_TMR0_MR0 (LPC43_TMR0_BASE+LPC43_TMR_MR0_OFFSET)
|
||||
#define LPC43_TMR0_MR1 (LPC43_TMR0_BASE+LPC43_TMR_MR1_OFFSET)
|
||||
#define LPC43_TMR0_MR2 (LPC43_TMR0_BASE+LPC43_TMR_MR2_OFFSET)
|
||||
#define LPC43_TMR0_MR3 (LPC43_TMR0_BASE+LPC43_TMR_MR3_OFFSET)
|
||||
#define LPC43_TMR0_CCR (LPC43_TMR0_BASE+LPC43_TMR_CCR_OFFSET)
|
||||
#define LPC43_TMR0_CR0 (LPC43_TMR0_BASE+LPC43_TMR_CR0_OFFSET)
|
||||
#define LPC43_TMR0_CR1 (LPC43_TMR0_BASE+LPC43_TMR_CR1_OFFSET)
|
||||
#define LPC43_TMR0_CR2 (LPC43_TMR0_BASE+LPC43_TMR_CR2_OFFSET)
|
||||
#define LPC43_TMR0_CR3 (LPC43_TMR0_BASE+LPC43_TMR_CR3_OFFSET)
|
||||
#define LPC43_TMR0_EMR (LPC43_TMR0_BASE+LPC43_TMR_EMR_OFFSET)
|
||||
#define LPC43_TMR0_CTCR (LPC43_TMR0_BASE+LPC43_TMR_CTCR_OFFSET)
|
||||
|
||||
#define LPC43_TMR1_IR (LPC43_TMR1_BASE+LPC43_TMR_IR_OFFSET)
|
||||
#define LPC43_TMR1_TCR (LPC43_TMR1_BASE+LPC43_TMR_TCR_OFFSET)
|
||||
#define LPC43_TMR1_TC (LPC43_TMR1_BASE+LPC43_TMR_TC_OFFSET)
|
||||
#define LPC43_TMR1_PR (LPC43_TMR1_BASE+LPC43_TMR_PR_OFFSET)
|
||||
#define LPC43_TMR1_PC (LPC43_TMR1_BASE+LPC43_TMR_PC_OFFSET)
|
||||
#define LPC43_TMR1_MCR (LPC43_TMR1_BASE+LPC43_TMR_MCR_OFFSET)
|
||||
#define LPC43_TMR1_MR0 (LPC43_TMR1_BASE+LPC43_TMR_MR0_OFFSET)
|
||||
#define LPC43_TMR1_MR1 (LPC43_TMR1_BASE+LPC43_TMR_MR1_OFFSET)
|
||||
#define LPC43_TMR1_MR2 (LPC43_TMR1_BASE+LPC43_TMR_MR2_OFFSET)
|
||||
#define LPC43_TMR1_MR3 (LPC43_TMR1_BASE+LPC43_TMR_MR3_OFFSET)
|
||||
#define LPC43_TMR1_CCR (LPC43_TMR1_BASE+LPC43_TMR_CCR_OFFSET)
|
||||
#define LPC43_TMR1_CR0 (LPC43_TMR1_BASE+LPC43_TMR_CR0_OFFSET)
|
||||
#define LPC43_TMR1_CR1 (LPC43_TMR1_BASE+LPC43_TMR_CR1_OFFSET)
|
||||
#define LPC43_TMR1_CR2 (LPC43_TMR1_BASE+LPC43_TMR_CR2_OFFSET)
|
||||
#define LPC43_TMR1_CR3 (LPC43_TMR1_BASE+LPC43_TMR_CR3_OFFSET)
|
||||
#define LPC43_TMR1_EMR (LPC43_TMR1_BASE+LPC43_TMR_EMR_OFFSET)
|
||||
#define LPC43_TMR1_CTCR (LPC43_TMR1_BASE+LPC43_TMR_CTCR_OFFSET)
|
||||
|
||||
#define LPC43_TMR2_IR (LPC43_TMR2_BASE+LPC43_TMR_IR_OFFSET)
|
||||
#define LPC43_TMR2_TCR (LPC43_TMR2_BASE+LPC43_TMR_TCR_OFFSET)
|
||||
#define LPC43_TMR2_TC (LPC43_TMR2_BASE+LPC43_TMR_TC_OFFSET)
|
||||
#define LPC43_TMR2_PR (LPC43_TMR2_BASE+LPC43_TMR_PR_OFFSET)
|
||||
#define LPC43_TMR2_PC (LPC43_TMR2_BASE+LPC43_TMR_PC_OFFSET)
|
||||
#define LPC43_TMR2_MCR (LPC43_TMR2_BASE+LPC43_TMR_MCR_OFFSET)
|
||||
#define LPC43_TMR2_MR0 (LPC43_TMR2_BASE+LPC43_TMR_MR0_OFFSET)
|
||||
#define LPC43_TMR2_MR1 (LPC43_TMR2_BASE+LPC43_TMR_MR1_OFFSET)
|
||||
#define LPC43_TMR2_MR2 (LPC43_TMR2_BASE+LPC43_TMR_MR2_OFFSET)
|
||||
#define LPC43_TMR2_MR3 (LPC43_TMR2_BASE+LPC43_TMR_MR3_OFFSET)
|
||||
#define LPC43_TMR2_CCR (LPC43_TMR2_BASE+LPC43_TMR_CCR_OFFSET)
|
||||
#define LPC43_TMR2_CR0 (LPC43_TMR2_BASE+LPC43_TMR_CR0_OFFSET)
|
||||
#define LPC43_TMR2_CR1 (LPC43_TMR2_BASE+LPC43_TMR_CR1_OFFSET)
|
||||
#define LPC43_TMR2_CR2 (LPC43_TMR2_BASE+LPC43_TMR_CR2_OFFSET)
|
||||
#define LPC43_TMR2_CR3 (LPC43_TMR2_BASE+LPC43_TMR_CR3_OFFSET)
|
||||
#define LPC43_TMR2_EMR (LPC43_TMR2_BASE+LPC43_TMR_EMR_OFFSET)
|
||||
#define LPC43_TMR2_CTCR (LPC43_TMR2_BASE+LPC43_TMR_CTCR_OFFSET)
|
||||
|
||||
#define LPC43_TMR3_IR (LPC43_TMR3_BASE+LPC43_TMR_IR_OFFSET)
|
||||
#define LPC43_TMR3_TCR (LPC43_TMR3_BASE+LPC43_TMR_TCR_OFFSET)
|
||||
#define LPC43_TMR3_TC (LPC43_TMR3_BASE+LPC43_TMR_TC_OFFSET)
|
||||
#define LPC43_TMR3_PR (LPC43_TMR3_BASE+LPC43_TMR_PR_OFFSET)
|
||||
#define LPC43_TMR3_PC (LPC43_TMR3_BASE+LPC43_TMR_PC_OFFSET)
|
||||
#define LPC43_TMR3_MCR (LPC43_TMR3_BASE+LPC43_TMR_MCR_OFFSET)
|
||||
#define LPC43_TMR3_MR0 (LPC43_TMR3_BASE+LPC43_TMR_MR0_OFFSET)
|
||||
#define LPC43_TMR3_MR1 (LPC43_TMR3_BASE+LPC43_TMR_MR1_OFFSET)
|
||||
#define LPC43_TMR3_MR2 (LPC43_TMR3_BASE+LPC43_TMR_MR2_OFFSET)
|
||||
#define LPC43_TMR3_MR3 (LPC43_TMR3_BASE+LPC43_TMR_MR3_OFFSET)
|
||||
#define LPC43_TMR3_CCR (LPC43_TMR3_BASE+LPC43_TMR_CCR_OFFSET)
|
||||
#define LPC43_TMR3_CR0 (LPC43_TMR3_BASE+LPC43_TMR_CR0_OFFSET)
|
||||
#define LPC43_TMR3_CR1 (LPC43_TMR3_BASE+LPC43_TMR_CR1_OFFSET)
|
||||
#define LPC43_TMR3_CR2 (LPC43_TMR3_BASE+LPC43_TMR_CR2_OFFSET)
|
||||
#define LPC43_TMR3_CR3 (LPC43_TMR3_BASE+LPC43_TMR_CR3_OFFSET)
|
||||
#define LPC43_TMR3_EMR (LPC43_TMR3_BASE+LPC43_TMR_EMR_OFFSET)
|
||||
#define LPC43_TMR3_CTCR (LPC43_TMR3_BASE+LPC43_TMR_CTCR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Registers holding 32-bit numeric values (no bit field definitions):
|
||||
*
|
||||
* Timer Counter (TC)
|
||||
* Prescale Register (PR)
|
||||
* Prescale Counter (PC)
|
||||
* Match Register 0 (MR0)
|
||||
* Match Register 1 (MR1)
|
||||
* Match Register 2 (MR2)
|
||||
* Match Register 3 (MR3)
|
||||
* Capture Register 0 (CR0)
|
||||
* Capture Register 1 (CR1)
|
||||
* Capture Register 2 (CR2)
|
||||
* Capture Register 3 (CR3)
|
||||
*/
|
||||
|
||||
/* Interrupt Register */
|
||||
|
||||
#define TMR_IR_MR0 (1 << 0) /* Bit 0: Match channel 0 interrupt */
|
||||
#define TMR_IR_MR1 (1 << 1) /* Bit 1: Match channel 1 interrupt */
|
||||
#define TMR_IR_MR2 (1 << 2) /* Bit 2: Match channel 2 interrupt */
|
||||
#define TMR_IR_MR3 (1 << 3) /* Bit 3: Match channel 3 interrupt */
|
||||
#define TMR_IR_CR0 (1 << 4) /* Bit 4: Capture channel 0 interrupt */
|
||||
#define TMR_IR_CR1 (1 << 5) /* Bit 5: Capture channel 1 interrupt */
|
||||
#define TMR_IR_CR2 (1 << 6) /* Bit 6: Capture channel 2 interrupt */
|
||||
#define TMR_IR_CR3 (1 << 7) /* Bit 7: Capture channel 3 interrupt */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Timer Control Register */
|
||||
|
||||
#define TMR_TCR_EN (1 << 0) /* Bit 0: Counter Enable */
|
||||
#define TMR_TCR_RESET (1 << 1) /* Bit 1: Counter Reset */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* Match Control Register */
|
||||
|
||||
#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */
|
||||
#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */
|
||||
#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */
|
||||
#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */
|
||||
#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */
|
||||
#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */
|
||||
#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */
|
||||
#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */
|
||||
#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */
|
||||
#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */
|
||||
#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */
|
||||
#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Capture Control Register */
|
||||
|
||||
#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */
|
||||
#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg3 */
|
||||
#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */
|
||||
#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */
|
||||
#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg3 */
|
||||
#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */
|
||||
#define TMR_CCR_CAP2RE (1 << 6) /* Bit 6: Capture on CAPn.2 rising edge */
|
||||
#define TMR_CCR_CAP2FE (1 << 7) /* Bit 7: Capture on CAPn.2 falling edg3 */
|
||||
#define TMR_CCR_CAP2I (1 << 8) /* Bit 8: Interrupt on CAPn.2 */
|
||||
#define TMR_CCR_CAP3RE (1 << 9) /* Bit 9: Capture on CAPn.3 rising edge */
|
||||
#define TMR_CCR_CAP3FE (1 << 10) /* Bit 10: Capture on CAPn.3 falling edg3 */
|
||||
#define TMR_CCR_CAP3I (1 << 11) /* Bit 11: Interrupt on CAPn.3 */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* External Match Register */
|
||||
|
||||
#define TMR_EMR_NOTHING (0) /* Do Nothing */
|
||||
#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */
|
||||
#define TMR_EMR_SET (2) /* Set external match bit MATn.m */
|
||||
#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */
|
||||
|
||||
#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */
|
||||
#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */
|
||||
#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */
|
||||
#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */
|
||||
#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */
|
||||
#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy)
|
||||
# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT)
|
||||
#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */
|
||||
#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT)
|
||||
#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */
|
||||
#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT)
|
||||
#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */
|
||||
#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Count Control Register */
|
||||
|
||||
#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */
|
||||
#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT)
|
||||
# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer ModeMode: Rising PCLK edge */
|
||||
# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */
|
||||
# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */
|
||||
# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */
|
||||
#define TMR_CTCR_INSEL_SHIFT (2) /* Bits 2-3: Count Input Select */
|
||||
#define TMR_CTCR_INSEL_MASK (3 << TMR_CTCR_INSEL_SHIFT)
|
||||
# define TMR_CTCR_INSEL_CAPNp0 (0 << TMR_CTCR_INSEL_SHIFT) /* CAPn.0 for TIMERn */
|
||||
# define TMR_CTCR_INSEL_CAPNp1 (1 << TMR_CTCR_INSEL_SHIFT) /* CAPn.1 for TIMERn */
|
||||
# define TMR_CTCR_INSEL_CAPNp2 (2 << TMR_CTCR_INSEL_SHIFT) /* CAPn.2 for TIMERn */
|
||||
# define TMR_CTCR_INSEL_CAPNp3 (3 << TMR_CTCR_INSEL_SHIFT) /* CAPn.3 for TIMERn */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H */
|
||||
|
|
|
|||
|
|
@ -1,397 +1,397 @@
|
|||
/********************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_uart.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/* Register offsets *************************************************************************/
|
||||
/* Common Register Offsets */
|
||||
|
||||
#define LPC43_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register */
|
||||
#define LPC43_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register */
|
||||
#define LPC43_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB */
|
||||
#define LPC43_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB */
|
||||
#define LPC43_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register */
|
||||
#define LPC43_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register */
|
||||
#define LPC43_UART_FCR_OFFSET 0x0008 /* FIFO Control Register */
|
||||
#define LPC43_UART_LCR_OFFSET 0x000c /* Line Control Register */
|
||||
#define LPC43_UART_LSR_OFFSET 0x0014 /* Line Status Register */
|
||||
#define LPC43_UART_SCR_OFFSET 0x001c /* Scratch Pad Register */
|
||||
#define LPC43_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register */
|
||||
#define LPC43_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register */
|
||||
|
||||
#define LPC43_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control */
|
||||
#define LPC43_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match */
|
||||
#define LPC43_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay */
|
||||
|
||||
/* Registers available only on UART1 */
|
||||
|
||||
#define LPC43_UART_MCR_OFFSET 0x0010 /* Modem Control Register */
|
||||
#define LPC43_UART_MSR_OFFSET 0x0018 /* Modem Status Register */
|
||||
#define LPC43_UART_TER_OFFSET 0x0030 /* Transmit Enable Register */
|
||||
|
||||
/* Registers available only on USART0,2,3 */
|
||||
|
||||
#define LPC43_USART_ICR_OFFSET 0x0024 /* IrDA Control Register */
|
||||
#define LPC43_USART_OSR_OFFSET 0x002c /* Oversampling Register */
|
||||
#define LPC43_USART_HDEN_OFFSET 0x0040 /* Half-duplex enable Register */
|
||||
#define LPC43_USART_SCICTRL_OFFSET 0x0048 /* Smart card interface control register */
|
||||
#define LPC43_USART_SYNCCTRL_OFFSET 0x0058 /* Synchronous mode control register */
|
||||
#define LPC43_USART_TER_OFFSET 0x005c /* Transmit Enable Register */
|
||||
|
||||
/* Register addresses ***********************************************************************/
|
||||
|
||||
#define LPC43_USART0_RBR (LPC43_USART0_BASE+LPC43_UART_RBR_OFFSET)
|
||||
#define LPC43_USART0_THR (LPC43_USART0_BASE+LPC43_UART_THR_OFFSET)
|
||||
#define LPC43_USART0_DLL (LPC43_USART0_BASE+LPC43_UART_DLL_OFFSET)
|
||||
#define LPC43_USART0_DLM (LPC43_USART0_BASE+LPC43_UART_DLM_OFFSET)
|
||||
#define LPC43_USART0_IER (LPC43_USART0_BASE+LPC43_UART_IER_OFFSET)
|
||||
#define LPC43_USART0_IIR (LPC43_USART0_BASE+LPC43_UART_IIR_OFFSET)
|
||||
#define LPC43_USART0_FCR (LPC43_USART0_BASE+LPC43_UART_FCR_OFFSET)
|
||||
#define LPC43_USART0_LCR (LPC43_USART0_BASE+LPC43_UART_LCR_OFFSET)
|
||||
#define LPC43_USART0_LSR (LPC43_USART0_BASE+LPC43_UART_LSR_OFFSET)
|
||||
#define LPC43_USART0_SCR (LPC43_USART0_BASE+LPC43_UART_SCR_OFFSET)
|
||||
#define LPC43_USART0_ACR (LPC43_USART0_BASE+LPC43_UART_ACR_OFFSET)
|
||||
#define LPC43_USART0_ICR (LPC43_USART0_BASE+LPC43_USART_ICR_OFFSET)
|
||||
#define LPC43_USART0_FDR (LPC43_USART0_BASE+LPC43_UART_FDR_OFFSET)
|
||||
#define LPC43_USART0_OSR (LPC43_USART0_BASE+LPC43_USART_OSR_OFFSET)
|
||||
#define LPC43_USART0_HDEM (LPC43_USART0_BASE+LPC43_USART_HDEN_OFFSET)
|
||||
#define LPC43_USART0_SCICTRL (LPC43_USART0_BASE+LPC43_USART_SCICTRL_OFFSET)
|
||||
#define LPC43_USART0_RS485CTRL (LPC43_USART0_BASE+LPC43_UART_RS485CTRL_OFFSET)
|
||||
#define LPC43_USART0_ADRMATCH (LPC43_USART0_BASE+LPC43_UART_ADRMATCH_OFFSET)
|
||||
#define LPC43_USART0_RS485DLY (LPC43_USART0_BASE+LPC43_UART_RS485DLY_OFFSET)
|
||||
#define LPC43_USART0_SYNCCTRL (LPC43_USART0_BASE+LPC43_USART_SYNCCTRL_OFFSET)
|
||||
#define LPC43_USART0_TER (LPC43_USART0_BASE+LPC43_USART_TER_OFFSET)
|
||||
|
||||
#define LPC43_UART1_RBR (LPC43_UART1_BASE+LPC43_UART_RBR_OFFSET)
|
||||
#define LPC43_UART1_THR (LPC43_UART1_BASE+LPC43_UART_THR_OFFSET)
|
||||
#define LPC43_UART1_DLL (LPC43_UART1_BASE+LPC43_UART_DLL_OFFSET)
|
||||
#define LPC43_UART1_DLM (LPC43_UART1_BASE+LPC43_UART_DLM_OFFSET)
|
||||
#define LPC43_UART1_IER (LPC43_UART1_BASE+LPC43_UART_IER_OFFSET)
|
||||
#define LPC43_UART1_IIR (LPC43_UART1_BASE+LPC43_UART_IIR_OFFSET)
|
||||
#define LPC43_UART1_FCR (LPC43_UART1_BASE+LPC43_UART_FCR_OFFSET)
|
||||
#define LPC43_UART1_LCR (LPC43_UART1_BASE+LPC43_UART_LCR_OFFSET)
|
||||
#define LPC43_UART1_MCR (LPC43_UART1_BASE+LPC43_UART_MCR_OFFSET)
|
||||
#define LPC43_UART1_LSR (LPC43_UART1_BASE+LPC43_UART_LSR_OFFSET)
|
||||
#define LPC43_UART1_MSR (LPC43_UART1_BASE+LPC43_UART_MSR_OFFSET)
|
||||
#define LPC43_UART1_SCR (LPC43_UART1_BASE+LPC43_UART_SCR_OFFSET)
|
||||
#define LPC43_UART1_ACR (LPC43_UART1_BASE+LPC43_UART_ACR_OFFSET)
|
||||
#define LPC43_UART1_FDR (LPC43_UART1_BASE+LPC43_UART_FDR_OFFSET)
|
||||
#define LPC43_UART1_TER (LPC43_UART1_BASE+LPC43_UART_TER_OFFSET)
|
||||
#define LPC43_UART1_RS485CTRL (LPC43_UART1_BASE+LPC43_UART_RS485CTRL_OFFSET)
|
||||
#define LPC43_UART1_ADRMATCH (LPC43_UART1_BASE+LPC43_UART_ADRMATCH_OFFSET)
|
||||
#define LPC43_UART1_RS485DLY (LPC43_UART1_BASE+LPC43_UART_RS485DLY_OFFSET)
|
||||
|
||||
#define LPC43_USART1_RBR (LPC43_USART1_BASE+LPC43_UART_RBR_OFFSET)
|
||||
#define LPC43_USART1_THR (LPC43_USART1_BASE+LPC43_UART_THR_OFFSET)
|
||||
#define LPC43_USART1_DLL (LPC43_USART1_BASE+LPC43_UART_DLL_OFFSET)
|
||||
#define LPC43_USART1_DLM (LPC43_USART1_BASE+LPC43_UART_DLM_OFFSET)
|
||||
#define LPC43_USART1_IER (LPC43_USART1_BASE+LPC43_UART_IER_OFFSET)
|
||||
#define LPC43_USART1_IIR (LPC43_USART1_BASE+LPC43_UART_IIR_OFFSET)
|
||||
#define LPC43_USART1_FCR (LPC43_USART1_BASE+LPC43_UART_FCR_OFFSET)
|
||||
#define LPC43_USART1_LCR (LPC43_USART1_BASE+LPC43_UART_LCR_OFFSET)
|
||||
#define LPC43_USART1_LSR (LPC43_USART1_BASE+LPC43_UART_LSR_OFFSET)
|
||||
#define LPC43_USART1_SCR (LPC43_USART1_BASE+LPC43_UART_SCR_OFFSET)
|
||||
#define LPC43_USART1_ACR (LPC43_USART1_BASE+LPC43_UART_ACR_OFFSET)
|
||||
#define LPC43_USART1_ICR (LPC43_USART1_BASE+LPC43_USART_ICR_OFFSET)
|
||||
#define LPC43_USART1_FDR (LPC43_USART1_BASE+LPC43_UART_FDR_OFFSET)
|
||||
#define LPC43_USART1_OSR (LPC43_USART1_BASE+LPC43_USART_OSR_OFFSET)
|
||||
#define LPC43_USART1_HDEM (LPC43_USART1_BASE+LPC43_USART_HDEN_OFFSET)
|
||||
#define LPC43_USART1_SCICTRL (LPC43_USART1_BASE+LPC43_USART_SCICTRL_OFFSET)
|
||||
#define LPC43_USART1_RS485CTRL (LPC43_USART1_BASE+LPC43_UART_RS485CTRL_OFFSET)
|
||||
#define LPC43_USART1_ADRMATCH (LPC43_USART1_BASE+LPC43_UART_ADRMATCH_OFFSET)
|
||||
#define LPC43_USART1_RS485DLY (LPC43_USART1_BASE+LPC43_UART_RS485DLY_OFFSET)
|
||||
#define LPC43_USART1_SYNCCTRL (LPC43_USART1_BASE+LPC43_USART_SYNCCTRL_OFFSET)
|
||||
#define LPC43_USART1_TER (LPC43_USART1_BASE+LPC43_USART_TER_OFFSET)
|
||||
|
||||
#define LPC43_USART2_RBR (LPC43_USART2_BASE+LPC43_UART_RBR_OFFSET)
|
||||
#define LPC43_USART2_THR (LPC43_USART2_BASE+LPC43_UART_THR_OFFSET)
|
||||
#define LPC43_USART2_DLL (LPC43_USART2_BASE+LPC43_UART_DLL_OFFSET)
|
||||
#define LPC43_USART2_DLM (LPC43_USART2_BASE+LPC43_UART_DLM_OFFSET)
|
||||
#define LPC43_USART2_IER (LPC43_USART2_BASE+LPC43_UART_IER_OFFSET)
|
||||
#define LPC43_USART2_IIR (LPC43_USART2_BASE+LPC43_UART_IIR_OFFSET)
|
||||
#define LPC43_USART2_FCR (LPC43_USART2_BASE+LPC43_UART_FCR_OFFSET)
|
||||
#define LPC43_USART2_LCR (LPC43_USART2_BASE+LPC43_UART_LCR_OFFSET)
|
||||
#define LPC43_USART2_LSR (LPC43_USART2_BASE+LPC43_UART_LSR_OFFSET)
|
||||
#define LPC43_USART2_SCR (LPC43_USART2_BASE+LPC43_UART_SCR_OFFSET)
|
||||
#define LPC43_USART2_ACR (LPC43_USART2_BASE+LPC43_UART_ACR_OFFSET)
|
||||
#define LPC43_USART2_ICR (LPC43_USART2_BASE+LPC43_USART_ICR_OFFSET)
|
||||
#define LPC43_USART2_FDR (LPC43_USART2_BASE+LPC43_UART_FDR_OFFSET)
|
||||
#define LPC43_USART2_OSR (LPC43_USART2_BASE+LPC43_USART_OSR_OFFSET)
|
||||
#define LPC43_USART2_HDEM (LPC43_USART2_BASE+LPC43_USART_HDEN_OFFSET)
|
||||
#define LPC43_USART2_SCICTRL (LPC43_USART2_BASE+LPC43_USART_SCICTRL_OFFSET)
|
||||
#define LPC43_USART2_RS485CTRL (LPC43_USART2_BASE+LPC43_UART_RS485CTRL_OFFSET)
|
||||
#define LPC43_USART2_ADRMATCH (LPC43_USART2_BASE+LPC43_UART_ADRMATCH_OFFSET)
|
||||
#define LPC43_USART2_RS485DLY (LPC43_USART2_BASE+LPC43_UART_RS485DLY_OFFSET)
|
||||
#define LPC43_USART2_SYNCCTRL (LPC43_USART2_BASE+LPC43_USART_SYNCCTRL_OFFSET)
|
||||
#define LPC43_USART2_TER (LPC43_USART2_BASE+LPC43_USART_TER_OFFSET)
|
||||
|
||||
/* Register bit definitions *****************************************************************/
|
||||
|
||||
/* RBR (DLAB =0) Receiver Buffer Register */
|
||||
|
||||
#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* THR (DLAB =0) Transmit Holding Register */
|
||||
|
||||
#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DLL (DLAB =1) Divisor Latch LSB */
|
||||
|
||||
#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DLM (DLAB =1) Divisor Latch MSB */
|
||||
|
||||
#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* IER (DLAB =0) Interrupt Enable Register */
|
||||
|
||||
#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */
|
||||
#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */
|
||||
#define UART_IER_RXIE (1 << 2) /* Bit 2: RX Line Status Interrupt Enable */
|
||||
#define UART_IER_MSIE (1 << 3) /* Bit 3: Modem Status Interrupt Enable (UART only) */
|
||||
/* Bits 4-6: Reserved */
|
||||
#define UART_IER_CTSIE (1 << 7) /* Bit 7: CTS transition interrupt (UART only) */
|
||||
#define UART_IER_ABEOIE (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */
|
||||
#define UART_IER_ABTOIE (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */
|
||||
/* Bits 10-31: Reserved */
|
||||
#define UART_IER_ALLIE (0x038f)
|
||||
#define USART_IER_ALLIE (0x0307)
|
||||
|
||||
/* IIR Interrupt ID Register */
|
||||
|
||||
#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */
|
||||
#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */
|
||||
#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT)
|
||||
# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART only) */
|
||||
# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */
|
||||
# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */
|
||||
# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */
|
||||
# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */
|
||||
/* Bits 4-5: Reserved */
|
||||
#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR[0] */
|
||||
#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT)
|
||||
#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */
|
||||
#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* FCR FIFO Control Register */
|
||||
|
||||
#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */
|
||||
#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */
|
||||
#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */
|
||||
#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA Mode Select */
|
||||
/* Bits 4-5: Reserved */
|
||||
#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */
|
||||
#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT)
|
||||
# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 char) */
|
||||
# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 chars) */
|
||||
# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 chars) */
|
||||
# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 chars) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* LCR Line Control Register */
|
||||
|
||||
#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */
|
||||
#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT)
|
||||
#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */
|
||||
#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */
|
||||
#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */
|
||||
#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT)
|
||||
# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */
|
||||
# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */
|
||||
# define UART_LCR_PS_STICKY1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */
|
||||
# define UART_LCR_PS_STICKY0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */
|
||||
#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */
|
||||
#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* MCR Modem Control Register (UART only) */
|
||||
|
||||
#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */
|
||||
#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */
|
||||
/* Bit 5: Reserved */
|
||||
#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-RTS flow control */
|
||||
#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-CTS flow control */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* LSR Line Status Register */
|
||||
|
||||
#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */
|
||||
#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */
|
||||
#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
|
||||
#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
|
||||
#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
|
||||
#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
|
||||
#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
|
||||
#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */
|
||||
#define USART_LSR_RXFE (1 << 8) /* Bit 8: Error in transmitted char (USART onlY) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* MSR Modem Status Register (UART only) */
|
||||
|
||||
#define UART_MSR_DCTS (1 << 0) /* Bit 0: Delta CTS. CTS state change */
|
||||
#define UART_MSR_DDSR (1 << 1) /* Bit 1: Delta DSR. DSR state change */
|
||||
#define UART_MSR_TERI (1 << 2) /* Bit 2: Trailing Edge RI */
|
||||
#define UART_MSR_DDCD (1 << 3) /* Bit 3: Delta DCD. DCD state change */
|
||||
#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */
|
||||
#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */
|
||||
#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */
|
||||
#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SCR Scratch Pad Register */
|
||||
|
||||
#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* ACR Auto-baud Control Register */
|
||||
|
||||
#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/
|
||||
#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/
|
||||
#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/
|
||||
/* Bits 3-7: Reserved */
|
||||
#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */
|
||||
#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* ICA IrDA Control Register (UART0,2,3 only) */
|
||||
|
||||
#define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */
|
||||
#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */
|
||||
#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enable IrDA fixed pulse width mode */
|
||||
#define UART_ICR_PULSEDIV_SHIFT (3) /* Bits 3-5: Configures the pulse when FixPulseEn = 1 */
|
||||
#define UART_ICR_PULSEDIV_MASK (7 << UART_ICR_PULSEDIV_SHIFT)
|
||||
# define UART_ICR_PULSEDIV_2TPCLK (0 << UART_ICR_PULSEDIV_SHIFT) /* 2 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_4TPCLK (1 << UART_ICR_PULSEDIV_SHIFT) /* 4 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_8TPCLK (2 << UART_ICR_PULSEDIV_SHIFT) /* 8 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_16TPCLK (3 << UART_ICR_PULSEDIV_SHIFT) /* 16 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_32TPCLK (4 << UART_ICR_PULSEDIV_SHIFT) /* 32 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_64TPCLK (5 << UART_ICR_PULSEDIV_SHIFT) /* 64 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_128TPCLK (6 << UART_ICR_PULSEDIV_SHIFT) /* 128 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_256TPCLK (7 << UART_ICR_PULSEDIV_SHIFT) /* 256 x TPCLK */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* FDR Fractional Divider Register */
|
||||
|
||||
#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */
|
||||
#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT)
|
||||
#define UART_FDR_MULVAL_SHIFT (3) /* Bits 4-7 Baud-rate pre-scaler multiplier value */
|
||||
#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Oversampling Register (USART only) */
|
||||
/* Bit 0: Reserved */
|
||||
#define USART_OSR_OSFRAC_SHIFT (1) /* Bits 1-3: Fractional part of the oversampling ratio */
|
||||
#define USART_OSR_OSFRAC_MASK (7 << USART_OSR_OSFRAC_SHIFT)
|
||||
#define USART_OSR_OSINT_SHIFT (4) /* Bits 4-7: Integer part of the oversampling ratio */
|
||||
#define USART_OSR_OSINT_MASK (15 << USART_OSR_OSINT_SHIFT)
|
||||
#define USART_OSR_FDINT_SHIFT (8) /* Bits 8-14: Extension for Smart Card mode */
|
||||
#define USART_OSR_FDINT_MASK (0x7f << USART_OSR_FDINT_SHIFT)
|
||||
/* Bits 15-31: Reserved */
|
||||
/* TER Transmit Enable Register (UART only) */
|
||||
/* Bits 0-6: Reserved */
|
||||
#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Half-duplex enable Register (USART only) */
|
||||
|
||||
#define USART_HDEN_TXEN (1 << 0) /* Bit 0: Half-duplex mode enable */
|
||||
/* Bits 1-31: Reserved */
|
||||
/* Smart card interface control register (USART only) */
|
||||
|
||||
#define USART_SCICTRL_SCIEN (1 << 0) /* Bit 0: Smart Card Interface Enable */
|
||||
#define USART_SCICTRL_NACKDIS (1 << 1) /* Bit 1: NACK response disable */
|
||||
#define USART_SCICTRL_PROTSEL (1 << 2) /* Bit 2: Protocol selection */
|
||||
/* Bits 3-4: Reserved */
|
||||
#define USART_SCICTRL_TXRETRY_SHIFT (5) /* Bits 5-7: Maximum number of retransmissions */
|
||||
#define USART_SCICTRL_TXRETRY_MASK (7 << USART_SCICTRL_TXRETRY_SHIFT)
|
||||
#define USART_SCICTRL_GUARDTIME_SHIFT (8) /* Bits 8-15: Extra guard time */
|
||||
#define USART_SCICTRL_GUARDTIME_MASK (0xff << USART_SCICTRL_GUARDTIME_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
/* RS-485/EIA-485 Control */
|
||||
|
||||
#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */
|
||||
#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */
|
||||
#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */
|
||||
#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */
|
||||
#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */
|
||||
#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* RS-485/EIA-485 address match */
|
||||
|
||||
#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* RS-485/EIA-485 direction control delay */
|
||||
|
||||
#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Firection control (RTS/DTR) delay */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Synchronous mode control register (USART only) */
|
||||
|
||||
#define USART_SYNCCTRL_SYNC (1 << 0) /* Bit 0: Enables synchronous mode */
|
||||
#define USART_SYNCCTRL_CSRC (1 << 1) /* Bit 1: Clock source select */
|
||||
#define USART_SYNCCTRL_FES (1 << 2) /* Bit 2: Falling edge sampling */
|
||||
#define USART_SYNCCTRL_TSBYPASS (1 << 3) /* Bit 3: Transmit synchronization bypass */
|
||||
#define USART_SYNCCTRL_CSCEN (1 << 4) /* Bit 4: Continuous master clock enable */
|
||||
#define USART_SYNCCTRL_SSSDIS (1 << 5) /* Bit 5: Start/stop bits */
|
||||
#define USART_SYNCCTRL_CCCLR (1 << 6) /* Bit 6: Continuous clock clear */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* TER Transmit Enable Register (USART only) */
|
||||
|
||||
#define USART_TER_TXEN (1 << 0) /* Bit 0: TX Enable */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H */
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_uart.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/* Register offsets *************************************************************************/
|
||||
/* Common Register Offsets */
|
||||
|
||||
#define LPC43_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register */
|
||||
#define LPC43_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register */
|
||||
#define LPC43_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB */
|
||||
#define LPC43_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB */
|
||||
#define LPC43_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register */
|
||||
#define LPC43_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register */
|
||||
#define LPC43_UART_FCR_OFFSET 0x0008 /* FIFO Control Register */
|
||||
#define LPC43_UART_LCR_OFFSET 0x000c /* Line Control Register */
|
||||
#define LPC43_UART_LSR_OFFSET 0x0014 /* Line Status Register */
|
||||
#define LPC43_UART_SCR_OFFSET 0x001c /* Scratch Pad Register */
|
||||
#define LPC43_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register */
|
||||
#define LPC43_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register */
|
||||
|
||||
#define LPC43_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control */
|
||||
#define LPC43_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match */
|
||||
#define LPC43_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay */
|
||||
|
||||
/* Registers available only on UART1 */
|
||||
|
||||
#define LPC43_UART_MCR_OFFSET 0x0010 /* Modem Control Register */
|
||||
#define LPC43_UART_MSR_OFFSET 0x0018 /* Modem Status Register */
|
||||
#define LPC43_UART_TER_OFFSET 0x0030 /* Transmit Enable Register */
|
||||
|
||||
/* Registers available only on USART0,2,3 */
|
||||
|
||||
#define LPC43_USART_ICR_OFFSET 0x0024 /* IrDA Control Register */
|
||||
#define LPC43_USART_OSR_OFFSET 0x002c /* Oversampling Register */
|
||||
#define LPC43_USART_HDEN_OFFSET 0x0040 /* Half-duplex enable Register */
|
||||
#define LPC43_USART_SCICTRL_OFFSET 0x0048 /* Smart card interface control register */
|
||||
#define LPC43_USART_SYNCCTRL_OFFSET 0x0058 /* Synchronous mode control register */
|
||||
#define LPC43_USART_TER_OFFSET 0x005c /* Transmit Enable Register */
|
||||
|
||||
/* Register addresses ***********************************************************************/
|
||||
|
||||
#define LPC43_USART0_RBR (LPC43_USART0_BASE+LPC43_UART_RBR_OFFSET)
|
||||
#define LPC43_USART0_THR (LPC43_USART0_BASE+LPC43_UART_THR_OFFSET)
|
||||
#define LPC43_USART0_DLL (LPC43_USART0_BASE+LPC43_UART_DLL_OFFSET)
|
||||
#define LPC43_USART0_DLM (LPC43_USART0_BASE+LPC43_UART_DLM_OFFSET)
|
||||
#define LPC43_USART0_IER (LPC43_USART0_BASE+LPC43_UART_IER_OFFSET)
|
||||
#define LPC43_USART0_IIR (LPC43_USART0_BASE+LPC43_UART_IIR_OFFSET)
|
||||
#define LPC43_USART0_FCR (LPC43_USART0_BASE+LPC43_UART_FCR_OFFSET)
|
||||
#define LPC43_USART0_LCR (LPC43_USART0_BASE+LPC43_UART_LCR_OFFSET)
|
||||
#define LPC43_USART0_LSR (LPC43_USART0_BASE+LPC43_UART_LSR_OFFSET)
|
||||
#define LPC43_USART0_SCR (LPC43_USART0_BASE+LPC43_UART_SCR_OFFSET)
|
||||
#define LPC43_USART0_ACR (LPC43_USART0_BASE+LPC43_UART_ACR_OFFSET)
|
||||
#define LPC43_USART0_ICR (LPC43_USART0_BASE+LPC43_USART_ICR_OFFSET)
|
||||
#define LPC43_USART0_FDR (LPC43_USART0_BASE+LPC43_UART_FDR_OFFSET)
|
||||
#define LPC43_USART0_OSR (LPC43_USART0_BASE+LPC43_USART_OSR_OFFSET)
|
||||
#define LPC43_USART0_HDEM (LPC43_USART0_BASE+LPC43_USART_HDEN_OFFSET)
|
||||
#define LPC43_USART0_SCICTRL (LPC43_USART0_BASE+LPC43_USART_SCICTRL_OFFSET)
|
||||
#define LPC43_USART0_RS485CTRL (LPC43_USART0_BASE+LPC43_UART_RS485CTRL_OFFSET)
|
||||
#define LPC43_USART0_ADRMATCH (LPC43_USART0_BASE+LPC43_UART_ADRMATCH_OFFSET)
|
||||
#define LPC43_USART0_RS485DLY (LPC43_USART0_BASE+LPC43_UART_RS485DLY_OFFSET)
|
||||
#define LPC43_USART0_SYNCCTRL (LPC43_USART0_BASE+LPC43_USART_SYNCCTRL_OFFSET)
|
||||
#define LPC43_USART0_TER (LPC43_USART0_BASE+LPC43_USART_TER_OFFSET)
|
||||
|
||||
#define LPC43_UART1_RBR (LPC43_UART1_BASE+LPC43_UART_RBR_OFFSET)
|
||||
#define LPC43_UART1_THR (LPC43_UART1_BASE+LPC43_UART_THR_OFFSET)
|
||||
#define LPC43_UART1_DLL (LPC43_UART1_BASE+LPC43_UART_DLL_OFFSET)
|
||||
#define LPC43_UART1_DLM (LPC43_UART1_BASE+LPC43_UART_DLM_OFFSET)
|
||||
#define LPC43_UART1_IER (LPC43_UART1_BASE+LPC43_UART_IER_OFFSET)
|
||||
#define LPC43_UART1_IIR (LPC43_UART1_BASE+LPC43_UART_IIR_OFFSET)
|
||||
#define LPC43_UART1_FCR (LPC43_UART1_BASE+LPC43_UART_FCR_OFFSET)
|
||||
#define LPC43_UART1_LCR (LPC43_UART1_BASE+LPC43_UART_LCR_OFFSET)
|
||||
#define LPC43_UART1_MCR (LPC43_UART1_BASE+LPC43_UART_MCR_OFFSET)
|
||||
#define LPC43_UART1_LSR (LPC43_UART1_BASE+LPC43_UART_LSR_OFFSET)
|
||||
#define LPC43_UART1_MSR (LPC43_UART1_BASE+LPC43_UART_MSR_OFFSET)
|
||||
#define LPC43_UART1_SCR (LPC43_UART1_BASE+LPC43_UART_SCR_OFFSET)
|
||||
#define LPC43_UART1_ACR (LPC43_UART1_BASE+LPC43_UART_ACR_OFFSET)
|
||||
#define LPC43_UART1_FDR (LPC43_UART1_BASE+LPC43_UART_FDR_OFFSET)
|
||||
#define LPC43_UART1_TER (LPC43_UART1_BASE+LPC43_UART_TER_OFFSET)
|
||||
#define LPC43_UART1_RS485CTRL (LPC43_UART1_BASE+LPC43_UART_RS485CTRL_OFFSET)
|
||||
#define LPC43_UART1_ADRMATCH (LPC43_UART1_BASE+LPC43_UART_ADRMATCH_OFFSET)
|
||||
#define LPC43_UART1_RS485DLY (LPC43_UART1_BASE+LPC43_UART_RS485DLY_OFFSET)
|
||||
|
||||
#define LPC43_USART1_RBR (LPC43_USART1_BASE+LPC43_UART_RBR_OFFSET)
|
||||
#define LPC43_USART1_THR (LPC43_USART1_BASE+LPC43_UART_THR_OFFSET)
|
||||
#define LPC43_USART1_DLL (LPC43_USART1_BASE+LPC43_UART_DLL_OFFSET)
|
||||
#define LPC43_USART1_DLM (LPC43_USART1_BASE+LPC43_UART_DLM_OFFSET)
|
||||
#define LPC43_USART1_IER (LPC43_USART1_BASE+LPC43_UART_IER_OFFSET)
|
||||
#define LPC43_USART1_IIR (LPC43_USART1_BASE+LPC43_UART_IIR_OFFSET)
|
||||
#define LPC43_USART1_FCR (LPC43_USART1_BASE+LPC43_UART_FCR_OFFSET)
|
||||
#define LPC43_USART1_LCR (LPC43_USART1_BASE+LPC43_UART_LCR_OFFSET)
|
||||
#define LPC43_USART1_LSR (LPC43_USART1_BASE+LPC43_UART_LSR_OFFSET)
|
||||
#define LPC43_USART1_SCR (LPC43_USART1_BASE+LPC43_UART_SCR_OFFSET)
|
||||
#define LPC43_USART1_ACR (LPC43_USART1_BASE+LPC43_UART_ACR_OFFSET)
|
||||
#define LPC43_USART1_ICR (LPC43_USART1_BASE+LPC43_USART_ICR_OFFSET)
|
||||
#define LPC43_USART1_FDR (LPC43_USART1_BASE+LPC43_UART_FDR_OFFSET)
|
||||
#define LPC43_USART1_OSR (LPC43_USART1_BASE+LPC43_USART_OSR_OFFSET)
|
||||
#define LPC43_USART1_HDEM (LPC43_USART1_BASE+LPC43_USART_HDEN_OFFSET)
|
||||
#define LPC43_USART1_SCICTRL (LPC43_USART1_BASE+LPC43_USART_SCICTRL_OFFSET)
|
||||
#define LPC43_USART1_RS485CTRL (LPC43_USART1_BASE+LPC43_UART_RS485CTRL_OFFSET)
|
||||
#define LPC43_USART1_ADRMATCH (LPC43_USART1_BASE+LPC43_UART_ADRMATCH_OFFSET)
|
||||
#define LPC43_USART1_RS485DLY (LPC43_USART1_BASE+LPC43_UART_RS485DLY_OFFSET)
|
||||
#define LPC43_USART1_SYNCCTRL (LPC43_USART1_BASE+LPC43_USART_SYNCCTRL_OFFSET)
|
||||
#define LPC43_USART1_TER (LPC43_USART1_BASE+LPC43_USART_TER_OFFSET)
|
||||
|
||||
#define LPC43_USART2_RBR (LPC43_USART2_BASE+LPC43_UART_RBR_OFFSET)
|
||||
#define LPC43_USART2_THR (LPC43_USART2_BASE+LPC43_UART_THR_OFFSET)
|
||||
#define LPC43_USART2_DLL (LPC43_USART2_BASE+LPC43_UART_DLL_OFFSET)
|
||||
#define LPC43_USART2_DLM (LPC43_USART2_BASE+LPC43_UART_DLM_OFFSET)
|
||||
#define LPC43_USART2_IER (LPC43_USART2_BASE+LPC43_UART_IER_OFFSET)
|
||||
#define LPC43_USART2_IIR (LPC43_USART2_BASE+LPC43_UART_IIR_OFFSET)
|
||||
#define LPC43_USART2_FCR (LPC43_USART2_BASE+LPC43_UART_FCR_OFFSET)
|
||||
#define LPC43_USART2_LCR (LPC43_USART2_BASE+LPC43_UART_LCR_OFFSET)
|
||||
#define LPC43_USART2_LSR (LPC43_USART2_BASE+LPC43_UART_LSR_OFFSET)
|
||||
#define LPC43_USART2_SCR (LPC43_USART2_BASE+LPC43_UART_SCR_OFFSET)
|
||||
#define LPC43_USART2_ACR (LPC43_USART2_BASE+LPC43_UART_ACR_OFFSET)
|
||||
#define LPC43_USART2_ICR (LPC43_USART2_BASE+LPC43_USART_ICR_OFFSET)
|
||||
#define LPC43_USART2_FDR (LPC43_USART2_BASE+LPC43_UART_FDR_OFFSET)
|
||||
#define LPC43_USART2_OSR (LPC43_USART2_BASE+LPC43_USART_OSR_OFFSET)
|
||||
#define LPC43_USART2_HDEM (LPC43_USART2_BASE+LPC43_USART_HDEN_OFFSET)
|
||||
#define LPC43_USART2_SCICTRL (LPC43_USART2_BASE+LPC43_USART_SCICTRL_OFFSET)
|
||||
#define LPC43_USART2_RS485CTRL (LPC43_USART2_BASE+LPC43_UART_RS485CTRL_OFFSET)
|
||||
#define LPC43_USART2_ADRMATCH (LPC43_USART2_BASE+LPC43_UART_ADRMATCH_OFFSET)
|
||||
#define LPC43_USART2_RS485DLY (LPC43_USART2_BASE+LPC43_UART_RS485DLY_OFFSET)
|
||||
#define LPC43_USART2_SYNCCTRL (LPC43_USART2_BASE+LPC43_USART_SYNCCTRL_OFFSET)
|
||||
#define LPC43_USART2_TER (LPC43_USART2_BASE+LPC43_USART_TER_OFFSET)
|
||||
|
||||
/* Register bit definitions *****************************************************************/
|
||||
|
||||
/* RBR (DLAB =0) Receiver Buffer Register */
|
||||
|
||||
#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* THR (DLAB =0) Transmit Holding Register */
|
||||
|
||||
#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DLL (DLAB =1) Divisor Latch LSB */
|
||||
|
||||
#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DLM (DLAB =1) Divisor Latch MSB */
|
||||
|
||||
#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* IER (DLAB =0) Interrupt Enable Register */
|
||||
|
||||
#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */
|
||||
#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */
|
||||
#define UART_IER_RXIE (1 << 2) /* Bit 2: RX Line Status Interrupt Enable */
|
||||
#define UART_IER_MSIE (1 << 3) /* Bit 3: Modem Status Interrupt Enable (UART only) */
|
||||
/* Bits 4-6: Reserved */
|
||||
#define UART_IER_CTSIE (1 << 7) /* Bit 7: CTS transition interrupt (UART only) */
|
||||
#define UART_IER_ABEOIE (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */
|
||||
#define UART_IER_ABTOIE (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */
|
||||
/* Bits 10-31: Reserved */
|
||||
#define UART_IER_ALLIE (0x038f)
|
||||
#define USART_IER_ALLIE (0x0307)
|
||||
|
||||
/* IIR Interrupt ID Register */
|
||||
|
||||
#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */
|
||||
#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */
|
||||
#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT)
|
||||
# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART only) */
|
||||
# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */
|
||||
# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */
|
||||
# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */
|
||||
# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */
|
||||
/* Bits 4-5: Reserved */
|
||||
#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR[0] */
|
||||
#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT)
|
||||
#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */
|
||||
#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* FCR FIFO Control Register */
|
||||
|
||||
#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */
|
||||
#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */
|
||||
#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */
|
||||
#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA Mode Select */
|
||||
/* Bits 4-5: Reserved */
|
||||
#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */
|
||||
#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT)
|
||||
# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 char) */
|
||||
# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 chars) */
|
||||
# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 chars) */
|
||||
# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 chars) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* LCR Line Control Register */
|
||||
|
||||
#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */
|
||||
#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT)
|
||||
#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */
|
||||
#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */
|
||||
#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */
|
||||
#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT)
|
||||
# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */
|
||||
# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */
|
||||
# define UART_LCR_PS_STICKY1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */
|
||||
# define UART_LCR_PS_STICKY0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */
|
||||
#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */
|
||||
#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* MCR Modem Control Register (UART only) */
|
||||
|
||||
#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */
|
||||
#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */
|
||||
/* Bit 5: Reserved */
|
||||
#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-RTS flow control */
|
||||
#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-CTS flow control */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* LSR Line Status Register */
|
||||
|
||||
#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */
|
||||
#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */
|
||||
#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
|
||||
#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
|
||||
#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
|
||||
#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
|
||||
#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
|
||||
#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */
|
||||
#define USART_LSR_RXFE (1 << 8) /* Bit 8: Error in transmitted char (USART onlY) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* MSR Modem Status Register (UART only) */
|
||||
|
||||
#define UART_MSR_DCTS (1 << 0) /* Bit 0: Delta CTS. CTS state change */
|
||||
#define UART_MSR_DDSR (1 << 1) /* Bit 1: Delta DSR. DSR state change */
|
||||
#define UART_MSR_TERI (1 << 2) /* Bit 2: Trailing Edge RI */
|
||||
#define UART_MSR_DDCD (1 << 3) /* Bit 3: Delta DCD. DCD state change */
|
||||
#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */
|
||||
#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */
|
||||
#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */
|
||||
#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SCR Scratch Pad Register */
|
||||
|
||||
#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* ACR Auto-baud Control Register */
|
||||
|
||||
#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running */
|
||||
#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select */
|
||||
#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */
|
||||
#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* ICA IrDA Control Register (UART0,2,3 only) */
|
||||
|
||||
#define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */
|
||||
#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */
|
||||
#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enable IrDA fixed pulse width mode */
|
||||
#define UART_ICR_PULSEDIV_SHIFT (3) /* Bits 3-5: Configures the pulse when FixPulseEn = 1 */
|
||||
#define UART_ICR_PULSEDIV_MASK (7 << UART_ICR_PULSEDIV_SHIFT)
|
||||
# define UART_ICR_PULSEDIV_2TPCLK (0 << UART_ICR_PULSEDIV_SHIFT) /* 2 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_4TPCLK (1 << UART_ICR_PULSEDIV_SHIFT) /* 4 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_8TPCLK (2 << UART_ICR_PULSEDIV_SHIFT) /* 8 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_16TPCLK (3 << UART_ICR_PULSEDIV_SHIFT) /* 16 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_32TPCLK (4 << UART_ICR_PULSEDIV_SHIFT) /* 32 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_64TPCLK (5 << UART_ICR_PULSEDIV_SHIFT) /* 64 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_128TPCLK (6 << UART_ICR_PULSEDIV_SHIFT) /* 128 x TPCLK */
|
||||
# define UART_ICR_PULSEDIV_256TPCLK (7 << UART_ICR_PULSEDIV_SHIFT) /* 256 x TPCLK */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* FDR Fractional Divider Register */
|
||||
|
||||
#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */
|
||||
#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT)
|
||||
#define UART_FDR_MULVAL_SHIFT (3) /* Bits 4-7 Baud-rate pre-scaler multiplier value */
|
||||
#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Oversampling Register (USART only) */
|
||||
/* Bit 0: Reserved */
|
||||
#define USART_OSR_OSFRAC_SHIFT (1) /* Bits 1-3: Fractional part of the oversampling ratio */
|
||||
#define USART_OSR_OSFRAC_MASK (7 << USART_OSR_OSFRAC_SHIFT)
|
||||
#define USART_OSR_OSINT_SHIFT (4) /* Bits 4-7: Integer part of the oversampling ratio */
|
||||
#define USART_OSR_OSINT_MASK (15 << USART_OSR_OSINT_SHIFT)
|
||||
#define USART_OSR_FDINT_SHIFT (8) /* Bits 8-14: Extension for Smart Card mode */
|
||||
#define USART_OSR_FDINT_MASK (0x7f << USART_OSR_FDINT_SHIFT)
|
||||
/* Bits 15-31: Reserved */
|
||||
/* TER Transmit Enable Register (UART only) */
|
||||
/* Bits 0-6: Reserved */
|
||||
#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Half-duplex enable Register (USART only) */
|
||||
|
||||
#define USART_HDEN_TXEN (1 << 0) /* Bit 0: Half-duplex mode enable */
|
||||
/* Bits 1-31: Reserved */
|
||||
/* Smart card interface control register (USART only) */
|
||||
|
||||
#define USART_SCICTRL_SCIEN (1 << 0) /* Bit 0: Smart Card Interface Enable */
|
||||
#define USART_SCICTRL_NACKDIS (1 << 1) /* Bit 1: NACK response disable */
|
||||
#define USART_SCICTRL_PROTSEL (1 << 2) /* Bit 2: Protocol selection */
|
||||
/* Bits 3-4: Reserved */
|
||||
#define USART_SCICTRL_TXRETRY_SHIFT (5) /* Bits 5-7: Maximum number of retransmissions */
|
||||
#define USART_SCICTRL_TXRETRY_MASK (7 << USART_SCICTRL_TXRETRY_SHIFT)
|
||||
#define USART_SCICTRL_GUARDTIME_SHIFT (8) /* Bits 8-15: Extra guard time */
|
||||
#define USART_SCICTRL_GUARDTIME_MASK (0xff << USART_SCICTRL_GUARDTIME_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
/* RS-485/EIA-485 Control */
|
||||
|
||||
#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */
|
||||
#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */
|
||||
#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */
|
||||
#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */
|
||||
#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */
|
||||
#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* RS-485/EIA-485 address match */
|
||||
|
||||
#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* RS-485/EIA-485 direction control delay */
|
||||
|
||||
#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Firection control (RTS/DTR) delay */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Synchronous mode control register (USART only) */
|
||||
|
||||
#define USART_SYNCCTRL_SYNC (1 << 0) /* Bit 0: Enables synchronous mode */
|
||||
#define USART_SYNCCTRL_CSRC (1 << 1) /* Bit 1: Clock source select */
|
||||
#define USART_SYNCCTRL_FES (1 << 2) /* Bit 2: Falling edge sampling */
|
||||
#define USART_SYNCCTRL_TSBYPASS (1 << 3) /* Bit 3: Transmit synchronization bypass */
|
||||
#define USART_SYNCCTRL_CSCEN (1 << 4) /* Bit 4: Continuous master clock enable */
|
||||
#define USART_SYNCCTRL_SSSDIS (1 << 5) /* Bit 5: Start/stop bits */
|
||||
#define USART_SYNCCTRL_CCCLR (1 << 6) /* Bit 6: Continuous clock clear */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* TER Transmit Enable Register (USART only) */
|
||||
|
||||
#define USART_TER_TXEN (1 << 0) /* Bit 0: TX Enable */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H */
|
||||
|
|
|
|||
|
|
@ -1,111 +1,111 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_wwdt.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_WWDT_MOD_OFFSET 0x0000 /* Watchdog mode register */
|
||||
#define LPC43_WWDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */
|
||||
#define LPC43_WWDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */
|
||||
#define LPC43_WWDT_TV_OFFSET 0x000c /* Watchdog timer value register */
|
||||
#define LPC43_WWDT_WARNINT_OFFSET 0x0014 /* Watchdog warning interrupt register */
|
||||
#define LPC43_WWDT_WINDOW_OFFSET 0x0018 /* Watchdog timer window register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_WWDT_MOD (LPC43_WWDT_BASE+LPC43_WWDT_MOD_OFFSET)
|
||||
#define LPC43_WWDT_TC (LPC43_WWDT_BASE+LPC43_WWDT_TC_OFFSET)
|
||||
#define LPC43_WWDT_FEED (LPC43_WWDT_BASE+LPC43_WWDT_FEED_OFFSET)
|
||||
#define LPC43_WWDT_TV (LPC43_WWDT_BASE+LPC43_WWDT_TV_OFFSET)
|
||||
#define LPC43_WWDT_WDCLKSEL (LPC43_WWDT_BASE+LPC43_WWDT_WDCLKSEL_OFFSET)
|
||||
#define LPC43_WWDT_WARNINT (LPC43_WWDT_BASE+LPC43_WWDT_WARNINT_OFFSET)
|
||||
#define LPC43_WWDT_WINDOW (LPC43_WWDT_BASE+LPC43_WWDT_WINDOW_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Watchdog mode register */
|
||||
|
||||
#define WWDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */
|
||||
#define WWDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */
|
||||
#define WWDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */
|
||||
#define WWDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */
|
||||
#define WWDT_MOD_WDPROTECT (1 << 4) /* Bit 4: Watchdog update mode */
|
||||
/* Bits 5-31: Reserved */
|
||||
/* Watchdog timer constant register */
|
||||
|
||||
#define WWDT_TC_MASK 0x00ffffff /* Bits 0-23: Watchdog time-out value */
|
||||
/* Bits 24-31: Reserved */
|
||||
/* Watchdog feed sequence register */
|
||||
|
||||
#define WWDT_FEED_MASK 0xff /* Bits 0-7: Feed value: 0xaa followed by 0x55 */
|
||||
/* Bits 14-31: Reserved */
|
||||
/* Watchdog timer value register */
|
||||
|
||||
#define WWDT_TV_MASK 0x00ffffff /* Bits 0-23: Counter timer value */
|
||||
/* Bits 24-31: Reserved */
|
||||
/* Watchdog warning interrupt register */
|
||||
|
||||
#define WWDT_WARNINT_MASK 0x03ff /* Bits 0-9: Watchdog warning compare value */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* Watchdog timer window register */
|
||||
|
||||
#define WWDT_WINDOW_MASK 0x00ffffff /* Bits 0-23: Watchdog window value */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_wwdt.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC43_WWDT_MOD_OFFSET 0x0000 /* Watchdog mode register */
|
||||
#define LPC43_WWDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */
|
||||
#define LPC43_WWDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */
|
||||
#define LPC43_WWDT_TV_OFFSET 0x000c /* Watchdog timer value register */
|
||||
#define LPC43_WWDT_WARNINT_OFFSET 0x0014 /* Watchdog warning interrupt register */
|
||||
#define LPC43_WWDT_WINDOW_OFFSET 0x0018 /* Watchdog timer window register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC43_WWDT_MOD (LPC43_WWDT_BASE+LPC43_WWDT_MOD_OFFSET)
|
||||
#define LPC43_WWDT_TC (LPC43_WWDT_BASE+LPC43_WWDT_TC_OFFSET)
|
||||
#define LPC43_WWDT_FEED (LPC43_WWDT_BASE+LPC43_WWDT_FEED_OFFSET)
|
||||
#define LPC43_WWDT_TV (LPC43_WWDT_BASE+LPC43_WWDT_TV_OFFSET)
|
||||
#define LPC43_WWDT_WDCLKSEL (LPC43_WWDT_BASE+LPC43_WWDT_WDCLKSEL_OFFSET)
|
||||
#define LPC43_WWDT_WARNINT (LPC43_WWDT_BASE+LPC43_WWDT_WARNINT_OFFSET)
|
||||
#define LPC43_WWDT_WINDOW (LPC43_WWDT_BASE+LPC43_WWDT_WINDOW_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Watchdog mode register */
|
||||
|
||||
#define WWDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */
|
||||
#define WWDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */
|
||||
#define WWDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */
|
||||
#define WWDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */
|
||||
#define WWDT_MOD_WDPROTECT (1 << 4) /* Bit 4: Watchdog update mode */
|
||||
/* Bits 5-31: Reserved */
|
||||
/* Watchdog timer constant register */
|
||||
|
||||
#define WWDT_TC_MASK 0x00ffffff /* Bits 0-23: Watchdog time-out value */
|
||||
/* Bits 24-31: Reserved */
|
||||
/* Watchdog feed sequence register */
|
||||
|
||||
#define WWDT_FEED_MASK 0xff /* Bits 0-7: Feed value: 0xaa followed by 0x55 */
|
||||
/* Bits 14-31: Reserved */
|
||||
/* Watchdog timer value register */
|
||||
|
||||
#define WWDT_TV_MASK 0x00ffffff /* Bits 0-23: Counter timer value */
|
||||
/* Bits 24-31: Reserved */
|
||||
/* Watchdog warning interrupt register */
|
||||
|
||||
#define WWDT_WARNINT_MASK 0x03ff /* Bits 0-9: Watchdog warning compare value */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* Watchdog timer window register */
|
||||
|
||||
#define WWDT_WINDOW_MASK 0x00ffffff /* Bits 0-23: Watchdog window value */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue