forked from Archive/PX4-Autopilot
Adding LPC43xx header files
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4881 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
314a7cbabc
commit
1b0a8ced06
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@ -58,17 +58,17 @@
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#define LPC31_EVNTRTR_NOUTPUTS 5 /* Outputs o=0-4 (incl CGU Wakeup) */
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#define LPC31_EVNTRTR_NEVENTS (32*LPC31_EVNTRTR_NBANKS)
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#define _B(b) ((b)<<2) /* Maps bank number 0-3 to word offset */
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#define _O(o) ((o)<<5) /* Maps output to bank group offset */
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#define _OB(o,b) (_O(o)+_B(b)) /* Mqpw output and bank to word offset */
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#define _B(b) ((b)<<2) /* Maps bank number 0-3 to word offset */
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#define _O(o) ((o)<<5) /* Maps output to bank group offset */
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#define _OB(o,b) (_O(o)+_B(b)) /* Mqpw output and bank to word offset */
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#define EVNTRTR_EVENT(bank,bit) ((bank)<<5|bit) /* Makes a event number from a bank and bit */
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#define EVNTRTR_BANK(e) ((e)>>5) /* Maps a event to a bank */
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#define EVNTRTR_BIT(e) ((e)&0x1f) /* Maps a event to a bit */
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#define EVNTRTR_EVENT(bank,bit) ((bank)<<5|bit) /* Makes a event number from a bank and bit */
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#define EVNTRTR_BANK(e) ((e)>>5) /* Maps a event to a bank */
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#define EVNTRTR_BIT(e) ((e)&0x1f) /* Maps a event to a bit */
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/* EVNTRTR register offsets (with respect to the EVNTRTR base) ******************************************/
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/* 0x0000-0x0bff: Reserved */
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/* 0x0000-0x0bff: Reserved */
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#define LPC31_EVNTRTR_PEND_OFFSET(b) (0x0c00+_B(b)) /* Input event pending */
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#define LPC31_EVNTRTR_INTCLR_OFFSET(b) (0x0c20+_B(b)) /* Input event clear */
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#define LPC31_EVNTRTR_INTSET_OFFSET(b) (0x0c40+_B(b)) /* Input event set */
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@ -79,7 +79,7 @@
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#define LPC31_EVNTRTR_ATR_OFFSET(b) (0x0ce0+_B(b)) /* Input event activation type */
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#define LPC31_EVNTRTR_RSR_OFFSET(b) (0x0d20+_B(b)) /* Input event raw status */
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#define LPC31_EVNTRTR_INTOUT_OFFSET 0x0d40 /* State of interrupt output pins */
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/* 0x0e00-0x0ffc: Reserved */
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/* 0x0e00-0x0ffc: Reserved */
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#define LPC31_EVNTRTR_INTOUTPEND_OFFSET(o,b) (0x1000+_OB(o,b)) /* Interrupt output 'o' pending */
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#define LPC31_EVNTRTR_CGUWKUPPEND_OFFSET(b) (0x1000+_OB(4,b)) /* cgu_wakeup pending */
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#define LPC31_EVNTRTR_INTOUTMASK_OFFSET(o,b) (0x1400+_OB(o,b)) /* Interrupt output 'o' mask */
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@ -0,0 +1,110 @@
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/************************************************************************************
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* arch/arm/src/lpc43xx/chip/lpc43_aes.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* The AES is controlled through a set of simple API calls located in the LPC43xx
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* ROM. This value holds the pointer to the AES driver table.
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*/
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#define LPC43_ROM_AES_DRIVER_TABLE LPC43_ROM_DRIVER_TABLE2
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/************************************************************************************
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* Public Types
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************************************************************************************/
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enum lpc43_aescmd_e
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{
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AES_API_CMD_ENCODE_ECB = 0,
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AES_API_CMD_DECODE_ECB = 1,
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AES_API_CMD_ENCODE_CBC = 2,
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AES_API_CMD_DECODE_CBC = 3
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};
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struct lpc43_aes_s
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{
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/* Initialize the AES engine */
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void (*aes_Init)(void);
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/* Offset 0x04 -- Defines AES engine operation mode. See enum lpc43_aescmd_e */
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unsigned int (*aes_SetMode)(unsigned int cmd);
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/* Load 128-bit AES user keys */
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void (*aes_LoadKey1)(void);
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void (*aes_LoadKey2)(void);
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/* Loads randomly generated key in AES engine. To update the RNG and load a new
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* random number, use the API call otp_GenRand before aes_LoadKeyRNG.
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*/
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void (*aes_LoadKeyRNG)(void);
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/* Loads 128-bit AES software defined user key (16 bytes) */
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void (*aes_LoadKeySW)(unsigned char *key);
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/* Loads 128-bit AES initialization vector (16 bytes) */
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void (*aes_LoadIV_SW)(unsigned char *iv);
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/* Loads 128-bit AES IC specific initialization vector, which is used to decrypt
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* a boot image.
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*/
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void (*aes_LoadIV_IC)(void);
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};
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H */
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@ -0,0 +1,160 @@
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/************************************************************************************
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* arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define LPC43_EVNTRTR_HILO_OFFSET 0x0000 /* Level configuration register */
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#define LPC43_EVNTRTR_EDGE_OFFSET 0x0004 /* Edge configuration */
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#define LPC43_EVNTRTR_CLREN_OFFSET 0x0fd8 /* Clear event enable register */
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#define LPC43_EVNTRTR_SETEN_OFFSET 0x0fdc /* Set event enable register */
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#define LPC43_EVNTRTR_STATUS_OFFSET 0x0fe0 /* Event Status register */
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#define LPC43_EVNTRTR_ENABLE_OFFSET 0x0fe4 /* Event Enable register */
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#define LPC43_EVNTRTR_CLRSTAT_OFFSET 0x0fe8 /* Clear event status register */
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#define LPC43_EVNTRTR_SETSTAT_OFFSET 0x0fec /* Set event status register */
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/* Register Addresses ***************************************************************/
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#define LPC43_EVNTRTR_HILO (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_HILO_OFFSET)
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#define LPC43_EVNTRTR_EDGE (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_EDGE_OFFSET)
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#define LPC43_EVNTRTR_CLREN (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_CLREN_OFFSET)
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#define LPC43_EVNTRTR_SETEN (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_SETEN_OFFSET)
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#define LPC43_EVNTRTR_STATUS (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_STATUS_OFFSET)
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#define LPC43_EVNTRTR_ENABLE (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_ENABLE_OFFSET)
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#define LPC43_EVNTRTR_CLRSTAT (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_CLRSTAT_OFFSET)
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#define LPC43_EVNTRTR_SETSTAT (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_SETSTAT_OFFSET)
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/* Register Bit Definitions *********************************************************/
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/* Event router inputs. Bit settings common to all registers */
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#define EVNTRTR_SOURCE_WAKEUP0 0 /* WAKEUP0 pin */
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#define EVNTRTR_SOURCE_WAKEUP1 1 /* WAKEUP1 pin */
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#define EVNTRTR_SOURCE_WAKEUP2 2 /* WAKEUP2 pin */
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#define EVNTRTR_SOURCE_WAKEUP3 3 /* WAKEUP3 pin */
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#define EVNTRTR_SOURCE_ATIMER 4 /* Alarm timer interrupt */
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#define EVNTRTR_SOURCE_RTC 5 /* RTC interrupt and event recorder/monitor interrupt */
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#define EVNTRTR_SOURCE_BOD 6 /* BOD trip level 1interrupt */
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#define EVNTRTR_SOURCE_WWDT 7 /* WWDT interrupt */
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#define EVNTRTR_SOURCE_ETHERNET 8 /* Ethernet wake-up packet indicator */
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#define EVNTRTR_SOURCE_USB0 9 /* USB0 wake-up request signal */
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#define EVNTRTR_SOURCE_USB1 10 /* USB1 AHB_NEED_CLK signal */
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#define EVNTRTR_SOURCE_SDMMC 11 /* SD/MMC interrupt */
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#define EVNTRTR_SOURCE_CAN 12 /* C_CAN0 | C_CAN1 interrupt */
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#define EVNTRTR_SOURCE_TIM2 13 /* Combined timer output 2 (SCT output 2 | TIMER0 Ch2) */
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#define EVNTRTR_SOURCE_TIM6 14 /* Combined timer output 6 (SCT output 6 | TIMER1 Ch2) */
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#define EVNTRTR_SOURCE_QEI 15 /* QEI interrupt */
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#define EVNTRTR_SOURCE_TIM14 16 /* Combined timer output 14 (SCT output 14 | TIMER3 Ch2) */
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/* 17-18: Reserved */
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#define EVNTRTR_SOURCE_RESET 19 /* Reset event */
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#define EVNTRTR_WAKEUP0 (1 << EVNTRTR_SOURCE_WAKEUP0)
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#define EVNTRTR_WAKEUP1 (1 << EVNTRTR_SOURCE_WAKEUP1)
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#define EVNTRTR_WAKEUP2 (1 << EVNTRTR_SOURCE_WAKEUP2)
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#define EVNTRTR_WAKEUP3 (1 << EVNTRTR_SOURCE_WAKEUP3)
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#define EVNTRTR_ATIMER (1 << EVNTRTR_SOURCE_ATIMER)
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#define EVNTRTR_RTC (1 << EVNTRTR_SOURCE_RTC)
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#define EVNTRTR_BOD (1 << EVNTRTR_SOURCE_BOD)
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#define EVNTRTR_WWDT (1 << EVNTRTR_SOURCE_WWDT)
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#define EVNTRTR_ETH (1 << EVNTRTR_SOURCE_ETHERNET)
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#define EVNTRTR_USB0 (1 << EVNTRTR_SOURCE_USB0)
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#define EVNTRTR_USB1 (1 << EVNTRTR_SOURCE_USB1)
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#define EVNTRTR_SDMMC (1 << EVNTRTR_SOURCE_SDMMC)
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#define EVNTRTR_CAN (1 << EVNTRTR_SOURCE_CAN)
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#define EVNTRTR_TIM2 (1 << EVNTRTR_SOURCE_TIM2)
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#define EVNTRTR_TIM6 (1 << EVNTRTR_SOURCE_TIM6)
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#define EVNTRTR_QEI (1 << EVNTRTR_SOURCE_QEI)
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#define EVNTRTR_TIM14 (1 << EVNTRTR_SOURCE_TIM14)
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#define EVNTRTR_RESET (1 << EVNTRTR_SOURCE_RESET)
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/* Level configuration register */
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#define EVNTRTR_HILO(n) (1 << (n))
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/* Edge configuration */
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#define EVNTRTR_EDGE(n) (1 << (n))
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/* Clear event enable register */
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#define EVNTRTR_CLREN(n) (1 << (n))
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/* Set event enable register */
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#define EVNTRTR_SETEN(n) (1 << (n))
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/* Event Status register */
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#define EVNTRTR_STATUS(n) (1 << (n))
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/* Event Enable register */
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#define EVNTRTR_ENABLE(n) (1 << (n))
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/* Clear event status register */
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#define EVNTRTR_CLRSTAT(n) (1 << (n))
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/* Set event status register */
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#define EVNTRTR_SETSTAT(n) (1 << (n))
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H */
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@ -1,5 +1,5 @@
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/************************************************************************************
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* arch/arm/src/lpc43xx/chip.h
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* arch/arm/src/lpc43xx/chip/lpc43_memorymap.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -73,6 +73,18 @@
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#define LPC43_EXTMEM_CS2_BASE (LPC43_LOCSRAM_BASE + 0x0e000000)
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#define LPC43_EXTMEM_CS3_BASE (LPC43_LOCSRAM_BASE + 0x0f000000)
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/* ROM Driver Table */
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#define LPC43_ROM_DRIVER_TABLE (LPC43_ROM_BASE+0x00000100)
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#define LPC43_ROM_DRIVER_TABLE0 (LPC43_ROM_DRIVER_TABLE+0x0000)
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#define LPC43_ROM_DRIVER_TABLE1 (LPC43_ROM_DRIVER_TABLE+0x0004)
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#define LPC43_ROM_DRIVER_TABLE2 (LPC43_ROM_DRIVER_TABLE+0x0008)
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#define LPC43_ROM_DRIVER_TABLE3 (LPC43_ROM_DRIVER_TABLE+0x000c)
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#define LPC43_ROM_DRIVER_TABLE4 (LPC43_ROM_DRIVER_TABLE+0x0010)
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#define LPC43_ROM_DRIVER_TABLE5 (LPC43_ROM_DRIVER_TABLE+0x0014)
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#define LPC43_ROM_DRIVER_TABLE6 (LPC43_ROM_DRIVER_TABLE+0x0018)
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#define LPC43_ROM_DRIVER_TABLE7 (LPC43_ROM_DRIVER_TABLE+0x001c)
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/* AHB SRAM */
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#define LPC43_AHBSRAM_BANK0_BASE (LPC43_AHBSRAM_BASE)
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@ -112,7 +124,7 @@
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#define LPC43_BACKUP_BASE (LPC43_RTCPERIPH_BASE + 0x00001000)
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#define LPC43_PWRMODE_BASE (LPC43_RTCPERIPH_BASE + 0x00002000)
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#define LPC43_CREG_BASE (LPC43_RTCPERIPH_BASE + 0x00003000)
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#define LPC43_EVROUTER_BASE (LPC43_RTCPERIPH_BASE + 0x00004000)
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#define LPC43_EVNTRTR_BASE (LPC43_RTCPERIPH_BASE + 0x00004000)
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#define LPC43_OTPC_BASE (LPC43_RTCPERIPH_BASE + 0x00005000)
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#define LPC43_RTC_BASE (LPC43_RTCPERIPH_BASE + 0x00006000)
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@ -0,0 +1,192 @@
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/************************************************************************************
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* arch/arm/src/lpc43xx/chip/lpc43_otp.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define LPC43_OTP_MEM00_OFFSET 0x0010 /* General purpose OTP memory 0, word 0 */
|
||||
#define LPC43_OTP_MEM01_OFFSET 0x0014 /* General purpose OTP memory 0, word 1 */
|
||||
#define LPC43_OTP_MEM02_OFFSET 0x0018 /* General purpose OTP memory 0, word 2 */
|
||||
#define LPC43_OTP_MEM03_OFFSET 0x001c /* General purpose OTP memory 0, word 3 */
|
||||
|
||||
#define LPC43_OTP_MEM10_OFFSET 0x0020 /* General purpose OTP memory 1, word 0 */
|
||||
#define LPC43_OTP_MEM11_OFFSET 0x0024 /* General purpose OTP memory 1, word 1 */
|
||||
#define LPC43_OTP_MEM12_OFFSET 0x0028 /* General purpose OTP memory 1, word 2 */
|
||||
#define LPC43_OTP_MEM13_OFFSET 0x002c /* General purpose OTP memory 1, word 3 */
|
||||
|
||||
#define LPC43_OTP_MEM20_OFFSET 0x0034 /* General purpose OTP memory 2, word 0 */
|
||||
#define LPC43_OTP_MEM21_OFFSET 0x0038 /* General purpose OTP memory 2, word 1 */
|
||||
#define LPC43_OTP_MEM22_OFFSET 0x003c /* General purpose OTP memory 2, word 2 */
|
||||
|
||||
#define LPC43_OTP_AES00_OFFSET 0x0010 /* AES key 0, word 0 */
|
||||
#define LPC43_OTP_AES01_OFFSET 0x0014 /* AES key 0, word 1 */
|
||||
#define LPC43_OTP_AES02_OFFSET 0x0018 /* AES key 0, word 2 */
|
||||
#define LPC43_OTP_AES03_OFFSET 0x001c /* AES key 0, word 3 */
|
||||
|
||||
#define LPC43_OTP_AES10_OFFSET 0x0020 /* AES key 1, word 0 */
|
||||
#define LPC43_OTP_AES11_OFFSET 0x0024 /* AES key 1, word 1 */
|
||||
#define LPC43_OTP_AES12_OFFSET 0x0028 /* AES key 1, word 2 */
|
||||
#define LPC43_OTP_AES13_OFFSET 0x002c /* AES key 1, word 3 */
|
||||
|
||||
#define LPC43_OTP_CCD_OFFSET 0x0030 /* Customer control data */
|
||||
#define LPC43_OTP_USBID_OFFSET 0x0034 /* USB ID */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define LPC43_OTP_MEM00 (LPC43_OTPC_BASE+LPC43_OTP_MEM00_OFFSET)
|
||||
#define LPC43_OTP_MEM01 (LPC43_OTPC_BASE+LPC43_OTP_MEM01_OFFSET)
|
||||
#define LPC43_OTP_MEM02 (LPC43_OTPC_BASE+LPC43_OTP_MEM02_OFFSET)
|
||||
#define LPC43_OTP_MEM03 (LPC43_OTPC_BASE+LPC43_OTP_MEM03_OFFSET)
|
||||
|
||||
#define LPC43_OTP_MEM10 (LPC43_OTPC_BASE+LPC43_OTP_MEM10_OFFSET)
|
||||
#define LPC43_OTP_MEM11 (LPC43_OTPC_BASE+LPC43_OTP_MEM11_OFFSET)
|
||||
#define LPC43_OTP_MEM12 (LPC43_OTPC_BASE+LPC43_OTP_MEM12_OFFSET)
|
||||
#define LPC43_OTP_MEM13 (LPC43_OTPC_BASE+LPC43_OTP_MEM13_OFFSET)
|
||||
|
||||
#define LPC43_OTP_MEM20 (LPC43_OTPC_BASE+LPC43_OTP_MEM20_OFFSET)
|
||||
#define LPC43_OTP_MEM21 (LPC43_OTPC_BASE+LPC43_OTP_MEM21_OFFSET)
|
||||
#define LPC43_OTP_MEM22 (LPC43_OTPC_BASE+LPC43_OTP_MEM22_OFFSET)
|
||||
|
||||
#define LPC43_OTP_AES00 (LPC43_OTPC_BASE+LPC43_OTP_AES00_OFFSET)
|
||||
#define LPC43_OTP_AES01 (LPC43_OTPC_BASE+LPC43_OTP_AES01_OFFSET)
|
||||
#define LPC43_OTP_AES02 (LPC43_OTPC_BASE+LPC43_OTP_AES02_OFFSET)
|
||||
#define LPC43_OTP_AES03 (LPC43_OTPC_BASE+LPC43_OTP_AES03_OFFSET)
|
||||
|
||||
#define LPC43_OTP_AES10 (LPC43_OTPC_BASE+LPC43_OTP_AES10_OFFSET)
|
||||
#define LPC43_OTP_AES11 (LPC43_OTPC_BASE+LPC43_OTP_AES11_OFFSET)
|
||||
#define LPC43_OTP_AES12 (LPC43_OTPC_BASE+LPC43_OTP_AES12_OFFSET)
|
||||
#define LPC43_OTP_AES13 (LPC43_OTPC_BASE+LPC43_OTP_AES13_OFFSET)
|
||||
|
||||
#define LPC43_OTP_CCD (LPC43_OTPC_BASE+LPC43_OTP_CCD_OFFSET)
|
||||
#define LPC43_OTP_USBID (LPC43_OTPC_BASE+LPC43_OTP_USBID_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *********************************************************/
|
||||
|
||||
/* Customer control data */
|
||||
/* Bits 0-22: Reserved */
|
||||
#define OTP_CCD_USBID (1 << 23) /* Bit 23: USB ID enable */
|
||||
/* Bit 24: Reserved */
|
||||
#define OPT_CCD_BOOTSRC_SHIFT (25) /* Bits 25-28: Boot source selection in OTP */
|
||||
#define OPT_CCD_BOOTSRC_MASK (15 << OPT_CCD_BOOTSRC_SHIFT)
|
||||
# define OPT_CCD_BOOTSRC_EXT (0 << OPT_CCD_BOOTSRC_SHIFT) /* External pins */
|
||||
# define OPT_CCD_BOOTSRC_UART0 (1 << OPT_CCD_BOOTSRC_SHIFT) /* UART0 */
|
||||
# define OPT_CCD_BOOTSRC_EMC8 (3 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 8-bit */
|
||||
# define OPT_CCD_BOOTSRC_EMC16 (4 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 16-bit */
|
||||
# define OPT_CCD_BOOTSRC_EMC32 (5 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 32-bit */
|
||||
# define OPT_CCD_BOOTSRC_USB0 (6 << OPT_CCD_BOOTSRC_SHIFT) /* USB0 */
|
||||
# define OPT_CCD_BOOTSRC_USB1 (7 << OPT_CCD_BOOTSRC_SHIFT) /* USB1 */
|
||||
# define OPT_CCD_BOOTSRC_SPI (8 << OPT_CCD_BOOTSRC_SHIFT) /* SPI (via SSP) */
|
||||
# define OPT_CCD_BOOTSRC_UART3 (9 << OPT_CCD_BOOTSRC_SHIFT) /* UART3 */
|
||||
/* Bits 29-30: Reserved */
|
||||
#define OTP_CCD_JTAGDIS (1 << 31) /* Bit 31: JTAG disable */
|
||||
|
||||
/* USB ID */
|
||||
|
||||
#define OTP_USBID_VID_SHIFT (0) /* Bits 0-15: USB vendor ID */
|
||||
#define OTP_USBID_VID_MASK (0xffff << OTP_USBID_VID_SHIFT)
|
||||
#define OTP_USBID_PID_SHIFT (0) /* Bits 16-31: USB product ID */
|
||||
#define OTP_USBID_PID_MASK (0xffff << OTP_USBID_PID_SHIFT)
|
||||
|
||||
/* OTP API *************************************************************************/
|
||||
/* The AES is controlled through a set of simple API calls located in the LPC43xx
|
||||
* ROM. This value holds the pointer to the OTP driver table.
|
||||
*/
|
||||
|
||||
#define LPC43_ROM_OTP_DRIVER_TABLE LPC43_ROM_DRIVER_TABLE1
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
struct lpc43_otp_s
|
||||
{
|
||||
/* Initializes the OTP controller */
|
||||
|
||||
unsigned int (*otp_Init)(void);
|
||||
|
||||
/* Programs boot source */
|
||||
|
||||
unsigned int (*otp_ProgBootSrc)(unsigned int src);
|
||||
|
||||
/* JTAG disable. This command disables JTAG only when the device is AES capable. */
|
||||
|
||||
unsigned int (*otp_ProgJTAGDis)(void);
|
||||
|
||||
/* Programs USB_ID */
|
||||
|
||||
unsigned int (*otp_ProgUSBID)(unsigned int pid, unsigned int vid);
|
||||
|
||||
/* Reserved */
|
||||
|
||||
void *reserved[3];
|
||||
|
||||
/* Program the general purpose OTP memories. Use only if the device is not AES
|
||||
* capable.
|
||||
*/
|
||||
|
||||
unsigned int (*otp_ProgGP0)(unsigned int data, unsigned int mask);
|
||||
unsigned int (*otp_ProgGP1)(unsigned int data, unsigned int mask);
|
||||
unsigned int (*otp_ProgGP2)(unsigned int data, unsigned int mask);
|
||||
|
||||
/* Program AES keys. 16 byte keys are expected. */
|
||||
|
||||
unsigned int (*otp_ProgKey1)(unsigned char *key);
|
||||
unsigned int (*otp_ProgKey2)(unsigned char *key);
|
||||
|
||||
/* Generate new random number using the hardware Random Number Generator (RNG). */
|
||||
|
||||
unsigned int (*otp_GenRand)(void);
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H */
|
||||
|
|
@ -805,6 +805,15 @@ Where <subdir> is one of the following:
|
|||
|
||||
CONFIG_STM32_BUILDROOT=y : NuttX buildroot under Linux or Cygwin
|
||||
|
||||
pm:
|
||||
--
|
||||
This is a configuration that is used to test STM32 power management, i.e.,
|
||||
to test that the board can go into lower and lower states of power usage
|
||||
as a result of inactivity. This configuration is based on the nsh2
|
||||
configuration with modifications for testing power management.
|
||||
|
||||
CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows
|
||||
|
||||
RIDE
|
||||
----
|
||||
This configuration builds a trivial bring-up binary. It is
|
||||
|
|
|
|||
Loading…
Reference in New Issue