forked from Archive/PX4-Autopilot
Merge whitespace and comments so that we are closer to in sync with trunk.
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px4dev
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0c7c32ce95
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@ -281,7 +281,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t statu
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static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
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enum stm32_trace_e event, uint32_t parm);
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static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
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#endif
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#endif /* CONFIG_I2C_TRACE */
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static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
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uint32_t frequency);
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static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
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@ -291,7 +291,7 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
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#ifdef I2C1_FSMC_CONFLICT
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static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv);
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static inline void stm32_i2c_enablefsmc(uint32_t ahbenr);
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#endif
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#endif /* I2C1_FSMC_CONFLICT */
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static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
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#ifndef CONFIG_I2C_POLLED
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#ifdef CONFIG_STM32_I2C1
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@ -582,15 +582,14 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int
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abstime.tv_sec++;
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abstime.tv_nsec -= 1000 * 1000 * 1000;
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}
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#else
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#if CONFIG_STM32_I2CTIMEOMS > 0
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#elif CONFIG_STM32_I2CTIMEOMS > 0
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abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000;
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if (abstime.tv_nsec > 1000 * 1000 * 1000)
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{
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abstime.tv_sec++;
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abstime.tv_nsec -= 1000 * 1000 * 1000;
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}
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#endif
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#endif
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/* Wait until either the transfer is complete or the timeout expires */
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@ -932,7 +931,7 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
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{
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/* Fast mode speed calculation with Tlow/Thigh = 16/9 */
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#ifdef CONFIG_I2C_DUTY16_9
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#ifdef CONFIG_STM32_I2C_DUTY16_9
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speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25));
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/* Set DUTY and fast speed bits */
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@ -1071,7 +1070,7 @@ static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv)
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/* Is this I2C1 */
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#ifdef CONFIG_STM32_I2C2
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#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3)
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if (priv->config->base == STM32_I2C1_BASE)
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#endif
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{
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@ -1198,26 +1197,29 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
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{
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stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
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/* No interrupts or context switches may occur in the following
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* sequence. Otherwise, additional bytes may be sent by the
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* device.
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*/
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#ifdef CONFIG_I2C_POLLED
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irqstate_t state = irqsave();
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#endif
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/* Receive a byte */
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*priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
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/* Disable acknowledge when last byte is to be received */
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priv->dcnt--;
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if (priv->dcnt == 1)
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{
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stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0);
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}
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priv->dcnt--;
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#ifdef CONFIG_I2C_POLLED
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irqrestore(state);
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#endif
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}
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}
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@ -1408,7 +1410,6 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
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/* Enable power and reset the peripheral */
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modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit);
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modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit);
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modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0);
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@ -1461,17 +1462,23 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
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stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0);
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/* Unconfigure GPIO pins */
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stm32_unconfiggpio(priv->config->scl_pin);
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stm32_unconfiggpio(priv->config->sda_pin);
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/* Disable and detach interrupts */
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#ifndef CONFIG_I2C_POLLED
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up_disable_irq(priv->config->ev_irq);
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up_disable_irq(priv->config->er_irq);
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irq_detach(priv->config->ev_irq);
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irq_detach(priv->config->er_irq);
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#endif
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modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
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/* Disable clocking */
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modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
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return OK;
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}
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@ -1623,7 +1630,9 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
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*/
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stm32_i2c_clrstart(priv);
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// XXX also clear busy flag in case of timeout
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/* Clear busy flag in case of timeout */
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status = priv->status & 0xffff;
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}
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else
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@ -2070,4 +2079,4 @@ out:
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return ret;
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}
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#endif /* defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) */
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#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */
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