forked from Archive/PX4-Autopilot
l3gd20: use highest possible on-chip filter bandwidth
this allows the software filter to do its job properly
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@ -92,9 +92,12 @@ static const int ERROR = -1;
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#define REG1_RATE_LP_MASK 0xF0 /* Mask to guard partial register update */
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/* keep lowpass low to avoid noise issues */
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#define RATE_95HZ_LP_25HZ ((0<<7) | (0<<6) | (0<<5) | (1<<4))
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#define RATE_190HZ_LP_25HZ ((0<<7) | (1<<6) | (1<<5) | (1<<4))
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#define RATE_190HZ_LP_25HZ ((0<<7) | (1<<6) | (0<<5) | (1<<4))
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#define RATE_190HZ_LP_70HZ ((0<<7) | (1<<6) | (1<<5) | (1<<4))
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#define RATE_380HZ_LP_20HZ ((1<<7) | (0<<6) | (1<<5) | (0<<4))
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#define RATE_380HZ_LP_100HZ ((1<<7) | (0<<6) | (1<<5) | (1<<4))
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#define RATE_760HZ_LP_30HZ ((1<<7) | (1<<6) | (0<<5) | (0<<4))
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#define RATE_760HZ_LP_100HZ ((1<<7) | (1<<6) | (1<<5) | (1<<4))
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#define ADDR_CTRL_REG2 0x21
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#define ADDR_CTRL_REG3 0x22
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@ -659,16 +662,15 @@ L3GD20::set_samplerate(unsigned frequency)
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} else if (frequency <= 200) {
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_current_rate = 190;
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bits |= RATE_190HZ_LP_25HZ;
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bits |= RATE_190HZ_LP_70HZ;
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} else if (frequency <= 400) {
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_current_rate = 380;
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bits |= RATE_380HZ_LP_20HZ;
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bits |= RATE_380HZ_LP_100HZ;
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} else if (frequency <= 800) {
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_current_rate = 760;
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bits |= RATE_760HZ_LP_30HZ;
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bits |= RATE_760HZ_LP_100HZ;
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} else {
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return -EINVAL;
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}
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@ -732,7 +734,7 @@ L3GD20::reset()
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* callback fast enough to not miss data. */
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write_reg(ADDR_FIFO_CTRL_REG, FIFO_CTRL_BYPASS_MODE);
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set_samplerate(L3GD20_DEFAULT_RATE);
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set_samplerate(0); // 760Hz
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set_range(L3GD20_DEFAULT_RANGE_DPS);
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set_driver_lowpass_filter(L3GD20_DEFAULT_RATE, L3GD20_DEFAULT_FILTER_FREQ);
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