Andrew Tridgell 38e9bd5336 SITL: provide simulation timestamp from JSBSim		2015-03-24 08:06:50 -07:00
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fgout_template.xml	autotest: added templates for JSBSim port numbers	2013-08-15 09:47:24 +10:00
rascal_test_template.xml	autotest: added templates for JSBSim port numbers	2013-08-15 09:47:24 +10:00
runsim.py	SITL: provide simulation timestamp from JSBSim	2015-03-24 08:06:50 -07:00