10a612566a
enable TIM4 in shared mode on IOMCU for dshot stop the PWM peripheral in rcout DMA swapping on IOMCU to prevent UART corruption provide debugging options on iomcu dshot support unshared DMA with iomcu dshot optimize rcout on iomcu tune iomcu stack for 8 channels
52 lines
1.7 KiB
Plaintext
52 lines
1.7 KiB
Plaintext
# hw definition file for processing by chibios_pins.py
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include ../iomcu/hwdef.dat
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undef AP_FASTBOOT_ENABLED AP_BOOTLOADER_FLASHING_ENABLED
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undef HAL_DSHOT_ENABLED
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# PPM uses a DMA channel that is required for TIM2, and no remapping of PA8 is possible
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undef PA8
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undef STM32_ICU_USE_TIM1 RCIN_ICU_TIMER STM32_RCIN_DMA_STREAM HAL_USE_ICU
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undef PORT_INT_REQUIRED_STACK MAIN_STACK
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undef CH_CFG_ST_TIMEDELTA CH_CFG_ST_FREQUENCY
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undef AP_HAL_SHARED_DMA_ENABLED
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define HAL_NO_LED_THREAD 1
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# TIM2_UP required for PWM1/2
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define STM32_TIM_TIM2_UP_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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define STM32_TIM_TIM2_UP_DMA_CHAN 1
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# TIM4_UP (PWM 3/4) cannot be used with sharin as channels used by high speed USART2 RX/TX
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define AP_HAL_SHARED_DMA_ENABLED 1
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define STM32_TIM_TIM4_UP_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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define STM32_TIM_TIM4_UP_DMA_CHAN 1
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define SHARED_DMA_MASK (1U<<STM32_TIM_TIM4_UP_DMA_STREAM)
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# TIM3_UP required for PWM5-8
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define STM32_TIM_TIM3_UP_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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define STM32_TIM_TIM3_UP_DMA_CHAN 1
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define NO_FASTBOOT
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define HAL_WITH_DSP FALSE
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define HAL_DSHOT_ENABLED TRUE
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define HAL_SERIALLED_ENABLED FALSE
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# Tickless mode is required in order for the virtual timers used by dshot to work correctly
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STM32_ST_USE_TIMER 15
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define CH_CFG_ST_RESOLUTION 16
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define CH_CFG_ST_TIMEDELTA 2
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define CH_CFG_ST_FREQUENCY 1000000
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# ChibiOS already correctly sets stack sizes and considers 64 extra as conservative
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define PORT_INT_REQUIRED_STACK 64
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# "main" stack is only used for exceptions and ISR, but they can be nested
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MAIN_STACK 0x180
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# defines to allow the loop timing to be observed with a Saleae
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#define IOMCU_LOOP_TIMING_DEBUG 1
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#undef PB0 PB1
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#PB0 PINIO1 OUTPUT GPIO(107) LOW
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#PB1 PINIO2 OUTPUT GPIO(108) LOW
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